JP2007005782A5 - - Google Patents

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Publication number
JP2007005782A5
JP2007005782A5 JP2006145085A JP2006145085A JP2007005782A5 JP 2007005782 A5 JP2007005782 A5 JP 2007005782A5 JP 2006145085 A JP2006145085 A JP 2006145085A JP 2006145085 A JP2006145085 A JP 2006145085A JP 2007005782 A5 JP2007005782 A5 JP 2007005782A5
Authority
JP
Japan
Prior art keywords
conductive layer
layer
opening
conductive
signal wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2006145085A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007005782A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2006145085A priority Critical patent/JP2007005782A/ja
Priority claimed from JP2006145085A external-priority patent/JP2007005782A/ja
Publication of JP2007005782A publication Critical patent/JP2007005782A/ja
Publication of JP2007005782A5 publication Critical patent/JP2007005782A5/ja
Withdrawn legal-status Critical Current

Links

JP2006145085A 2005-05-27 2006-05-25 半導体装置及び半導体装置の作製方法 Withdrawn JP2007005782A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006145085A JP2007005782A (ja) 2005-05-27 2006-05-25 半導体装置及び半導体装置の作製方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005156443 2005-05-27
JP2006145085A JP2007005782A (ja) 2005-05-27 2006-05-25 半導体装置及び半導体装置の作製方法

Publications (2)

Publication Number Publication Date
JP2007005782A JP2007005782A (ja) 2007-01-11
JP2007005782A5 true JP2007005782A5 (fr) 2009-06-18

Family

ID=37691035

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006145085A Withdrawn JP2007005782A (ja) 2005-05-27 2006-05-25 半導体装置及び半導体装置の作製方法

Country Status (1)

Country Link
JP (1) JP2007005782A (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5306705B2 (ja) * 2008-05-23 2013-10-02 株式会社半導体エネルギー研究所 半導体装置
US7821068B2 (en) * 2008-08-18 2010-10-26 Xerox Corporation Device and process involving pinhole undercut area
WO2010038599A1 (fr) 2008-10-01 2010-04-08 Semiconductor Energy Laboratory Co., Ltd. Dispositif à semi-conducteur
JP5729186B2 (ja) 2011-07-14 2015-06-03 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP2014120710A (ja) * 2012-12-19 2014-06-30 Nippon Telegr & Teleph Corp <Ntt> 多層高周波伝送線路およびその製造方法
US9654094B2 (en) 2014-03-12 2017-05-16 Kabushiki Kaisha Toshiba Semiconductor switch circuit and semiconductor substrate

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04313300A (ja) * 1991-04-10 1992-11-05 Sumitomo Electric Ind Ltd フレキシブルプリント配線板
JPH0547767A (ja) * 1991-08-19 1993-02-26 Yamaha Corp 集積回路装置の配線構造
JP2904135B2 (ja) * 1996-06-25 1999-06-14 富士ゼロックス株式会社 プリント配線板
JP4158008B2 (ja) * 1999-11-16 2008-10-01 セイコーエプソン株式会社 半導体チップの製造方法
JP2002109487A (ja) * 2000-09-28 2002-04-12 Denso Corp Ｉｃカード
JP4063533B2 (ja) * 2001-12-10 2008-03-19 日本碍子株式会社 フレキシブル配線板
JP4566578B2 (ja) * 2003-02-24 2010-10-20 株式会社半導体エネルギー研究所 薄膜集積回路の作製方法

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