JP2007005782A5 - - Google Patents
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- JP2007005782A5 JP2007005782A5 JP2006145085A JP2006145085A JP2007005782A5 JP 2007005782 A5 JP2007005782 A5 JP 2007005782A5 JP 2006145085 A JP2006145085 A JP 2006145085A JP 2006145085 A JP2006145085 A JP 2006145085A JP 2007005782 A5 JP2007005782 A5 JP 2007005782A5
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- Prior art keywords
- conductive layer
- layer
- opening
- conductive
- signal wiring
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- 239000010408 film Substances 0.000 claims 10
- 239000000758 substrate Substances 0.000 claims 10
- 238000004519 manufacturing process Methods 0.000 claims 7
- 238000000034 method Methods 0.000 claims 5
- 239000010409 thin film Substances 0.000 claims 2
- 238000009413 insulation Methods 0.000 claims 1
Claims (14)
前記第2の導電層は、前記開口において前記第1の導電層と接しており、
前記第1の導電層は、前記信号配線層と第2の絶縁層を介して重なっていることを特徴とするRFIDタグ。 A first conductive layer on a first insulating layer over a flexible substrate; a second insulating layer including an opening reaching the first conductive layer on the first conductive layer; A signal wiring layer electrically connecting the integrated circuit portion and the antenna on the two insulating layers and a second conductive layer adjacent to the signal wiring layer;
The second conductive layer is in contact with the first conductive layer in the opening;
The RFID tag, wherein the first conductive layer overlaps with the signal wiring layer via a second insulating layer.
前記第1の導電層は、前記第1の開口において前記第2の導電層と、前記第2の開口において前記第3の導電層と、それぞれ接していることを特徴とするRFIDタグ。 A first conductive layer on a first insulating layer over a flexible substrate, and a first opening and a second opening reaching the first conductive layer on the first conductive layer. Two insulating layers, a signal wiring layer electrically connecting the integrated circuit portion and the antenna on the second insulating layer, a second conductive layer adjacent to the signal wiring layer, and a third A conductive layer,
The RFID tag , wherein the first conductive layer is in contact with the second conductive layer in the first opening and the third conductive layer in the second opening.
前記第2の導電層は、前記開口において前記第1の導電層と接しており、
前記第2の導電層は、前記信号配線層と第2の絶縁層を介して重なっていることを特徴とするRFIDタグ。 A signal wiring layer for electrically connecting an integrated circuit portion and an antenna on a first insulating layer on a flexible substrate; a first conductive layer adjacent to the signal wiring layer; the signal wiring layer; A second insulating layer including an opening reaching the first conductive layer on the first conductive layer; and a second conductive layer on the second insulating layer;
The second conductive layer is in contact with the first conductive layer in the opening;
The RFID tag, wherein the second conductive layer overlaps with the signal wiring layer via a second insulating layer.
前記第3の導電層は、前記第1の開口において前記第1の導電層と、前記第2の開口において前記第2の導電層と、それぞれ接していることを特徴とするRFIDタグ。 A signal wiring layer for electrically connecting the integrated circuit portion and the antenna on the first insulating layer on the flexible substrate, and the first conductive layer and the second adjacent to each other with the signal wiring layer interposed therebetween A second opening reaching the first conductive layer and a second conductive layer on the signal wiring layer, the first conductive layer, and the second conductive layer. A second insulating layer including an opening; and a third conductive layer on the second insulating layer;
The RFID tag, wherein the third conductive layer is in contact with the first conductive layer in the first opening and the second conductive layer in the second opening.
前記第1の導電層は、前記第1の開口において前記第2の導電層と、前記第2の開口において前記第3の導電層とそれぞれ接し、
前記第4の導電層は、前記第3の開口において前記第2の導電層と、前記第4の開口において前記第3の導電層とそれぞれ接していることを特徴とするRFIDタグ。 A first conductive layer on a first insulating layer over a flexible substrate; a second insulating layer including a first opening and a second opening on the first conductive layer; A signal wiring layer for electrically connecting the integrated circuit portion and the antenna on two insulating layers, a second conductive layer and a third conductive layer adjacent to each other with the signal wiring layer interposed therebetween, and the signal wiring layer A third insulating layer including a third opening reaching the second conductive layer and a fourth opening reaching the third conductive layer on the second conductive layer and the third conductive layer; and A fourth conductive layer on the third insulating layer;
The first conductive layer is in contact with the second conductive layer in the first opening, and the third conductive layer in the second opening, respectively.
The RFID tag , wherein the fourth conductive layer is in contact with the second conductive layer in the third opening and the third conductive layer in the fourth opening.
前記第1の導電層上に前記第1の導電層に達する開口を含む第2の絶縁層を形成し、
前記第2の絶縁層上に導電膜を形成し、
前記導電膜を加工して、前記第1の導電層と前記第2の絶縁層を介して重なり、かつ集積回路部とアンテナとを電気的に接続する信号配線層と、前記信号配線層に隣接し、かつ前記開口において前記第1の導電層と接する第2の導電層とを形成することを特徴とするRFIDタグの作製方法。 Forming a first conductive layer on a first insulating layer over a flexible substrate;
Forming a second insulating layer including an opening reaching the first conductive layer on the first conductive layer;
Forming a conductive film on the second insulating layer;
Processing the conductive film, overlapping the first conductive layer and the second insulating layer and electrically connecting the integrated circuit portion and the antenna, and adjacent to the signal wiring layer and, and a method for manufacturing a RFID tag, which comprises forming a second conductive layer in contact with the first conductive layer in the opening.
前記第1の導電層上に前記第1の導電層に達する第1の開口及び第2の開口を含む第2の絶縁層を形成し、
前記第2の絶縁層上に導電膜を形成し、
前記導電膜を加工して、前記第1の導電層と前記第2の絶縁層を介して重なり、かつ集積回路部とアンテナとを電気的に接続する信号配線層と、前記信号配線層に隣接し、かつ前記開口において前記第1の導電層と接する第2の導電層とを形成することを特徴とするRFIDタグの作製方法。 Forming a first conductive layer on a first insulating layer over a flexible substrate;
Forming a second insulating layer including a first opening and a second opening reaching the first conductive layer on the first conductive layer;
Forming a conductive film on the second insulating layer;
Processing the conductive film, overlapping the first conductive layer and the second insulating layer and electrically connecting the integrated circuit portion and the antenna, and adjacent to the signal wiring layer and, and a method for manufacturing a RFID tag, which comprises forming a second conductive layer in contact with the first conductive layer in the opening.
前記導電膜を加工して、集積回路部とアンテナとを電気的に接続する信号配線層と、前記信号配線層に隣接する第1の導電層とを形成し、
前記信号配線層及び前記第1の導電層上に、前記第1の導電層に達する開口を含む第2の絶縁層を形成し、
前記第2の絶縁層上に前記開口において前記第1の導電層と接する第2の導電層を形成することを特徴とするRFIDタグの作製方法。 A conductive film is formed over the first insulating layer over the flexible substrate;
Processing the conductive film to form a signal wiring layer that electrically connects the integrated circuit portion and the antenna, and a first conductive layer adjacent to the signal wiring layer,
Forming a second insulating layer including an opening reaching the first conductive layer on the signal wiring layer and the first conductive layer;
A method for manufacturing an RFID tag , comprising: forming a second conductive layer in contact with the first conductive layer in the opening over the second insulating layer.
前記導電膜を加工して、集積回路部とアンテナとを電気的に接続する信号配線層と、前記信号配線層を間に挟んで隣接する第1の導電層及び第2の導電層とを形成し、
前記信号配線層、前記第1の導電層及び前記第2の導電層上に、前記第1の導電層に達する第1の開口及び前記第2の導電層に達する第2の開口を含む第2の絶縁層を形成し、
前記第2の絶縁層上に前記第1の開口において前記第1の導電層と、前記第2の開口において前記第2の導電層とそれぞれ接する第3の導電層を形成することを特徴とするRFIDタグの作製方法。 A conductive film is formed over the first insulating layer over the flexible substrate;
The conductive film is processed to form a signal wiring layer that electrically connects the integrated circuit portion and the antenna, and a first conductive layer and a second conductive layer that are adjacent to each other with the signal wiring layer interposed therebetween. And
A second opening including a first opening reaching the first conductive layer and a second opening reaching the second conductive layer on the signal wiring layer, the first conductive layer, and the second conductive layer; Forming an insulating layer of
Forming the first conductive layer in the first opening and the third conductive layer in contact with the second conductive layer in the second opening on the second insulating layer; A method for manufacturing an RFID tag .
前記第1の導電層上に第1の開口及び第2の開口を含む第2の絶縁層を形成し、
前記第2の絶縁層上に導電膜を形成し、
前記導電膜を加工して、集積回路部とアンテナとを電気的に接続する信号配線層と、前記信号配線層を間に挟んで隣接し、かつ前記第1の開口において前記第1の導電層と接する第2の導電層及び前記第2の開口において前記第1の導電層と接する前記第3の導電層とを形成し、
前記信号配線層、前記第2の導電層及び第3の導電層上に前記第2の導電層に達する第3の開口及び前記第3の導電層に達する第4の開口を含む第3の絶縁層を形成し、
前記第3の絶縁層上に前記第3の開口において前記第2の導電層と、前記第4の開口において前記第3の導電層とそれぞれ接する第4の導電層とを形成することを特徴とするRFIDタグの作製方法。 Forming a first conductive layer on a first insulating layer over a flexible substrate;
Forming a second insulating layer including a first opening and a second opening on the first conductive layer;
Forming a conductive film on the second insulating layer;
A signal wiring layer for electrically connecting the integrated circuit portion and the antenna by processing the conductive film, adjacent to the signal wiring layer with the signal wiring layer interposed therebetween, and the first conductive layer in the first opening A second conductive layer in contact with the first conductive layer and the third conductive layer in contact with the first conductive layer in the second opening,
Third insulation including a third opening reaching the second conductive layer and a fourth opening reaching the third conductive layer on the signal wiring layer, the second conductive layer, and the third conductive layer Forming a layer,
The second conductive layer in the third opening and the fourth conductive layer in contact with the third conductive layer in the fourth opening are formed on the third insulating layer, respectively. A method for manufacturing an RFID tag .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006145085A JP2007005782A (en) | 2005-05-27 | 2006-05-25 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005156443 | 2005-05-27 | ||
JP2006145085A JP2007005782A (en) | 2005-05-27 | 2006-05-25 | Semiconductor device and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007005782A JP2007005782A (en) | 2007-01-11 |
JP2007005782A5 true JP2007005782A5 (en) | 2009-06-18 |
Family
ID=37691035
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2006145085A Withdrawn JP2007005782A (en) | 2005-05-27 | 2006-05-25 | Semiconductor device and manufacturing method thereof |
Country Status (1)
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JP (1) | JP2007005782A (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5306705B2 (en) * | 2008-05-23 | 2013-10-02 | 株式会社半導体エネルギー研究所 | Semiconductor device |
US7821068B2 (en) * | 2008-08-18 | 2010-10-26 | Xerox Corporation | Device and process involving pinhole undercut area |
KR101611643B1 (en) | 2008-10-01 | 2016-04-11 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
JP5729186B2 (en) | 2011-07-14 | 2015-06-03 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
JP2014120710A (en) * | 2012-12-19 | 2014-06-30 | Nippon Telegr & Teleph Corp <Ntt> | Multilayer high frequency transmission line and manufacturing method therefor |
US9654094B2 (en) | 2014-03-12 | 2017-05-16 | Kabushiki Kaisha Toshiba | Semiconductor switch circuit and semiconductor substrate |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04313300A (en) * | 1991-04-10 | 1992-11-05 | Sumitomo Electric Ind Ltd | Flexible printed wiring board |
JPH0547767A (en) * | 1991-08-19 | 1993-02-26 | Yamaha Corp | Wiring structure of integrated circuit device |
JP2904135B2 (en) * | 1996-06-25 | 1999-06-14 | 富士ゼロックス株式会社 | Printed wiring board |
JP4158008B2 (en) * | 1999-11-16 | 2008-10-01 | セイコーエプソン株式会社 | Manufacturing method of semiconductor chip |
JP2002109487A (en) * | 2000-09-28 | 2002-04-12 | Denso Corp | Ic card |
JP4063533B2 (en) * | 2001-12-10 | 2008-03-19 | 日本碍子株式会社 | Flexible wiring board |
JP4566578B2 (en) * | 2003-02-24 | 2010-10-20 | 株式会社半導体エネルギー研究所 | Method for manufacturing thin film integrated circuit |
-
2006
- 2006-05-25 JP JP2006145085A patent/JP2007005782A/en not_active Withdrawn
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