JP2006344779A - 半導体装置および半導体装置の制御方法 - Google Patents
半導体装置および半導体装置の制御方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 143
- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 238000010992 reflux Methods 0.000 claims description 27
- 230000005669 field effect Effects 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 16
- 210000000746 body region Anatomy 0.000 claims description 13
- 230000015556 catabolic process Effects 0.000 description 18
- 238000009792 diffusion process Methods 0.000 description 11
- 238000005468 ion implantation Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
【解決手段】半導体装置100は,IGBT領域とパワーMOS領域とが1チップ内に形成されている。そして,電力供給期間には両領域で電流を流し,還流期間にはパワーMOS領域の内蔵ダイオードを利用して電流を流している。パワーMOS領域のNドリフト領域17は,複数段のPフローティング領域51を有している。さらには,パワーMOS領域のNドリフト領域17は,IGBT領域のN- ドリフト領域12よりも不純物濃度が高い。また,半導体装置100では,還流期間中,IGBT領域をオフとし,パワーMOS領域をオンとする。
【選択図】 図13
Description
第1の形態に係る半導体装置100は,IGBTとパワーMOSFETとが同一基板上に形成されたトレンチゲート型半導体装置であり,図1の平面図に示す構造を有している。半導体装置100は,IGBTが形成された領域(以下,「IGBT領域とする」)と,パワーMOSFETが形成された領域(以下,「パワーMOS領域」とする)によって囲まれた構造となっている。すなわち,半導体装置100では,IGBTとパワーMOSとが1チップ内に形成されている。
第2の形態に係る半導体装置200は,第1の形態と同様に,IGBTとパワーMOSFETとが同一基板上に形成されたトレンチゲート型半導体装置であり,IGBT領域がパワーMOS領域に囲まれた構造となっている。すなわち,半導体装置200では,IGBTとパワーMOSとが一体となっており,両領域から電流を流すことができるとともにパワーMOS領域から還流電流を流すことができる。また,半導体装置200では,第1の形態と同様に,IGBT領域とパワーMOS領域とを別々にオンさせることが可能となるように配置されている。本形態の半導体装置200は,パワーMOS領域内のドリフト領域中にフローティング領域を配置することで高耐圧化および低オン抵抗化を図っている。この点,スーパージャンクション構造によって高耐圧化および低オン抵抗化を図る第1の形態と異なる。
12 N- ドリフト領域
16 N+ ドレイン領域
17 Nドリフト領域
18 P拡散領域
21 ゲートトレンチ
22 ゲート電極
26 ゲートトレンチ
27 ゲート電極
28 ゲートトレンチ
29 堆積絶縁層
31 N+ エミッタ領域
36 N+ ソース領域
41 P- ベース領域
46 P- ベース領域
51 Pフローティング領域
100 半導体装置
Claims (10)
- 電力制御に供する半導体装置において,
絶縁ゲート型バイポーラトランジスタ領域と,
前記絶縁ゲート型バイポーラトランジスタと並列に接続された絶縁ゲート型電界効果型トランジスタ領域とを有し,
前記絶縁ゲート型バイポーラトランジスタ領域と前記絶縁ゲート型電界効果型トランジスタ領域とが同一半導体チップ内に形成され,
前記絶縁ゲート型バイポーラトランジスタ領域のゲート電極と,前記絶縁ゲート型電界効果型トランジスタ領域のゲート電極とは,電気的に非接続であることを特徴とする半導体装置。 - 請求項1に記載する半導体装置において,
電力供給を行う期間では,前記絶縁ゲート型バイポーラトランジスタ領域および前記絶縁ゲート型電界効果型トランジスタ領域がともにオンされ,
還流動作を行う期間では,前記絶縁ゲート型バイポーラトランジスタ領域がオフされ,前記絶縁ゲート型電界効果型トランジスタ領域がオンされることを特徴とする半導体装置。 - 請求項2に記載する半導体装置において,
前記絶縁ゲート型電界効果型トランジスタ領域は,還流動作を行う期間となってから所定の期間待機した後にオンされることを特徴とする半導体装置。 - 請求項1から請求項3のいずれか1つに記載する半導体装置において,
前記絶縁ゲート型電界効果型トランジスタ領域は,
第1導電型半導体である第1半導体領域と第2導電型半導体である第2半導体領域とが基板の幅方向に交互に配置されたコラム領域と,
半導体基板の主表面側に位置し,ゲート電極領域とゲート絶縁膜を挟んで対向し,第2導電型半導体であるボディ領域とを有し,
前記ボディ領域と前記コラム領域の第2半導体領域とは一体であることを特徴とする半導体装置。 - 請求項1から請求項3のいずれか1つに記載する半導体装置において,
前記絶縁ゲート型電界効果型トランジスタ領域は,
第1導電型半導体であるドリフト領域と,
前記ドリフト領域に囲まれ,第2導電型半導体であるフローティング領域とを有することを特徴とする半導体装置。 - 請求項5に記載する半導体装置において,
半導体基板の上面に開口部が設けられ,その底部が前記フローティング領域内に位置するトレンチ部を有することを特徴とする半導体装置。 - 請求項4から請求項6のいずれか1つに記載する半導体装置において,
前記絶縁ゲート型電界効果型トランジスタ領域のドリフト領域の不純物濃度は,前記絶縁ゲート型バイポーラトランジスタ領域のドリフト領域の不純物濃度よりも高いことを特徴とする半導体装置。 - 請求項1から請求項7のいずれか1つに記載する半導体装置において,
前記絶縁ゲート型バイポーラトランジスタ領域は,半導体装置の上面から見て前記絶縁ゲート型電界効果型トランジスタ領域に囲まれていることを特徴とする半導体装置。 - 絶縁ゲート型バイポーラトランジスタと,絶縁ゲート型電界効果型トランジスタとが並列に接続された半導体装置の制御方法において,
電力供給を行う期間では,前記絶縁ゲート型バイポーラトランジスタおよび前記絶縁ゲート型電界効果型トランジスタをともにオンし,
還流動作を行う期間では,前記絶縁ゲート型バイポーラトランジスタをオフし,前記絶縁ゲート型電界効果型トランジスタをオンすることを特徴とする半導体装置の制御方法。 - 請求項9に記載する半導体装置の制御方法において,
前記絶縁ゲート型電界効果型トランジスタは,還流動作を行う期間となってから所定の期間待機した後にオンすることを特徴とする半導体装置の制御方法。
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Cited By (40)
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JP2007266550A (ja) * | 2006-03-30 | 2007-10-11 | Shindengen Electric Mfg Co Ltd | 半導体装置 |
JP2008277324A (ja) * | 2007-04-25 | 2008-11-13 | Denso Corp | 縦型mosfetを有する半導体装置 |
WO2009034851A1 (ja) * | 2007-09-10 | 2009-03-19 | Toyota Jidosha Kabushiki Kaisha | 給電装置とその駆動方法 |
WO2009101868A1 (ja) * | 2008-02-14 | 2009-08-20 | Toyota Jidosha Kabushiki Kaisha | 逆導通半導体素子の駆動方法と半導体装置及び給電装置 |
JP2010135573A (ja) * | 2008-12-05 | 2010-06-17 | Mitsubishi Electric Corp | 炭化珪素半導体装置及びその製造方法 |
WO2011001588A1 (ja) * | 2009-06-29 | 2011-01-06 | 株式会社デンソー | 半導体装置 |
JP2011096852A (ja) * | 2009-10-29 | 2011-05-12 | Toyota Motor Corp | 給電装置 |
US8018008B2 (en) | 2008-05-08 | 2011-09-13 | Denso Corporation | Semiconductor device including a plurality of chips and method of manufacturing semiconductor device |
JP2012079945A (ja) * | 2010-10-01 | 2012-04-19 | Toyota Motor Corp | 半導体装置 |
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JP2012234926A (ja) * | 2011-04-28 | 2012-11-29 | Sanken Electric Co Ltd | 半導体装置 |
US8410489B2 (en) | 2009-04-30 | 2013-04-02 | Panasonic Corporation | Semiconductor element, semiconductor device, and power converter |
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