FR2808921B1 - Dispositif a semiconducteur ayant une structure a triple caisson et procede de fabrication - Google Patents

Dispositif a semiconducteur ayant une structure a triple caisson et procede de fabrication

Info

Publication number
FR2808921B1
FR2808921B1 FR0104561A FR0104561A FR2808921B1 FR 2808921 B1 FR2808921 B1 FR 2808921B1 FR 0104561 A FR0104561 A FR 0104561A FR 0104561 A FR0104561 A FR 0104561A FR 2808921 B1 FR2808921 B1 FR 2808921B1
Authority
FR
France
Prior art keywords
manufacturing
semiconductor device
box structure
triple box
triple
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0104561A
Other languages
English (en)
Other versions
FR2808921A1 (fr
Inventor
Tomohiro Yamashita
Yoshinori Okumura
Atsushi Hachisuka
Shinya Soeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of FR2808921A1 publication Critical patent/FR2808921A1/fr
Application granted granted Critical
Publication of FR2808921B1 publication Critical patent/FR2808921B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
FR0104561A 2000-04-05 2001-04-04 Dispositif a semiconducteur ayant une structure a triple caisson et procede de fabrication Expired - Fee Related FR2808921B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000103083A JP2001291779A (ja) 2000-04-05 2000-04-05 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
FR2808921A1 FR2808921A1 (fr) 2001-11-16
FR2808921B1 true FR2808921B1 (fr) 2004-09-10

Family

ID=18616850

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0104561A Expired - Fee Related FR2808921B1 (fr) 2000-04-05 2001-04-04 Dispositif a semiconducteur ayant une structure a triple caisson et procede de fabrication

Country Status (5)

Country Link
US (1) US6388295B1 (fr)
JP (1) JP2001291779A (fr)
KR (1) KR100362904B1 (fr)
DE (1) DE10116800A1 (fr)
FR (1) FR2808921B1 (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003158204A (ja) * 2001-11-22 2003-05-30 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法
JP2004311684A (ja) * 2003-04-07 2004-11-04 Sanyo Electric Co Ltd 半導体装置
JP2005142321A (ja) 2003-11-06 2005-06-02 Nec Electronics Corp 半導体集積回路装置およびその製造方法
JP4890838B2 (ja) * 2005-11-17 2012-03-07 ルネサスエレクトロニクス株式会社 半導体集積回路のレイアウト設計方法、及びレイアウト設計ツール
US7781289B1 (en) * 2007-05-03 2010-08-24 National Semiconductor Corporation Method for fabricating higher quality thicker gate oxide in a non-volatile memory cell and associated circuits
US20090042377A1 (en) * 2007-08-08 2009-02-12 Seetharaman Sridhar Method for forming self-aligned wells to support tight spacing
KR100959438B1 (ko) * 2007-11-30 2010-05-25 주식회사 동부하이텍 정전기방전 보호소자 및 그 제조방법
JP2009182076A (ja) * 2008-01-30 2009-08-13 Panasonic Corp 半導体装置及びその製造方法
US8377772B2 (en) * 2010-08-17 2013-02-19 Texas Instruments Incorporated CMOS integration method for optimal IO transistor VT
JP2014011336A (ja) * 2012-06-29 2014-01-20 Fujitsu Semiconductor Ltd 半導体装置及びその製造方法
JP2014207361A (ja) * 2013-04-15 2014-10-30 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US9831134B1 (en) * 2016-09-28 2017-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device having deep wells
US10923344B2 (en) * 2017-10-30 2021-02-16 Asm Ip Holding B.V. Methods for forming a semiconductor structure and related semiconductor structures
CN116153934B (zh) * 2023-04-20 2023-06-27 长鑫存储技术有限公司 半导体结构及其制备方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0671067B2 (ja) * 1985-11-20 1994-09-07 株式会社日立製作所 半導体装置
JPH04211155A (ja) * 1990-01-29 1992-08-03 Matsushita Electron Corp 半導体装置
JP2523409B2 (ja) 1990-05-02 1996-08-07 三菱電機株式会社 半導体記憶装置およびその製造方法
JP3252432B2 (ja) 1992-03-19 2002-02-04 松下電器産業株式会社 半導体装置およびその製造方法
KR940003026A (ko) * 1992-07-13 1994-02-19 김광호 트리플웰을 이용한 반도체장치
US5595925A (en) * 1994-04-29 1997-01-21 Texas Instruments Incorporated Method for fabricating a multiple well structure for providing multiple substrate bias for DRAM device formed therein
JPH09321135A (ja) * 1996-05-24 1997-12-12 Nippon Steel Corp 半導体装置
JPH1070243A (ja) * 1996-05-30 1998-03-10 Toshiba Corp 半導体集積回路装置およびその検査方法およびその検査装置
JP3777000B2 (ja) * 1996-12-20 2006-05-24 富士通株式会社 半導体装置とその製造方法
JP3335876B2 (ja) 1997-07-08 2002-10-21 シャープ株式会社 半導体装置の製造方法及び半導体装置
JPH1197646A (ja) * 1997-09-22 1999-04-09 Fujitsu Ltd 半導体装置及びその製造方法
JP3419672B2 (ja) * 1997-12-19 2003-06-23 富士通株式会社 半導体装置及びその製造方法
KR100275725B1 (ko) * 1997-12-27 2000-12-15 윤종용 트리플웰 구조를 갖는 반도체 메모리 장치 및 그 제조방법
JP2978467B2 (ja) * 1998-03-16 1999-11-15 株式会社日立製作所 半導体集積回路装置の製造方法
JPH11261022A (ja) * 1998-03-16 1999-09-24 Hitachi Ltd 半導体集積回路装置
JP3097652B2 (ja) * 1998-03-31 2000-10-10 日本電気株式会社 半導体集積回路装置の製造方法

Also Published As

Publication number Publication date
US6388295B1 (en) 2002-05-14
KR20010096527A (ko) 2001-11-07
FR2808921A1 (fr) 2001-11-16
JP2001291779A (ja) 2001-10-19
KR100362904B1 (ko) 2002-11-29
DE10116800A1 (de) 2001-10-18

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Legal Events

Date Code Title Description
TP Transmission of property
PLFP Fee payment

Year of fee payment: 15

CA Change of address

Effective date: 20160217

TP Transmission of property

Owner name: RENESAS ELECTRONICS CORPORATION, JP

Effective date: 20160217

ST Notification of lapse

Effective date: 20161230