FR2451103A1 - PROCESS FOR PASSIVATING AN INTEGRATED CIRCUIT, USING A SILICON NITRIDE LAYER (SI3N4) AND A PHOSPHOSILICATE GLASS LAYER (PSG) - Google Patents

PROCESS FOR PASSIVATING AN INTEGRATED CIRCUIT, USING A SILICON NITRIDE LAYER (SI3N4) AND A PHOSPHOSILICATE GLASS LAYER (PSG)

Info

Publication number
FR2451103A1
FR2451103A1 FR8004843A FR8004843A FR2451103A1 FR 2451103 A1 FR2451103 A1 FR 2451103A1 FR 8004843 A FR8004843 A FR 8004843A FR 8004843 A FR8004843 A FR 8004843A FR 2451103 A1 FR2451103 A1 FR 2451103A1
Authority
FR
France
Prior art keywords
layer
passivating
integrated circuit
active regions
si3n4
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR8004843A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Publication of FR2451103A1 publication Critical patent/FR2451103A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'INVENTION CONCERNE UN PROCEDE DE PASSIVATION D'UN CIRCUIT INTEGRE COMPRENANT UN SUBSTRAT SEMI-CONDUCTEUR AVEC DES DISPOSITIFS SEMI-CONDUCTEURS AYANT DES REGIONS ACTIVES ET DES REGIONS DE CHAMP, ET DANS LEQUEL ON COUVRE LE SUBSTRAT D'UNE COUCHE ISOLANTE OU L'ON FORME DES OUVERTURES DE CONTACT, ON APPLIQUE UNE COUCHE DE VERRE AU PHOSPHOSILICATE SUR LA COUCHE ISOLANTE, ON RETIRE DES PARTIES DE CETTE COUCHE QUI S'ETENDENT SUR LES REGIONS ACTIVES DU DISPOSITIF, ON CHAUFFE LA COUCHE DE VERRE ET ON APPLIQUE UNE COUCHE EN METAL SUR LA SURFACE DE LA COUCHE DE VERRE, QUI TRAVERSE LES OUVERTURES JUSQU'AUX PARTIES SOUS-JACENTES DANS LES REGIONS ACTIVES DU DISPOSITIF. SELON L'INVENTION, AVANT D'APPLIQUER LA COUCHE DE VERRE AU PHOSPHOSILICATE 32, ON APPLIQUE UNE COUCHE IMPERMEABLE 30 SUR LA COUCHE ISOLANTE, ON CHAUFFE EN PRESENCE DE VAPEUR ET APRES CHAUFFAGE ON RETIRE LES PARTIES DE LA COUCHE 30 SE TROUVANT AU-DESSUS DES REGIONS ACTIVES DU DISPOSITIF. L'INVENTION S'APPLIQUE NOTAMMENT A L'INDUSTRIE DES SEMI-CONDUCTEURS.THE INVENTION RELATES TO A PROCESS FOR PASSIVATING AN INTEGRATED CIRCUIT INCLUDING A SEMICONDUCTOR SUBSTRATE WITH SEMICONDUCTOR DEVICES HAVING ACTIVE REGIONS AND FIELD REGIONS, AND IN WHICH THE SUBSTRATE IS COVERED WITH AN INSULATING LAYER OR THE SUBSTRATE. CONTACT OPENINGS ARE FORMED, A LAYER OF PHOSPHOSILICATE GLASS IS APPLIED TO THE INSULATING LAYER, PARTS OF THIS LAYER WHICH EXTEND OVER THE ACTIVE REGIONS OF THE DEVICE, HEATED AND A LAYER IS APPLIED. METAL ON THE SURFACE OF THE LAYER OF GLASS, WHICH PASSES THE OPENINGS TO THE UNDERLYING PARTS IN THE ACTIVE REGIONS OF THE DEVICE. ACCORDING TO THE INVENTION, BEFORE APPLYING THE GLASS COATER TO THE PHOSPHOSILICATE 32, A WATERPROOF LAYER 30 IS APPLIED TO THE INSULATION LAYER, IT IS HEATED IN THE PRESENCE OF VAPOR AND AFTER HEATING THE PARTS OF LAYER 30 ARE BEING REMOVED ABOVE. ACTIVE REGIONS OF THE SYSTEM. THE INVENTION APPLIES IN PARTICULAR TO THE SEMICONDUCTOR INDUSTRY.

FR8004843A 1979-03-05 1980-03-04 PROCESS FOR PASSIVATING AN INTEGRATED CIRCUIT, USING A SILICON NITRIDE LAYER (SI3N4) AND A PHOSPHOSILICATE GLASS LAYER (PSG) Withdrawn FR2451103A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US1710079A 1979-03-05 1979-03-05

Publications (1)

Publication Number Publication Date
FR2451103A1 true FR2451103A1 (en) 1980-10-03

Family

ID=21780714

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8004843A Withdrawn FR2451103A1 (en) 1979-03-05 1980-03-04 PROCESS FOR PASSIVATING AN INTEGRATED CIRCUIT, USING A SILICON NITRIDE LAYER (SI3N4) AND A PHOSPHOSILICATE GLASS LAYER (PSG)

Country Status (7)

Country Link
JP (1) JPS55121669A (en)
DE (1) DE3007500A1 (en)
FR (1) FR2451103A1 (en)
GB (1) GB2044533B (en)
IT (1) IT1140645B (en)
NL (1) NL8001310A (en)
YU (1) YU61180A (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4542037A (en) * 1980-04-28 1985-09-17 Fairchild Camera And Instrument Corporation Laser induced flow of glass bonded materials
CA1174285A (en) * 1980-04-28 1984-09-11 Michelangelo Delfino Laser induced flow of integrated circuit structure materials
JPS581878A (en) * 1981-06-26 1983-01-07 Fujitsu Ltd Production of bubble memory device
DE3130666A1 (en) * 1981-08-03 1983-02-17 Siemens AG, 1000 Berlin und 8000 München Method for fabricating integrated MOS field effect transistors having a phosphosilicate glass layer as an intermediary oxide layer
DE3131050A1 (en) * 1981-08-05 1983-02-24 Siemens AG, 1000 Berlin und 8000 München Process for fabricating integrated MOS field effect transistors, employing a surface layer consisting of phosphosilicate glass on the intermediary oxide between polysilicon plane and metal conductor track plane
DE3133516A1 (en) * 1981-08-25 1983-03-17 Siemens AG, 1000 Berlin und 8000 München Process for rounding the intermediary oxide between the polysilicon plane and metal conductor track plane when fabricating integrated n-type channel MOS field-effect transistors
JPS5898934A (en) * 1981-12-08 1983-06-13 Matsushita Electronics Corp Manufacture of semiconductor device
US4686000A (en) * 1985-04-02 1987-08-11 Heath Barbara A Self-aligned contact process
JPH088246A (en) * 1994-06-21 1996-01-12 Nippon Motorola Ltd Method for forming metal wiring of semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3627598A (en) * 1970-02-05 1971-12-14 Fairchild Camera Instr Co Nitride passivation of mesa transistors by phosphovapox lifting
US3917495A (en) * 1970-06-01 1975-11-04 Gen Electric Method of making improved planar devices including oxide-nitride composite layer
US3943621A (en) * 1974-03-25 1976-03-16 General Electric Company Semiconductor device and method of manufacture therefor
US4005240A (en) * 1975-03-10 1977-01-25 Aeronutronic Ford Corporation Germanium device passivation
GB2023342A (en) * 1978-06-19 1979-12-28 Rca Corp Passivating composite for a semiconductor device comprising a silicon nitride (si3 n4) layer and phosphosilicate glass (psg) layer 3 and 4 the method off manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3627598A (en) * 1970-02-05 1971-12-14 Fairchild Camera Instr Co Nitride passivation of mesa transistors by phosphovapox lifting
US3917495A (en) * 1970-06-01 1975-11-04 Gen Electric Method of making improved planar devices including oxide-nitride composite layer
US3943621A (en) * 1974-03-25 1976-03-16 General Electric Company Semiconductor device and method of manufacture therefor
US4005240A (en) * 1975-03-10 1977-01-25 Aeronutronic Ford Corporation Germanium device passivation
GB2023342A (en) * 1978-06-19 1979-12-28 Rca Corp Passivating composite for a semiconductor device comprising a silicon nitride (si3 n4) layer and phosphosilicate glass (psg) layer 3 and 4 the method off manufacturing the same

Also Published As

Publication number Publication date
NL8001310A (en) 1980-09-09
GB2044533B (en) 1983-12-14
JPS55121669A (en) 1980-09-18
DE3007500A1 (en) 1980-09-18
YU61180A (en) 1983-02-28
IT8020023A1 (en) 1981-08-19
IT8020023A0 (en) 1980-02-19
IT1140645B (en) 1986-10-01
GB2044533A (en) 1980-10-15

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