FR2391562A1 - Sealed passivation for semiconductor devices - uses silica glass covered by polycrystalline silicon - Google Patents

Sealed passivation for semiconductor devices - uses silica glass covered by polycrystalline silicon

Info

Publication number
FR2391562A1
FR2391562A1 FR7814660A FR7814660A FR2391562A1 FR 2391562 A1 FR2391562 A1 FR 2391562A1 FR 7814660 A FR7814660 A FR 7814660A FR 7814660 A FR7814660 A FR 7814660A FR 2391562 A1 FR2391562 A1 FR 2391562A1
Authority
FR
France
Prior art keywords
layer
pref
semiconductor devices
polycrystalline silicon
silica glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7814660A
Other languages
French (fr)
Inventor
Louis N Pomante
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Solid State Scientific Inc
Original Assignee
Solid State Scientific Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Solid State Scientific Inc filed Critical Solid State Scientific Inc
Publication of FR2391562A1 publication Critical patent/FR2391562A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Formation Of Insulating Films (AREA)
  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The device includes a semiconductor substrate coated with a sealed, passive Si layer protecting the device against contamination. The substate is pref. provided with a metal layer and then an insulating layer under the Si layer. The Si layer is pref. polycrystalline Si, whereas the insulating layer is pref. passivation or glass, covered entirely by the Si layer; a second insulating layer may be used on top of the Si layer. The Si layer is pref. 500-3000, esp. 500-1000 angstroms thick, and is applied in a chamber at 450-525 degrees C. Used in the protection of integrated circuits against attack by moisture or by metal ions present in the surrounding atmos.
FR7814660A 1977-05-17 1978-05-09 Sealed passivation for semiconductor devices - uses silica glass covered by polycrystalline silicon Withdrawn FR2391562A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US79787877A 1977-05-17 1977-05-17

Publications (1)

Publication Number Publication Date
FR2391562A1 true FR2391562A1 (en) 1978-12-15

Family

ID=25172012

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7814660A Withdrawn FR2391562A1 (en) 1977-05-17 1978-05-09 Sealed passivation for semiconductor devices - uses silica glass covered by polycrystalline silicon

Country Status (4)

Country Link
JP (1) JPS53142178A (en)
CA (1) CA1070853A (en)
DE (1) DE2820469A1 (en)
FR (1) FR2391562A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3229203A1 (en) * 1982-08-05 1984-02-09 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Semiconductor component and process for its production

Also Published As

Publication number Publication date
CA1070853A (en) 1980-01-29
JPS53142178A (en) 1978-12-11
DE2820469A1 (en) 1979-04-12

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Legal Events

Date Code Title Description
ST Notification of lapse