JPS649642A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS649642A JPS649642A JP16579587A JP16579587A JPS649642A JP S649642 A JPS649642 A JP S649642A JP 16579587 A JP16579587 A JP 16579587A JP 16579587 A JP16579587 A JP 16579587A JP S649642 A JPS649642 A JP S649642A
- Authority
- JP
- Japan
- Prior art keywords
- barrier layer
- electrode wiring
- silicon
- high temperature
- aspect ratio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To form a metal wiring having a high aspect ratio using an excellent step coverage in such a manner that it has excellent ohmic contact by a method wherein a barrier layer of titanium nitride or zirconium nitride is formed, and an aluminum electrode wiring containing no silicon is flatly formed thereon at a high temperature. CONSTITUTION:A contact layer 4 of titanium silicide or zirconium silicide is formed on the surface directly contacting to a silicon substrate 1, and a barrier layer 5 of titanium nitride is formed thereon. Then, an aluminum electrode wiring 6 containing no silicon is flatly formed on the barrier layer 5 at a high temperature. As a result, ohmic contact is secured by the contact layer 4, it is unnecessary for the electrode wiring 6 to contain silicon by the presence of the barrier layer 5. Also, a flat electrode wiring 6 is formed at a sufficiently high temperature, and a metal wiring, having a high aspect ratio and an excellent step coverage, can be obtained by the synergistic action of the above-mentioned wirings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16579587A JPS649642A (en) | 1987-07-02 | 1987-07-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16579587A JPS649642A (en) | 1987-07-02 | 1987-07-02 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS649642A true JPS649642A (en) | 1989-01-12 |
Family
ID=15819136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16579587A Pending JPS649642A (en) | 1987-07-02 | 1987-07-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS649642A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100477833B1 (en) * | 1997-12-27 | 2005-06-21 | 주식회사 하이닉스반도체 | Barrier Metal Film Formation Method of Semiconductor Device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5638869A (en) * | 1979-09-07 | 1981-04-14 | Seiko Epson Corp | Manufacture of mos-type semiconductor device |
| JPS6154650A (en) * | 1984-08-24 | 1986-03-18 | Mitsubishi Electric Corp | Manufacturing method of semiconductor device |
| JPS62290128A (en) * | 1986-06-10 | 1987-12-17 | Toshiba Corp | Manufacture of semiconductor device |
-
1987
- 1987-07-02 JP JP16579587A patent/JPS649642A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5638869A (en) * | 1979-09-07 | 1981-04-14 | Seiko Epson Corp | Manufacture of mos-type semiconductor device |
| JPS6154650A (en) * | 1984-08-24 | 1986-03-18 | Mitsubishi Electric Corp | Manufacturing method of semiconductor device |
| JPS62290128A (en) * | 1986-06-10 | 1987-12-17 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100477833B1 (en) * | 1997-12-27 | 2005-06-21 | 주식회사 하이닉스반도체 | Barrier Metal Film Formation Method of Semiconductor Device |
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