FR2423030A1 - Cellule de memoire a semiconducteurs comportant des conducteurs de commande possedant une conductivite elevee - Google Patents

Cellule de memoire a semiconducteurs comportant des conducteurs de commande possedant une conductivite elevee

Info

Publication number
FR2423030A1
FR2423030A1 FR7908484A FR7908484A FR2423030A1 FR 2423030 A1 FR2423030 A1 FR 2423030A1 FR 7908484 A FR7908484 A FR 7908484A FR 7908484 A FR7908484 A FR 7908484A FR 2423030 A1 FR2423030 A1 FR 2423030A1
Authority
FR
France
Prior art keywords
control conductors
semiconductor memory
high conductivity
memory cell
cell containing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
FR7908484A
Other languages
English (en)
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of FR2423030A1 publication Critical patent/FR2423030A1/fr
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53271Conductive materials containing semiconductor material, e.g. polysilicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
FR7908484A 1978-04-11 1979-04-04 Cellule de memoire a semiconducteurs comportant des conducteurs de commande possedant une conductivite elevee Pending FR2423030A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2815605A DE2815605C3 (de) 1978-04-11 1978-04-11 Halbleiterspeicher mit Ansteuerleitungen hoher Leitfähigkeit

Publications (1)

Publication Number Publication Date
FR2423030A1 true FR2423030A1 (fr) 1979-11-09

Family

ID=6036700

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7908484A Pending FR2423030A1 (fr) 1978-04-11 1979-04-04 Cellule de memoire a semiconducteurs comportant des conducteurs de commande possedant une conductivite elevee

Country Status (3)

Country Link
DE (1) DE2815605C3 (de)
FR (1) FR2423030A1 (de)
GB (1) GB2019091B (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4329706A (en) * 1979-03-01 1982-05-11 International Business Machines Corporation Doped polysilicon silicide semiconductor integrated circuit interconnections
DE2926874A1 (de) * 1979-07-03 1981-01-22 Siemens Ag Verfahren zum herstellen von niederohmigen, diffundierten bereichen bei der silizium-gate-technologie
US4285761A (en) * 1980-06-30 1981-08-25 International Business Machines Corporation Process for selectively forming refractory metal silicide layers on semiconductor devices
JPS5832789B2 (ja) * 1980-07-18 1983-07-15 富士通株式会社 半導体メモリ
JPS5780739A (en) * 1980-11-07 1982-05-20 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
DE3046218C2 (de) * 1980-12-08 1982-09-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Erzeugung einer Eintransistor-Speicherzelle in Doppelsilizium-Technik
US4403394A (en) * 1980-12-17 1983-09-13 International Business Machines Corporation Formation of bit lines for ram device
JPS57159055A (en) * 1981-03-25 1982-10-01 Toshiba Corp Manufacture of semiconductor device
DE3250096C2 (de) * 1981-05-27 1997-09-11 Hitachi Ltd Verfahren zur Herstellung einer einen MISFET enthaltenden Halbleiterschaltung
JPS57194567A (en) * 1981-05-27 1982-11-30 Hitachi Ltd Semiconductor memory device
JPS57207556A (en) * 1981-06-12 1982-12-20 Nippon Denso Co Ltd Electric dust collector
JPS5873156A (ja) * 1981-10-28 1983-05-02 Hitachi Ltd 半導体装置
JPS5893347A (ja) * 1981-11-30 1983-06-03 Toshiba Corp Mos型半導体装置及びその製造方法
DE3304651A1 (de) * 1983-02-10 1984-08-16 Siemens AG, 1000 Berlin und 8000 München Dynamische halbleiterspeicherzelle mit wahlfreiem zugriff (dram) und verfahren zu ihrer herstellung
GB2139418A (en) * 1983-05-05 1984-11-07 Standard Telephones Cables Ltd Semiconductor devices and conductors therefor
JPS60136337A (ja) * 1983-12-22 1985-07-19 モノリシツク・メモリ−ズ・インコ−ポレイテツド 2重層処理においてヒロツク抑制層を形成する方法及びその構造物
JPS60134466A (ja) * 1983-12-23 1985-07-17 Hitachi Ltd 半導体装置およびその製造方法
JPS60263455A (ja) * 1984-06-04 1985-12-26 インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン ポリシリコン構造
KR940002772B1 (ko) * 1984-08-31 1994-04-02 가부시기가이샤 히다찌세이사꾸쇼 반도체 집적회로 장치 및 그 제조방법
JP2869090B2 (ja) * 1989-08-11 1999-03-10 株式会社リコー 半導体メモリ装置とその製造方法
US5362662A (en) * 1989-08-11 1994-11-08 Ricoh Company, Ltd. Method for producing semiconductor memory device having a planar cell structure

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2164745C3 (de) * 1971-12-27 1981-07-30 geb. Avvakumova Evdokija Kirillovna Moskva Šergold Halbleiter-Diodenmatrix
US4003036A (en) * 1975-10-23 1977-01-11 American Micro-Systems, Inc. Single IGFET memory cell with buried storage element

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
EXBK/74 *
EXBK/75 *
EXBK/77 *
EXBK/78 *

Also Published As

Publication number Publication date
GB2019091A (en) 1979-10-24
GB2019091B (en) 1982-07-07
DE2815605C3 (de) 1981-04-16
DE2815605B2 (de) 1980-06-26
DE2815605A1 (de) 1979-10-18

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