EP1055287B1 - Decoder with serial concatenated structure in communication system - Google Patents

Decoder with serial concatenated structure in communication system Download PDF

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Publication number
EP1055287B1
EP1055287B1 EP99959975A EP99959975A EP1055287B1 EP 1055287 B1 EP1055287 B1 EP 1055287B1 EP 99959975 A EP99959975 A EP 99959975A EP 99959975 A EP99959975 A EP 99959975A EP 1055287 B1 EP1055287 B1 EP 1055287B1
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Prior art keywords
decoding
decoder
codeword
bits
redundancy
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EP99959975A
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German (de)
English (en)
French (fr)
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EP1055287A1 (en
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Min-Goo Kim
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/45—Soft decoding, i.e. using symbol reliability information
    • H03M13/458—Soft decoding, i.e. using symbol reliability information by updating bit probabilities or hard decisions in an iterative fashion for convergence to a final decoding result
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3944—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes for block codes, especially trellis or lattice decoding thereof

Definitions

  • the present invention relates generally to a decoder in a radio communication system, and in particular, to a device for decoding linear block codes through an analysis of serial concatenated codes.
  • This technical field is related to soft decision of error correction codes and optimal performance of linear block codes, and in particular, to a decoding scheme for turbo codes.
  • this field is extensively related to reliability improvement of digital communication systems, including not only existing digital communication systems but also future mobile communication systems using linear block codes.
  • erasure decoding and trellis decoding are used for soft decision of the linear block codes.
  • decoding methods are disadvantageous in that an increase in redundancy (n-k) of the linear block codes causes geometric progression of the complexity.
  • n-k redundancy
  • ML maximum likelihood
  • the existing ML (Maximum likelihood) decoding uses a method of determining an ML (maximum likelihood) codeword, it is not a preferable method for minimizing a post information bit error probability. Therefore, a decoding method for minimizing the post information bit error probability is required.
  • a decoding device for decoding an input codeword bit stream using a generator polynomial represented by product of a plurality of sub-polynomials.
  • the decoding device comprises a plurality of serial concatenated decoders each having different generator polynomials, wherein a product of the different generator polynomials becomes said generator polynomial, the different generator polynomials are represented by the different sub-polynomials or by a product of the sub-polynomials, and a first-stage decoder out of the serial concatenated decoders receives said codeword bit stream.
  • the decoders each perform soft decision, and the codeword is a linear block code.
  • the invention includes a new encoding scheme for encoding serial concatenated codes by modifying an existing encoder for encoding linear block codes.
  • the decoding scheme the trellis structure of a codeword analyzed with the serial concatenated codes has a very low complexity as compared with the trellis structure of the existing linear block codes.
  • the invention includes a method for embodying a decoding scheme corresponding to the above encoding scheme, using an ML decoder or a MAP decoder (Maximum A Posteriori probability).
  • the invention also includes an iterative decoding algorithm and scheme for decoding the structured codeword at a receiver.
  • an encoder a description will be made of an encoder for encoding BCH codes and Reed-Solomon codes, which are typically used as linear block codes. Thereafter, it will be proven that the existing generator polynomial is identical to serial concatenation of generator polynomials of a new codeword defined by a plurality of sub-codes. Based on this analysis, the specification will show that the existing linear block codes can be divided into a plurality of sub-codes, and then describe a method for serially concatenating the sub-codes and a detailed solution thereof.
  • the specification will present an iterative decoding scheme for decoding the codes, and show several embodiments. Further, the specification will propose a method for utilizing extrinsic information for iterative decoding depending on the amount of information (i.e., traffic) output from each component decoder. Also, a reference will be made to an iterative decoding method and a deinterleaver for performance improvement. In addition, a combining method using the traffic of a channel will be described.
  • a generator polynomial of a given (n,k) BCH code C For a generator polynomial of a given (n,k) BCH code C, a selected one of primitive polynomials in a Galois field GF(2 m ) is used.
  • a codeword C(x) of a BCH code is represented by a product of polynomials as shown in Equation (1) below.
  • a generator polynomial of the used code is g(x) and a polynomial of input information is I(x)
  • a codeword C(x) generated from the encoder is given by the equation:
  • C x g x ⁇ I x
  • codeword polynomial C(x) of an (n,k) BCH code C can be expressed as:
  • Equation (4) implies that the existing codeword C(x) can be analyzed as a codeword generated by serial concatenation of t sub-codewords. Therefore, it is noted that the same result can be obtained, even though encoding is performed by dividing an encoder having one codeword into t sub-code encoders.
  • the encoder includes a plurality of serial concatenated component encoders, and each encoder performs encoding using a different sub-polynomial mt(x).
  • a description of encoding and decoding will be made with reference to linear block codes, by way of example.
  • a component encoder 211 encodes an input information bit stream k1 into a codeword bit stream n1.
  • An interleaver 212 interleaves the codeword bit stream n1 output from the component encoder 211.
  • a component encoder 213 encodes an interleaved codeword bit stream k2 into a codeword bit stream n2.
  • an interleaver 214 interleaves a codeword bit stream n(p-1) output from a component encoder in the pre-stage.
  • a component encoder 215 encodes the interleaved codeword bit stream kp to output a final codeword bit stream np
  • the interleavers have two operation modes: one is a bypass mode for outputting an input bit stream in the original sequence, and another is a permutation mode using random interleaving, uniform interleaving and non-uniform interleaving.
  • the operation mode of the interleaver is to optimize system performance.
  • a codeword generated from the encoder is identical to a (n,k) BCH code generated from an original encoder. Therefore, the characteristic parameters of the output codeword are all identical to the original parameters.
  • the output codeword becomes an (n,k) linear block code, but the characteristic parameters are different from the original parameters. Therefore, when an interleaver is set to permutation mode, the output codeword may not have the characteristics of the BCH code.
  • the encoder of FIG 2 can be comprised of two component encoders and one interleaver interposed between the component encoders.
  • a pre-stage component encoder corresponding to one of the two sub-polynomials encodes 7 input information bits into 11 first codeword bits, 4 of which are added as redundancy bits.
  • the first codeword bits are applied to a post-stage component encoder after interleaving by the interleaver.
  • the post-stage component encoder encodes the 11 codeword bits into 15 final codeword bits, 4 of which are added as redundancy bits. Therefore, the pre-stage component encoder corresponds to a (11,7) BCH code and the post-stage component encoder corresponds to a (15,11) BCH code. Further, a random interleaver is typically used for the interleaver.
  • FIG. 3 illustrates a format of codewords generated through an analysis of a serial concatenated code.
  • a first codeword 311 the lowest codeword, is generated from a first component encoder, and comprised of an information bit stream k1 and a redundancy bit stream r1.
  • the first codeword 311 is input to a succeeding post-state component encoder and used in generating a upper codeword.
  • a (p-3) codeword 312 is generated from a (p-3) component encoder, and comprised of an information bit stream k(p-3) and a redundancy bit stream r(p-3) provided from a pre-stage.
  • a (p-2) codeword 313 is generated from the (p-3)codeword 312, and comprised of the information bit stream k(p-2) and the redundancy bit stream r(p-2).
  • a final codeword bit stream np is generated by repeatedly performing a corresponding sub-codeword generating process on the lower codeword.
  • a codeword to be transmitted is comprised of k bits, and (n-k) redundancy bits are added thereto.
  • FIGS. 4 to 9 Various decoding schemes corresponding to the encoding scheme of FIG. 2 are shown in FIGS. 4 to 9 .
  • the decoding schemes include a plurality of serially concatenated component decoders each having different generator polynomials.
  • a first-state component decoder can decode either the uppermost codeword 316 or the lowermost codeword 311 of FIG. 3 .
  • the serial concatenated component decoders perform soft decision, and a MAP (Maximum A Posteriori probability) or SISO (Soft-in, Soft-Output) decoder is typically used for the component decoders.
  • a received information bit or information sample
  • a received redundancy bit or redundancy sample
  • the decoder in the receiver decodes a codeword comprised of the information bit stream and the redundancy bit stream by dividing the redundancy bit stream into several redundancy groups and then applying them to the corresponding component decoders, respectively.
  • FIG. 4 illustrates a decoder having a serial concatenated structure according to a first embodiment of the present invention, wherein the first-stage component decoder decodes the uppermost codeword 316 of FIG. 3 .
  • a component decoder 411 performs MAP/SISO decoding on the received information bit stream kp and its associated redundancy bit stream rp constituting the uppermost codeword, to output a decoded word bit stream kp.
  • a deinterleaver 412 deinterleaves the decoded word bit stream kp in reverse operation of interleaving performed in the transmission side.
  • a component decoder 413 performs MAP/SISO decoding on the decoded word bit stream n(p-1) output from the deinterleaver 412 and its associated received redundancy bit stream r(p-1), to output a decoded word bit stream k(p-1).
  • the component decoder 413 provides the component decoder 411 with extrinsic information Ext(p-1) for iterative decoding.
  • the component decoder 411 performs the decoding, after the gain of the input bits is adjusted with reference to the extrinsic information provided.
  • a deinterleaver 414 deinterleaves a decoded word bit stream k2 output from a pre-stage component decoder in reverse operation of interleaving performed in the transmission side.
  • a component decoder 415 performs MAP/SISO decoding on the decoded word bit stream n1 output from the deinterleaver 414 and its associated redundancy bit stream r1, to output a decoded final information bit stream k1.
  • the component decoder 415 provides a pre-stage component decoder with extrinsic information Ext(1) for iterative decoding.
  • FIG. 5 shows the decoder wherein the first-stage component decoder decodes the uppermost codeword, for a (15,7) BCH code.
  • the outer 4 bits out of 8 redundancy bits of the (15,7) BCH code will be referred to as the first redundancy group, and the inner 4 bits will be referred to as the second redundancy group.
  • a deinterleaver 512 deinterleaves the k2 information bits in reverse operation of interleaving performed in the transmission side.
  • the extrinsic information is iterative decoding information indicating reliability of the bits
  • the pre-stage component decoder 511 controls a reliability or a gain of the input symbol bits depending on the extrinsic information.
  • a switch 514 is switched to a node 'a' in a first iterative decoding process so as not to provide the extrinsic information to the component decoder 511, and is switched to a node 'b' beginning at a second iterative decoding process so as to provide the extrinsic information to the component decoder 511.
  • FIG. 6 shows a decoder having a serial concatenated structure according to a second embodiment of the present invention, wherein the first-stage component decoder decodes the lowermost codeword 311 of FIG. 3 .
  • a component decoder 611 performs MAP/SISO decoding on the received information bit stream k1 and its associated redundancy bit stream r1 constituting the lowermost codeword, to output a decoded word bit stream n1.
  • a deinterleaver 612 deinterleaves the decoded word bit stream n1 in reverse operation of interleaving performed in the transmission side.
  • a component decoder 613 performs MAP/SISO decoding on the decoded word bit stream n1 output from the deinterleaver 612 and its associated received redundancy bit stream r2, to output a decoded word bit stream n2.
  • a deinterleaver 614 deinterleaves a decoded word bit stream output from a pre-stage component decoder in reverse operation of interleaving performed in the transmission side.
  • a component decoder 615 performs MAP/SISO decoding on the decoded word bit stream n(p-1) output from the deinterleaver 614 and its associated redundancy bit stream rp, to output a final decoded word bit stream np.
  • the interleavers can operate in the bypass mode or in the permutation mode in dependence upon the interleaving operation mode of the transmitter.
  • FIG. 7 shows the decoder wherein the first-stage component decoder decodes the lowermost codeword, for a (15,7) BCH code.
  • the inner 4 bits out of 8 redundancy bits of the (15,7) BCH code will be referred to as a first redundancy group, and the outer 4 bits will be referred to as a second redundancy group.
  • a deinterleaver 712 deinterleaves the n1 information bits in reverse operation of interleaving performed in the transmission side.
  • FIG. 8 shows a decoder having a serial concatenated structure according to a third embodiment of the present invention, wherein each component decoder provides resulting extrinsic information obtained by decoding to its pre-stage component decoder.
  • the extrinsic information is iterative decoding information
  • the pre-stage component decoder controls a gain of the input symbol bits depending on the extrinsic information.
  • a component decoder 811 performs MAP/SISO decoding on the received information bit stream k1 and its associated redundancy bit stream r1, to output a decoded word bit stream n1.
  • a deinterleaver 812 deinterleaves the decoded word bit stream n1 in reverse operation of interleaving performed in the transmission side.
  • a component decoder 813 performs MAP/SISO decoding on the decoded word bit stream n1 output from the deinterleaver 812 and its associated received redundancy bit stream r2, to output a decoded word bit stream n2. In this process, the component decoder 813 provides the component decoder 811 with extrinsic information Ext(1) for iterative decoding.
  • the component decoder 811 then controls a reliability or a gain of the input bit stream depending on the provided extrinsic information and continues decoding.
  • the component decoder 813 performs MAP/SISO decoding on the received information bit stream n2 and its associated received redundancy bit stream r2, to output a decoded word bit stream n2.
  • a deinterleaver 814 deinterleaves a decoded word bit stream output from a pre-stage component decoder in reverse operation of the interleaving performed in the transmission side.
  • a component decoder 815 performs MAP/SISO decoding on the decoded word bit stream n(p-1) output from the deinterleaver 814 and its associated redundancy bit stream rp, to output a decoded final word bit stream np. And, the information word beat K is extracted from the decoded final word bit stream np.
  • the component decoder 815 provides a pre-stage component decoder with extrinsic information Ext(p-1) for iterative decoding. The pre-stage component decoder then controls a reliability or a gain of the input bits depending on the provided extrinsic information and continues decoding.
  • the decoding is performed using the received sample.
  • the component decoder 813 is in a good channel condition, the decoding is performed using the received sample (k1, r1).
  • the deinterleavers can operate in the bypass mode or in the permutation mode in dependence upon the interleaving operation mode of the transmitter.
  • FIG. 9 shows the decoder wherein the first-stage component decoder decodes the lowermost codeword 311, for a (15,7) BCH code.
  • each component decoder provides resulting extrinsic information obtained by decoding to its pre-stage component decoder.
  • the inner 4 bits out of 8 redundancy bits of the (15,7) BCH code will be referred to as a first redundancy group, and the outer 4 bits will be referred to as a second redundancy group.
  • a deinterleaver 912 deinterleaves the n1 decoded word bits output from the component decoder 911 in reverse operation of interleaving performed in the transmission side.
  • the component decoder 913 provides the component decoder 911 with extrinsic information Extl for iterative decoding.
  • a switch 914 is switched to a node 'a' in a first iterative decoding process so as not to provide the extrinsic information to the component decoder 911, and is switched to a node 'b' beginning at a second iterative decoding process so as to provide the extrinsic information to the component decoder 911.
  • the decoding is performed using the received sample (k1, r1).
  • the deinterleaver can operate in the bypass mode or in the permutation mode in dependence upon the interleaving operation mode of the transmitter.
  • the novel decoders have a reduced trellis complexity for soft decision as compared with the existing decoder.
  • the present invention proposes a new soft decision method for linear block codes, which is intensively used in a radio communication system.
  • the invention reduces the trellis size for soft decision of the linear block codes, thereby reducing the complexity.
  • the invention proposes a decoding method for minimizing the post information bit error probability, as compared with the existing ML decoding method.

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  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
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EP99959975A 1998-12-10 1999-12-10 Decoder with serial concatenated structure in communication system Expired - Lifetime EP1055287B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR9854130 1998-12-10
KR1019980054130A KR100277764B1 (ko) 1998-12-10 1998-12-10 통신시스템에서직렬쇄상구조를가지는부호화및복호화장치
PCT/KR1999/000761 WO2000035099A1 (en) 1998-12-10 1999-12-10 Encoder/decoder with serial concatenated structure in communication system

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EP1055287B1 true EP1055287B1 (en) 2010-11-10

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BR (1) BR9907819A (ko)
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