EP0520355A1 - Composant semi-conducteur de puissance à commande d'extinction et procédé de sa fabrication - Google Patents

Composant semi-conducteur de puissance à commande d'extinction et procédé de sa fabrication Download PDF

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Publication number
EP0520355A1
EP0520355A1 EP92110493A EP92110493A EP0520355A1 EP 0520355 A1 EP0520355 A1 EP 0520355A1 EP 92110493 A EP92110493 A EP 92110493A EP 92110493 A EP92110493 A EP 92110493A EP 0520355 A1 EP0520355 A1 EP 0520355A1
Authority
EP
European Patent Office
Prior art keywords
region
cathode
base layer
mosfet
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP92110493A
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German (de)
English (en)
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EP0520355B1 (fr
Inventor
Kenneth Johansson
Klas Lilja
Thomas Dr. Stockmeier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ABB Asea Brown Boveri Ltd
ABB AB
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ABB Asea Brown Boveri Ltd
Asea Brown Boveri AB
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Application filed by ABB Asea Brown Boveri Ltd, Asea Brown Boveri AB filed Critical ABB Asea Brown Boveri Ltd
Publication of EP0520355A1 publication Critical patent/EP0520355A1/fr
Application granted granted Critical
Publication of EP0520355B1 publication Critical patent/EP0520355B1/fr
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices
    • H01L29/745—Gate-turn-off devices with turn-off by field effect
    • H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure

Definitions

  • the invention further relates to a method for producing such a component.
  • GTO G ate T urn O ff
  • the GTO divides the entire chip area into a large number of unit cells connected in parallel. These components can be switched on and off via the gate contact; Because of the high gate currents when switching off, however, an enormous amount of circuitry for the gate control must be accepted.
  • MOS-controlled components For some years now, the development of MOS-controlled components has been increasingly promoted in power electronics.
  • the advantage of these MOS-controlled components lies mainly in the high input impedance at the control electrode. It enables the component to be controlled with a comparatively very low level of performance.
  • bipolar structures e.g. thyristors
  • the simple and in particular low-power control that is used in the power MOSFETs should be retained as far as possible.
  • MOS-controlled thyristor or MCT M OS C ontrolled T hyristor
  • GTO GTO consists of a plurality of adjacent, parallel-connected unit cells
  • the shutdown is achieved a short-circuit of the emitter with the p-type base by means of switchable emitter shorts.
  • MOSFETs integrated with the emitter serve as switches, which can naturally be designed as n- or p-channel MOSFETs.
  • the p short-circuit area is bridged by a MOSFET.
  • this additional layer lies between the cathode and the p-n-p-n thyristor structure and effectively prevents the electron injection leading to filamentation.
  • the essence of the invention is to provide a five-layer structure between the anode and the cathode instead of the usual bipolar, four-layer pnpn thyristor structure, with a p auf-doped layer directly connected to the cathode as the fifth layer on the cathode side p short-circuit area is arranged.
  • Switch-off area and p-short-circuit area are introduced into the semiconductor substrate in a self-adjusting manner through a first window between the first and second gate electrodes.
  • the p short-circuit area is bridged by a first MOSFET.
  • the injection takes place through a second cathode area arranged next to the switch-off area.
  • the p-type short-circuit region lies between the cathode and the pnpn thyristor structure and prevents it effective the electron injection leading to filamentation.
  • the holes injected by the anode are removed during the switch-off and thus effectively an avalanche breakdown prevented between the p-short-circuit area and the switch-off area.
  • FIG. 1 shows, in cross section, a plurality of unit cells EZ of a preferred embodiment of the component according to the invention, each of which is arranged in mirror image to one another.
  • the component is generally therefore hereinafter be referred to a five layers comprehensive, an insulated gate-controlled bipolar switch and is briefly as IG-FiBS (Insulated Gate Bipolar controlled F ive layer S witch).
  • IG-FiBS Insulated Gate Bipolar controlled F ive layer S witch
  • the IG-FiBS consists of a semiconductor substrate 1 with a first (lower) and a second (upper) main surface.
  • the first main surface is provided with a (metallic) anode contact 11, which is connected to the anode A.
  • the second main surface carries a (metallic) cathode contact 2 within each unit cell, which in turn is connected to the cathode K.
  • a layer sequence of five layers doped with alternating polarity is arranged within the semiconductor substrate 1, which layers successively have a p+-doped anode layer 10, an n ⁇ -doped n base layer 9, a p+-doped p -Base layer 8, a n-doped cut-off region 6 embedded in the p-base layer 8 and a p-doped p-short circuit region 5 embedded in the cut-off region 6.
  • the anode layer 10 is contacted by the anode contact 11; the p-short-circuit region 5 or a p+-doped contact region 12 which is additionally embedded in the p-short circuit region 5 to improve the contact are contacted on the other side of the semiconductor substrate 1 by the cathode contact 2.
  • a first MOSFET M1 and on the other side a second MOSFET M2 are integrated in the semiconductor substrate 1 in each unit cell EZ.
  • the first MOSFET M1 is composed of an n+-doped, first cathode region 4, the p-short-circuit region 5, the switch-off region 6 or an adjacent, n investigating-doped region that is let into the p-short circuit region 5 and connected to the cathode contact 2 , second cathode region 7, and a first gate electrode G1 arranged insulated above the p short-circuit region 5 (gate insulation 3).
  • it is an n-channel MOSFET, the channel area of which is part of the p-short-circuit area 5 that occurs between the switch-off area 6 and the first cathode area 4 and the second main surface.
  • the second MOSFET M2 is formed from the p-base layer 8, which comes to the second main surface, the switch-off region 6, the p-short-circuit region 5 and a second gate electrode G2 arranged insulated above the switch-off region 6 (gate insulation 3).
  • it is a p-channel MOSFET, the channel region of which is part of the switch-off region 6 that occurs between the trough-shaped p short-circuit region 5 and the p-base layer 8.
  • each unit cell EZ having a common second gate electrode G2 with the unit cell adjacent on one side and a unit gate adjacent to the unit cell on the other side share common second cathode region 7.
  • a first window F1 is formed between the first and second gate electrodes G1 and G2 of each unit cell EZ
  • a second window F2 is formed between the first gate electrodes G1 of adjacent unit cells.
  • the switch-off region 6 and the p-short-circuit region 5 can be introduced into the already existing p-base layer 8 in succession through the first windows F1 in a self-adjusting manner.
  • the second cathode region 7 is accordingly introduced through the second window F2. From the start, the gate electrodes and the windows in between act as masks for the various implantations.
  • 1 can be in an equivalent circuit as an anti-parallel series circuit consisting of a diode and a thyristor, wherein the diode can be bridged by the first MOSFET M1, while the second MOSFET M2 is connected between the cathode and the gate of the thyristor.
  • the function of the component according to FIG. 1 is as follows: in the ON state, the first gate electrode G1 has a positive gate voltage relative to the cathode K.
  • the first MOSFET M1 is thus switched on and short-circuits the cathode contact 2 with the switch-off region 6 and the adjacent second cathode region 7.
  • a particularly good transmission behavior results from the heavily n-doped second cathode region, which acts as an effective electron emitter for the rest of the component.
  • the short circuit reduces the active structure of the component to a pnpn sequence of four layers (anode layer 10, n base layer 9, p base layer 8 and second cathode region 7), which - apart from the channel resistance of the first MOSFET, which is very can be made small - how a conventional thyristor behaves.
  • the second MOSFET M2 is blocked in this phase.
  • the gate voltage at the first gate electrode G1 is reduced, so that the first MOSFET M1 changes to the blocked state.
  • the IG-FiBS is converted from the four-layer to a five-layer (p-n-p-n-p) structure and switches off.
  • the additional, p-doped switch-off region 5 basically completely stops the electron injection from the cathode side.
  • the second MOSFET M2 is switched on, which then takes over the full cut-off current. This is necessary to make an avalanche breakthrough at the PN junction between the p short circuit area 5 and the switch-off area 6 to prevent.
  • This PN junction has a rather low breakdown voltage (on the order of 10-20 V), which is far below the blocking capability of the entire component. An avalanche breakthrough at this PN junction would then prevent the component from being switched off or at least considerably slow down the switch-off process.
  • the cathode is formed by the p-doped p short-circuit region 5 when it is switched off. For this reason, electron injection is not possible at all. Rather, an increase in the current in the IG-FiBS structure during shutdown results in a faster degradation of the stored charge carriers, i.e. in a faster turn-off.
  • the IG-FiBS is therefore self-stabilizing.
  • the structure shown in FIG. 1 comprises the two MOSFETs M1 and M2, both of which - as explained above - are necessary for the switch-off process.
  • the component can then be switched on at certain points for switching on the component a third MOSFET M3 (Fig. 2A-C; Fig. 3) can be provided.
  • This third MOSFET M3 is basically formed by the n-base layer 9 drawn on the second main surface, the p-base layer 8 drawn on the second main surface, the second cathode region 7 (FIGS. 2A-C) and the switch-off region 6 (FIG. 3) , and an associated gate electrode arranged insulated over the part of the p-base layer 8 which comes to the second main surface.
  • this associated gate electrode can be a separate third gate electrode G3, which is arranged between the first gate electrodes G1 of two adjacent unit cells EZ.
  • the number of third MOSFETs M3 can be selected independently of and less than the number of unit cells EZ, so that e.g. -
  • a third MOSFET M3 gate electrode G3
  • the first and third gate electrodes G1 and G3 are then separated from one another by a third window F3 (FIG. 2A), through which the second cathode region 7 (individually for each unit cell EZ) can be introduced into the p-base layer 8 in a self-adjusting manner.
  • the function of the further gate electrode can also be taken over by the second gate electrode G2, as shown in FIG. 3.
  • Such a component is apparent from the embodiment shown in FIG. 1 in that the n-base layer 9 is also led to the second main surface of the semiconductor substrate 1 under certain or all of the second gate electrodes G2.
  • channel implantation areas 13 for MOSFET M2 in FIG. 2B
  • the p-type channel implantation region 13 converts the second MOSFET M2 from a normally-off to a normally-on MOSFET (depletion-type MOSFET).
  • the second gate electrode G2 of the second MOSFET M2 is short-circuited directly to the cathode K and is therefore at zero potential.
  • the gates of the MOSFETs M1 and M3 are then driven with an external gate voltage which is the same for both MOSFETs.
  • the component is initially in the on state, the gate voltage of the MOSFETs M1 and M3 taking a positive value (for example 10 V). M1 and M3 are therefore both switched on and the FiBS behaves like a thyristor that is supplied with a continuous ignition current. If this gate voltage is reduced (eg from +10 V to 0 V), M1 and M3 begin to switch off. The FiBS is then converted into a 5-layer structure and also starts to switch off. The voltage falling at the blocking transition between the cut-off area 6 and the p-short-circuit area 5 thus increases. As a result, the voltage of the switch-off region 6 becomes positive compared to the gate voltage of the second MOSFET M2.
  • a positive value for example 10 V
  • This MOSFET will therefore automatically turn on and the hole current that comes from the cathode K, take over.
  • the FiBS can then - as already described above - switch off without problems of current distribution or filamentation, since electron injection from the cathode is reliably prevented.
  • the gate voltage is raised again to switch on the component. M1 and M3 then turn on and the FiBS is again converted into a thyristor which is fired by the third MOSFET M3 and of course turns on. Since the electron injection from the cathode is limited by the current flowing in the MOSFET M1, the current distribution is also much more homogeneous when the FiBS is switched on than with the GTO or MCT.
  • the gate electrodes G1 to G3 of all three MOSFETs M1 to M3 are supplied with the same external gate voltage.
  • this gate voltage is kept at a positive value (e.g. +10 V). It is made negative for switching off (e.g. -10 V) and positive again for switching on.
  • the second MOSFET M2 is controlled by a different signal than the first MOSFET M1.
  • the gate voltage of the MOSFET M1 goes from a positive value to zero, and the gate voltage of the MOSFET M2 goes from zero to a negative value.
  • the reverse process results for the switch-on process.
  • an essential feature of the present invention is the largely self-adjusting manufacturability of the component structure.
  • Selected steps of an exemplary manufacturing process for a component according to FIG. 2A, which illustrate this self-adjustment, are shown in FIGS. 4A to 4F for a unit cell EZ.
  • the illustration is limited to the structure on the cathode side.
  • the manufacture starts with an n + -doped semiconductor substrate 1, which forms the n base layer 9.
  • the anode layer 10 is introduced into the n-base layer 9 in succession from the first main surface, and the p-base layer 8 from the second main surface.
  • the second main surface is then covered with the gate insulation 3, to which a continuous gate electrode layer 14 made of poly-Si is applied (FIG. 4A).
  • the third window F3 is then opened by photostructuring and etching, through which a first implantation IM1 for the later second cathode region 7 is introduced into the semiconductor substrate 1.
  • the unit cell at this stage has the configuration shown in Fig. 4A.
  • the first window F1 is then opened in the gate electrode layer 14.
  • the gate electrode layer 14 thereby breaks down into the later gate electrodes G1, G2 and G3.
  • a second implantation IM2 for the later switch-off region 6 is introduced into the semiconductor substrate 1 through the first window F1.
  • the unit cell at this stage has the configuration shown in Fig. 4B.
  • a subsequent drive-in already forms the switch-off region 6 and the second cathode region 7 in a first stage, so that a third implantation IM3 for the subsequent p-short-circuit region 5 can then be introduced into the switch-off region 6 through the first window F1.
  • the unit cell at this stage has the configuration shown in Fig. 4C.
  • a further drive-in further develops areas 6 and 7 and creates p-short-circuit area 5.
  • the first window F1 is then partially covered with the aid of an additional mask (not shown) and a fourth implantation IM4 for the later first cathode region 4, which is limited in width, is introduced into the p-short-circuit region 5 within the first window F1.
  • the additional mask is then removed again.
  • the unit cell at this stage has the configuration shown in Figure 4D.
  • a final drive-in then forms the first cathode region 4.
  • the gate electrodes G1, G2 and G3 are then completely covered by the gate insulation 3 and two openings for the contacting of the second gate electrode G2 and the cathode connection are etched into the gate insulation 3 (FIG. 4E).
  • a continuous cathode contact 2 is deposited on the gate insulation 3, which simultaneously contacts the second gate electrode G2, the first cathode region 4 and the p-short circuit region 5 through the two openings (FIG. 4F).
  • the gate electrode G2 is thus directly connected to the cathode K in this embodiment according to the control alternative 1 explained above.
  • the complete unit cell of the component created in this process has the structure shown in FIG. 5.
  • an additional n short-circuit region 16 (anode short) and a p-zone arranged between n short-circuit region 16 and n base layer 9 are provided on the anode side (see, for example, EP-A1-0 327 901).
  • Exemplary courses of the doping concentrations along the section lines A-A to E-E shown in broken lines in FIG. 5 are correspondingly shown in FIGS. 6A to 6E.
  • x denotes the depth measured from the respective main surface in ⁇ m
  • c the total doping concentration (in cm ⁇ 3)
  • c1 the concentration of P
  • c2 the concentration of B
  • c3 the concentration of As (all in cm ⁇ 3).
  • the invention results in an easily controllable, safely switchable high-performance component, in which filamentation of the current when switching off is avoided, and which can be produced comparatively easily and with high precision.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)
EP92110493A 1991-06-28 1992-06-22 Composant semi-conducteur de puissance à commande d'extinction et procédé de sa fabrication Expired - Lifetime EP0520355B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4121375A DE4121375A1 (de) 1991-06-28 1991-06-28 Abschaltbares leistungshalbleiter-bauelement sowie verfahren zu dessen herstellung
DE4121375 1991-06-28

Publications (2)

Publication Number Publication Date
EP0520355A1 true EP0520355A1 (fr) 1992-12-30
EP0520355B1 EP0520355B1 (fr) 1995-12-06

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EP92110493A Expired - Lifetime EP0520355B1 (fr) 1991-06-28 1992-06-22 Composant semi-conducteur de puissance à commande d'extinction et procédé de sa fabrication

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US (1) US5286981A (fr)
EP (1) EP0520355B1 (fr)
JP (1) JPH05218395A (fr)
DE (2) DE4121375A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0630054A1 (fr) * 1993-06-14 1994-12-21 Kabushiki Kaisha Toshiba Thyristor à grille isolée et procédé de mise en service
WO2004102671A1 (fr) * 2003-05-19 2004-11-25 Stmicroelectronics S.R.L. Dispositif de puissance a vitesse de commutation elevee, et son procede de production

Families Citing this family (14)

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Publication number Priority date Publication date Assignee Title
US5151762A (en) * 1990-04-12 1992-09-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, fabricating method thereof and flash control device using the semiconductor device
JPH04284669A (ja) * 1991-03-14 1992-10-09 Fuji Electric Co Ltd 絶縁ゲート制御サイリスタ
JPH06169089A (ja) * 1992-05-07 1994-06-14 Nec Corp 縦型ｍｏｓｆｅｔの製造方法
US5498884A (en) * 1994-06-24 1996-03-12 International Rectifier Corporation MOS-controlled thyristor with current saturation characteristics
US5444272A (en) * 1994-07-28 1995-08-22 International Rectifier Corporation Three-terminal thyristor with single MOS-gate controlled characteristics
US5510281A (en) * 1995-03-20 1996-04-23 General Electric Company Method of fabricating a self-aligned DMOS transistor device using SiC and spacers
JPH09246523A (ja) * 1996-03-13 1997-09-19 Mitsubishi Electric Corp 半導体装置
US6110763A (en) * 1997-05-22 2000-08-29 Intersil Corporation One mask, power semiconductor device fabrication process
US20030122149A1 (en) * 1998-04-15 2003-07-03 Junichi Sakano Complex semiconductor device and electric power conversion appratus using it
GB9921068D0 (en) * 1999-09-08 1999-11-10 Univ Montfort Bipolar mosfet device
US6391689B1 (en) * 2001-06-06 2002-05-21 United Microelectronics Corp. Method of forming a self-aligned thyristor
US7274076B2 (en) * 2003-10-20 2007-09-25 Micron Technology, Inc. Threshold voltage adjustment for long channel transistors
US20140157223A1 (en) * 2008-01-17 2014-06-05 Klas Olof Lilja Circuit and layout design methods and logic cells for soft error hard integrated circuits
CN104425246B (zh) * 2013-08-27 2018-01-23 无锡华润上华科技有限公司 绝缘栅双极型晶体管及其制备方法

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DE3447220A1 (de) * 1983-12-30 1985-07-11 General Electric Co., Schenectady, N.Y. Thyristor mit abschaltvermoegen mit verbessertem emitter-bereich und verfahren zu seiner herstellung
DE4011509A1 (de) * 1988-04-22 1990-10-25 Asea Brown Boveri Bidirektionales, abschaltbares halbleiterbauelement
EP0424710A2 (fr) * 1989-10-23 1991-05-02 Mitsubishi Denki Kabushiki Kaisha Thyristor et méthode de fabrication
EP0454201A2 (fr) * 1990-04-09 1991-10-30 Philips Electronics Uk Limited Dispositif semi-conducteur comprenant un thyristor
EP0487869A1 (fr) * 1990-11-29 1992-06-03 Asea Brown Boveri Ag Dispositif semi-conducteur de puissance, à extinction

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US4133011A (en) * 1977-12-23 1979-01-02 International Business Machines Corporation Sampled data positioning system employing a model of the physical system for time optimal control
US4278476A (en) * 1979-12-05 1981-07-14 Westinghouse Electric Corp. Method of making ion implanted reverse-conducting thyristor
US4604638A (en) * 1983-05-17 1986-08-05 Kabushiki Kaisha Toshiba Five layer semiconductor device with separate insulated turn-on and turn-off gates
CA1216968A (fr) * 1983-09-06 1987-01-20 Victor A.K. Temple Dispositif a semiconducteur a grille isolee a court-circuit base-source ameliore et methode de fabrication de ce court-circuit
DE3689680T2 (de) * 1985-09-30 1994-06-23 Toshiba Kawasaki Kk Mittels Steuerelektrode abschaltbarer Thyristor mit unabhängigen Zünd-/Lösch-Kontrolltransistoren.
US4717940A (en) * 1986-03-11 1988-01-05 Kabushiki Kaisha Toshiba MIS controlled gate turn-off thyristor
DE3623750A1 (de) * 1986-07-14 1988-01-21 Siemens Ag Abschaltbarer thyristor
DE3832208A1 (de) * 1988-09-22 1990-03-29 Asea Brown Boveri Steuerbares leistungshalbleiterbauelement
EP0409010A1 (fr) * 1989-07-19 1991-01-23 Asea Brown Boveri Ag Dispositif semi-conducteur de puissance, à extinction

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3447220A1 (de) * 1983-12-30 1985-07-11 General Electric Co., Schenectady, N.Y. Thyristor mit abschaltvermoegen mit verbessertem emitter-bereich und verfahren zu seiner herstellung
DE4011509A1 (de) * 1988-04-22 1990-10-25 Asea Brown Boveri Bidirektionales, abschaltbares halbleiterbauelement
EP0424710A2 (fr) * 1989-10-23 1991-05-02 Mitsubishi Denki Kabushiki Kaisha Thyristor et méthode de fabrication
EP0454201A2 (fr) * 1990-04-09 1991-10-30 Philips Electronics Uk Limited Dispositif semi-conducteur comprenant un thyristor
EP0487869A1 (fr) * 1990-11-29 1992-06-03 Asea Brown Boveri Ag Dispositif semi-conducteur de puissance, à extinction

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0630054A1 (fr) * 1993-06-14 1994-12-21 Kabushiki Kaisha Toshiba Thyristor à grille isolée et procédé de mise en service
WO2004102671A1 (fr) * 2003-05-19 2004-11-25 Stmicroelectronics S.R.L. Dispositif de puissance a vitesse de commutation elevee, et son procede de production

Also Published As

Publication number Publication date
DE59204557D1 (de) 1996-01-18
EP0520355B1 (fr) 1995-12-06
US5286981A (en) 1994-02-15
DE4121375A1 (de) 1993-01-14
JPH05218395A (ja) 1993-08-27

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