CN104425246B - 绝缘栅双极型晶体管及其制备方法 - Google Patents

绝缘栅双极型晶体管及其制备方法 Download PDF

Info

Publication number
CN104425246B
CN104425246B CN201310379443.1A CN201310379443A CN104425246B CN 104425246 B CN104425246 B CN 104425246B CN 201310379443 A CN201310379443 A CN 201310379443A CN 104425246 B CN104425246 B CN 104425246B
Authority
CN
China
Prior art keywords
type
substrate
heavily doped
polysilicon
bipolar transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310379443.1A
Other languages
English (en)
Other versions
CN104425246A (zh
Inventor
钟圣荣
周东飞
邓小社
王根毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CSMC Technologies Corp
Original Assignee
CSMC Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSMC Technologies Corp filed Critical CSMC Technologies Corp
Priority to CN201310379443.1A priority Critical patent/CN104425246B/zh
Priority to US14/902,284 priority patent/US9881994B2/en
Priority to PCT/CN2014/085082 priority patent/WO2015027878A1/zh
Priority to EP14840868.5A priority patent/EP3043387B1/en
Publication of CN104425246A publication Critical patent/CN104425246A/zh
Priority to US15/840,791 priority patent/US10084036B2/en
Application granted granted Critical
Publication of CN104425246B publication Critical patent/CN104425246B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/6634—Vertical insulated gate bipolar transistors with a recess formed by etching in the source/emitter contact region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)

Abstract

本发明公开了一种绝缘栅双极型晶体管（IGBT），其衬底为N型，N型衬底背面设有P型区，P型区背面设有背面金属结构，终端结构内设有终端保护环，有源区的正面设有多晶硅栅，衬底上多晶硅栅的两侧设有侧墙，衬底上设有覆盖多晶硅栅和侧墙的层间介质，层间介质上覆盖有金属引线层，有源区的衬底内设有N型的载流子增强区，载流子增强区内设有P型体区，P型体区内设有N型重掺杂区，N型重掺杂区内设有P型重掺杂区，P型重掺杂区表面形成有向内凹陷浅坑，深度为0.15微米～0.3微米。本发明还公开了一种IGBT的制备方法。本发明通过设置载流子增强区，能够增加沟道的载流子浓度，降低导通压降。同时该浅坑能够使器件获得良好的杂质分布和更大的金属接触面积，提高了器件的性能。

Description

绝缘栅双极型晶体管及其制备方法
技术领域
本发明涉及半导体器件的制造方法，特别是涉及一种绝缘栅双极型晶体管，还涉及一种绝缘栅双极型晶体管的制备方法。
背景技术
IGBT（Insulated Gate Bipolar Transistor），绝缘栅双极型晶体管，是由双极型三极管（BJT）和金属氧化物半导体场效应管（MOS）组成的功率半导体器件。
降低IGBT器件的导通压降，能够获得更好的电性能。
发明内容
基于此，为了解决传统绝缘栅双极型晶体管导通压降过高的问题，有必要提供一种低导通压降的绝缘栅双极型晶体管。
一种绝缘栅双极型晶体管，包括***的终端结构和被所述终端结构包围的有源区，所述绝缘栅双极型晶体管的衬底为N型衬底，所述N型衬底背面设有P型区，所述P型区背面设有背面金属结构，终端结构内设有终端保护环，有源区的所述衬底正面设有多晶硅栅，衬底上所述多晶硅栅的两侧设有侧墙，所述衬底上设有覆盖所述多晶硅栅和侧墙的层间介质，所述层间介质上覆盖有金属引线层，有源区的所述衬底内设有N型的载流子增强区，所述载流子增强区内设有P型体区，所述P型体区内设有N型重掺杂区，所述N型重掺杂区内设有P型重掺杂区，所述P型重掺杂区表面形成有向内凹陷的凹坑区域，所述凹坑区域相对于两侧的衬底向内凹陷的深度为0.15微米～0.3微米。
在其中一个实施例中，所述衬底的材质为硅、碳化硅、砷化镓、磷化铟或锗硅中的一种。
在其中一个实施例中，所述衬底的材质为晶向<100>的单晶硅。
本发明还提供一种绝缘栅双极型晶体管的制备方法。
一种绝缘栅双极型晶体管的制备方法，包括：提供衬底，在所述衬底的正面形成场氧层，用终端保护环光刻版光刻并刻蚀所述场氧层，并向被刻蚀开的区域下面的衬底内注入P型离子，形成终端保护环；用有源区光刻版光刻并刻蚀掉有源区区域的所述场氧层，并在场氧层被刻蚀掉的所述衬底上淀积多晶硅，在淀积的多晶硅上形成保护层，再用多晶硅光刻版光刻并刻蚀掉多余的多晶硅和保护层，形成多晶硅栅；用P阱光刻版光刻并刻蚀开所述多晶硅栅，并向被刻蚀开的多晶硅栅下面的衬底内注入N型离子，再推结后形成载流子增强区；用所述P阱光刻版光刻并向载流子增强区内注入P型离子，推结后形成P型体区；借助多晶硅栅向P型体区内进行自对准注入N型离子，推结后形成N型重掺杂区；在多晶硅栅两侧形成侧墙，再向所述N型重掺杂区内注入P型离子，推结后形成P型重掺杂区；形成层间介质，进行绝缘栅双极型晶体管的正面金属化工艺，进行背面减薄、P型离子注入及退火工艺，及进行绝缘栅双极型晶体管的背面金属化工艺。
在其中一个实施例中，所述在多晶硅栅两侧形成侧墙的步骤之后，向所述N型重掺杂区内注入P型离子的步骤之前，还包括对所述N型重掺杂区进行刻蚀形成凹坑区域的步骤，所述凹坑区域向内凹陷的深度相对于两侧的衬底为0.15微米～0.3微米。
在其中一个实施例中，所述在淀积的多晶硅上形成保护层的步骤包括在所述多晶硅表面形成第一氧化层，在所述第一氧化层表面淀积氮化硅层。
在其中一个实施例中，所述进行绝缘栅双极型晶体管的正面金属化工艺的工艺之后还包括再向所述P型重掺杂区内进行一次P型离子注入的步骤。
在其中一个实施例中，所述向被刻蚀开的区域下面的衬底内注入P型离子，形成终端保护环的步骤中，所述P型离子为硼离子；所述向被刻蚀开的多晶硅栅下面的衬底内注入N型离子的步骤中，所述N型离子为磷离子；所述用P阱光刻版光刻并向载流子增强区内注入P型离子的步骤中，所述P型离子为硼离子；所述借助多晶硅栅向P型体区内进行自对准注入N型离子的步骤中，所述N型离子为砷离子；所述向N型重掺杂区内注入P型离子的步骤中，所述P型离子为硼离子；所述去除保护层后向所述多晶硅栅进行多晶硅注入掺杂的步骤中，注入的离子为磷离子。
在其中一个实施例中，所述在多晶硅栅两侧形成侧墙的步骤包括：淀积第二氧化层、然后通过腐蚀去除多余的所述第二氧化层，剩余的第二氧化层形成所述侧墙。
在其中一个实施例中，所述进行绝缘栅双极型晶体管的正面金属化工艺的步骤包括用接触孔光刻版光刻并刻蚀出接触孔，并在所述层间介质上溅射导电金属，之后采用金属光刻版光刻并刻蚀溅射的金属形成覆盖所述层间介质的金属引线层。
上述绝缘栅双极型晶体管，通过设置载流子增强区，能够增加沟道的载流子浓度，降低导通压降。同时在P型重掺杂区内形成有0.15微米～0.3微米的浅坑，能够使器件获得良好的杂质分布和更大的金属接触面积，降低功耗，提高产品的可靠性，并进一步降低导通压降。
附图说明
图1是一实施例中绝缘栅双极型晶体管的结构示意图；
图2是一实施例中绝缘栅双极型晶体管的制备方法的流程图；
图3A～图3F是一实施例中采用绝缘栅双极型晶体管的制备方法制备的绝缘栅双极型晶体管在制备过程中的局部剖视图。
具体实施方式
为使本发明的目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
图1是一实施例中绝缘栅双极型晶体管100的结构示意图，包括***的终端结构（图1未示）和被终端结构包围的有源区。绝缘栅双极型晶体管100的衬底为N型衬底10，衬底10背面设有P型区16，P型区16背面设有背面金属结构18，终端结构内设有终端保护环（图1未示）。有源区的衬底10正面设有多晶硅栅31，衬底10上多晶硅栅31的两侧设有侧墙72，衬底10上设有覆盖多晶硅栅31和侧墙72的层间介质81，层间介质81上覆盖有金属引线层91。有源区的衬底10内设有N型的载流子增强（Carrier Enhanced）区41，载流子增强区41内设有P型体区51，P型体区51内设有N型重掺杂区61，N型重掺杂区61内设有P型重掺杂区71，P型重掺杂区71表面形成有向内凹陷的凹坑区域62，凹坑区域62相对于两侧的衬底向内凹陷的深度（即图1中的a）为0.15微米～0.3微米。
上述绝缘栅双极型晶体管通过设置载流子增强区41，能够增加沟道的载流子浓度，降低导通压降。同时在向N型重掺杂区61内注入P型离子之前、于P型重掺杂区71内刻蚀出0.15微米～0.3微米的浅坑（凹坑区域62），能够使器件获得良好的杂质分布和更大的金属接触面积，提高器件的性能，进一步降低导通压降。
衬底10的材质为硅、碳化硅、砷化镓、磷化铟或锗硅中的一种。在其中一个实施例中，衬底10采用晶向是<100>的单晶硅。
参见图2，本发明还提供一种上述绝缘栅双极型晶体管100的制备方法，包括下列步骤：
S110，提供衬底，在衬底的正面形成场氧层，并形成终端保护环。
衬底10的材质为硅、碳化硅、砷化镓、磷化铟或锗硅中的一种。在本实施例中，衬底10采用晶向是<100>的单晶硅晶圆（wafer）。
在本实施例中，先在衬底10的正面生长一层场氧层20，然后采用终端保护环光刻版光刻并刻蚀掉需要形成终端保护环的衬底10正上方的场氧化层20。然后以场氧化层20为掩蔽层注入P型离子，形成终端保护环，图3A中示出了三个终端保护环21、22、23，其中终端保护环23所处的位置靠近衬底10中间的有源区区域。可以理解的，终端保护环的数量并不以本实施例为限，本领域技术人员可根据器件实际需要自行选择设置。
图3A为本实施例中步骤S110完成后绝缘栅双极型晶体管的局部结构剖视图。在本实施例中，步骤S110注入的P型离子为硼离子。可以理解的，本实施例各离子注入步骤中所给出的具体注入的P型/N型离子仅是一个较佳实施例，在其它实施例中也可以用本领域技术人员习知的其它P型/N型离子代替。
S120，在衬底的有源区区域正面形成多晶硅栅，并在多晶硅栅上形成保护层。
用有源区光刻版光刻并刻蚀掉有源区区域的场氧层20，并在场氧层20被刻蚀掉的衬底10上淀积多晶硅，在淀积的多晶硅上形成保护层，再用多晶硅光刻版光刻并刻蚀掉多余的多晶硅和保护层，形成多晶硅栅31。在本实施例中，保护层包括氮化硅层32，在淀积氮化硅之前还需要进行一次氧化，在淀积的多晶硅表面形成第一氧化层（图3B未示），再于第一氧化层上通过淀积形成氮化硅层32。相对于直接在多晶硅表面淀积氮化硅，在多晶硅栅31与氮化硅层32之间淀积一层第一氧化层能够改善应力的问题。图3B为本实施例中步骤S120完成后绝缘栅双极型晶体管的局部结构剖视图，其示出的结构位于图3A右侧。
S130，用P阱光刻版光刻并刻蚀开多晶硅栅，并向衬底内注入N型离子，再推结后形成载流子增强区。
用P阱光刻版光刻并刻蚀开多晶硅栅31，向被刻蚀开的多晶硅栅31下面的衬底10内注入N型离子。在本实施例中，步骤S130注入的N型离子为磷离子。图3C是本实施例中磷离子注入完成且还未进行推结时绝缘栅双极型晶体管的局部结构剖视图。
离子注入后，再经过高温推结形成载流子增强（Carrier Enhanced）区41。
S140，用P阱光刻版光刻并向载流子增强区内注入P型离子，推结后形成P型体区。
步骤S140采用与S130相同的光刻版。在本实施例中，步骤S140注入的P型离子为硼离子，高温推结后形成P型体区（P-body）51。图3D是本实施例中步骤S140完成后绝缘栅双极型晶体管的局部结构剖视图，其示出的结构位于图3C右侧。
S150，借助多晶硅栅向P型体区内进行自对准注入N型离子，推结后形成N型重掺杂区。
在本实施例中，步骤S150注入的N型离子为砷离子，高温推结后形成N型重掺杂区（NSD）61。图3E是本实施例中步骤S150完成后绝缘栅双极型晶体管的局部结构剖视图。
S160，在多晶硅栅两侧形成侧墙，再向N型重掺杂区内注入P型离子，推结后形成P型重掺杂区。
先淀积一层第二氧化层，然后对器件进行侧墙腐蚀，多余的第二氧化层被腐蚀掉，在多晶硅栅31两侧形成侧墙（spacer）72。
在本实施例中，在侧墙72形成后，向N型重掺杂区61内注入P型离子之前，还包括对N型重掺杂区61进行硅刻蚀、形成凹坑区域62的步骤。凹坑区域62是一个向内凹陷的深度为0.15微米～0.3微米的浅坑。
在向N型重掺杂区61内注入P型离子之前，于P型重掺杂区内刻蚀出0.15微米～0.3微米的浅坑（凹坑区域62），能够使器件获得良好的杂质分布和更大的金属接触面积，降低功耗，提高产品的可靠性，并进一步降低导通压降。
刻蚀出凹坑区域62后进行P型离子的注入。在本实施例中，注入的P型离子为硼离子。注入完成后进行高温推结，形成P型重掺杂区（PSD）71。
S170，去除保护层后进行多晶硅栅注入掺杂。
如前述，本实施例中保护层包括氮化硅层32。去除多晶硅栅31表面的氮化硅层32后，再对多晶硅栅31进行N型离子的注入掺杂。在本实施例中，可以用多晶硅光刻版光刻后进行多晶硅栅31的注入掺杂。图3F是本实施例中步骤S170完成后绝缘栅双极型晶体管的局部结构剖视图。
步骤S170完成后可以进行常规的生成层间介质（ILD），正面金属化，背面减薄、注入及退火，以及背面金属化工艺。以下同样给出一个具体的实施例。
S180，形成覆盖多晶硅栅和侧墙表面的层间介质。
在器件表面淀积硼磷硅玻璃（BPSG）后进行热回流，形成覆盖多晶硅栅31和侧墙72表面的层间介质81。
S190，正面金属化。
采用接触孔光刻版进行光刻和接触孔（contact）刻蚀，并在器件表面溅射导电金属，之后采用金属光刻版刻蚀该导电金属，形成覆盖层间介质81的金属引线层91。
S200，背面减薄、P注入及退火。
将衬底10的背面减薄至所需厚度，对衬底10背面进行P型离子注入并退火，形成P型区16。P型区16与衬底10构成衬底PN结。在本实施例中，步骤S200注入的P型离子是硼离子。
S210，背面金属化。
对衬底10背面溅射导电金属，在P型区16表面形成背面金属结构18，作为集电极金属引线。图1是本实施例中步骤S210完成后绝缘栅双极型晶体管的局部结构剖视图。
上述绝缘栅双极型晶体管的制备方法，通过在步骤S130中用P阱光刻版将多晶硅栅31刻开时，就进行磷离子的注入，以增加沟道中载流子浓度，形成载流子增强区41，从而降低导通压降。
上述制备过程中共采用6张光刻版，分别是终端保护环光刻版、有源区光刻版、多晶硅光刻版、P阱光刻版、接触孔光刻版以及金属光刻版。载流子增强区41的离子注入与P型体区的离子注入采用同一块光刻版（P阱光刻版），能够节省成本。
同时上述绝缘栅双极型晶体管的制备方法与DMOS工艺兼容，具有普适性和不同IC生产线可移植性好等优点。
在其中一个实施例中，步骤S190采用接触孔光刻版进行光刻和接触孔刻蚀之后，溅射金属之前，还可以再进行一次PSD注入，向P型重掺杂区内注入P型离子，以获得良好的欧姆接触，提高器件的性能。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

1.一种绝缘栅双极型晶体管，包括***的终端结构和被所述终端结构包围的有源区，所述绝缘栅双极型晶体管的衬底为N型衬底，所述N型衬底背面设有P型区，所述P型区背面设有背面金属结构，终端结构内设有终端保护环，有源区的所述衬底正面设有多晶硅栅，衬底上所述多晶硅栅的两侧设有侧墙，所述衬底上设有覆盖所述多晶硅栅和侧墙的层间介质，所述层间介质上覆盖有金属引线层，其特征在于，
有源区的所述衬底内设有N型的载流子增强区，所述载流子增强区内设有P型体区，所述P型体区内设有N型重掺杂区，所述N型重掺杂区内设有P型重掺杂区，所述P型重掺杂区表面形成有向内凹陷的凹坑区域，所述凹坑区域形成于所述P型重掺杂区的区域内、从而使得凹坑区域位置处的P型重掺杂区表面低于凹坑区域两侧的P型重掺杂区表面，所述凹坑区域相对于两侧的衬底向内凹陷的深度为0.15微米～0.3微米。
2.根据权利要求1所述的绝缘栅双极型晶体管，其特征在于，所述衬底的材质为硅、碳化硅、砷化镓、磷化铟或锗硅中的一种。
3.根据权利要求2所述的绝缘栅双极型晶体管，其特征在于，所述衬底的材质为晶向<100>的单晶硅。
4.一种绝缘栅双极型晶体管的制备方法，包括：
提供衬底，在所述衬底的正面形成场氧层，用终端保护环光刻版光刻并刻蚀所述场氧层，并向被刻蚀开的区域下面的衬底内注入P型离子，形成终端保护环；
用有源区光刻版光刻并刻蚀掉有源区区域的所述场氧层，并在场氧层被刻蚀掉的所述衬底上淀积多晶硅，在淀积的多晶硅上形成保护层，再用多晶硅光刻版光刻并刻蚀掉多余的多晶硅和保护层，形成多晶硅栅；
用P阱光刻版光刻并刻蚀开所述多晶硅栅，并向被刻蚀开的多晶硅栅下面的衬底内注入N型离子，再推结后形成载流子增强区；
用所述P阱光刻版光刻并向载流子增强区内注入P型离子，推结后形成P型体区；
借助多晶硅栅向P型体区内进行自对准注入N型离子，推结后形成N型重掺杂区；
在多晶硅栅两侧形成侧墙，再向所述N型重掺杂区内注入P型离子，推结后形成P型重掺杂区；
去除所述保护层后向所述多晶硅栅进行多晶硅注入掺杂；
形成层间介质，进行绝缘栅双极型晶体管的正面金属化工艺，进行背面减薄、P型离子注入及退火工艺，及进行绝缘栅双极型晶体管的背面金属化工艺。
5.根据权利要求4所述的绝缘栅双极型晶体管的制备方法，其特征在于，所述在多晶硅栅两侧形成侧墙的步骤之后，向所述N型重掺杂区内注入P型离子的步骤之前，还包括对所述N型重掺杂区进行刻蚀形成凹坑区域的步骤，所述凹坑区域向内凹陷的深度相对于两侧的衬底为0.15微米～0.3微米。
6.根据权利要求4所述的绝缘栅双极型晶体管的制备方法，其特征在于，所述在淀积的多晶硅上形成保护层的步骤包括在所述多晶硅表面形成第一氧化层，在所述第一氧化层表面淀积氮化硅层。
7.根据权利要求4所述的绝缘栅双极型晶体管的制备方法，其特征在于，所述进行绝缘栅双极型晶体管的正面金属化工艺的工艺之后还包括再向所述P型重掺杂区内进行一次P型离子注入的步骤。
8.根据权利要求4所述的绝缘栅双极型晶体管的制备方法，其特征在于，所述向被刻蚀开的区域下面的衬底内注入P型离子，形成终端保护环的步骤中，所述P型离子为硼离子；所述向被刻蚀开的多晶硅栅下面的衬底内注入N型离子的步骤中，所述N型离子为磷离子；所述用P阱光刻版光刻并向载流子增强区内注入P型离子的步骤中，所述P型离子为硼离子；所述借助多晶硅栅向P型体区内进行自对准注入N型离子的步骤中，所述N型离子为砷离子；所述向N型重掺杂区内注入P型离子的步骤中，所述P型离子为硼离子；所述去除保护层后向所述多晶硅栅进行多晶硅注入掺杂的步骤中，注入的离子为磷离子。
9.根据权利要求4所述的绝缘栅双极型晶体管的制备方法，其特征在于，所述在多晶硅栅两侧形成侧墙的步骤包括：淀积第二氧化层、然后通过腐蚀去除多余的所述第二氧化层，剩余的第二氧化层形成所述侧墙。
10.根据权利要求4所述的绝缘栅双极型晶体管的制备方法，其特征在于，所述进行绝缘栅双极型晶体管的正面金属化工艺的步骤包括用接触孔光刻版光刻并刻蚀出接触孔，并在所述层间介质上溅射导电金属，之后采用金属光刻版光刻并刻蚀溅射的金属形成覆盖所述层间介质的金属引线层。
CN201310379443.1A 2013-08-27 2013-08-27 绝缘栅双极型晶体管及其制备方法 Active CN104425246B (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN201310379443.1A CN104425246B (zh) 2013-08-27 2013-08-27 绝缘栅双极型晶体管及其制备方法
US14/902,284 US9881994B2 (en) 2013-08-27 2014-08-25 Insulated gate bipolar transistor and manufacturing method therefor
PCT/CN2014/085082 WO2015027878A1 (zh) 2013-08-27 2014-08-25 绝缘栅双极型晶体管及其制备方法
EP14840868.5A EP3043387B1 (en) 2013-08-27 2014-08-25 Manufacturing method of an insulated gate bipolar transistor
US15/840,791 US10084036B2 (en) 2013-08-27 2017-12-13 Insulated gate bipolar transistor and manufacturing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310379443.1A CN104425246B (zh) 2013-08-27 2013-08-27 绝缘栅双极型晶体管及其制备方法

Publications (2)

Publication Number Publication Date
CN104425246A CN104425246A (zh) 2015-03-18
CN104425246B true CN104425246B (zh) 2018-01-23

Family

ID=52585575

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310379443.1A Active CN104425246B (zh) 2013-08-27 2013-08-27 绝缘栅双极型晶体管及其制备方法

Country Status (4)

Country Link
US (2) US9881994B2 (zh)
EP (1) EP3043387B1 (zh)
CN (1) CN104425246B (zh)
WO (1) WO2015027878A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112825301B (zh) * 2019-11-21 2022-08-12 东南大学 绝缘栅双极型晶体管器件及其制造方法
CN111081759B (zh) * 2019-12-10 2022-07-15 深圳第三代半导体研究院 一种增强型碳化硅mosfet器件及其制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0755077A2 (en) * 1995-07-21 1997-01-22 Plessey Semiconductors Limited High power MOS guided devices and methods of manufacturing them
CN1525575A (zh) * 2003-02-26 2004-09-01 �����Զ�����ʽ���� 高耐电压场效应型半导体设备
CN102496573A (zh) * 2011-12-28 2012-06-13 上海先进半导体制造股份有限公司 沟槽绝缘栅型双极晶体管的制作方法
CN102969243A (zh) * 2012-12-07 2013-03-13 株洲南车时代电气股份有限公司 一种平面栅型igbt芯片制作方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4567641A (en) 1982-04-12 1986-02-04 General Electric Company Method of fabricating semiconductor devices having a diffused region of reduced length
JPH0817233B2 (ja) * 1987-11-11 1996-02-21 三菱電機株式会社 絶縁ゲート型バイポーラトランジスタ
US4853345A (en) * 1988-08-22 1989-08-01 Delco Electronics Corporation Process for manufacture of a vertical DMOS transistor
JP2787921B2 (ja) * 1989-01-06 1998-08-20 三菱電機株式会社 絶縁ゲート型バイポーラトランジスタ
US5155052A (en) * 1991-06-14 1992-10-13 Davies Robert B Vertical field effect transistor with improved control of low resistivity region geometry
DE4121375A1 (de) * 1991-06-28 1993-01-14 Asea Brown Boveri Abschaltbares leistungshalbleiter-bauelement sowie verfahren zu dessen herstellung
US5843796A (en) * 1995-09-11 1998-12-01 Delco Electronics Corporation Method of making an insulated gate bipolar transistor with high-energy P+ im
US6110763A (en) * 1997-05-22 2000-08-29 Intersil Corporation One mask, power semiconductor device fabrication process
US6429481B1 (en) * 1997-11-14 2002-08-06 Fairchild Semiconductor Corporation Field effect transistor and method of its manufacture
US6570242B1 (en) * 1997-11-20 2003-05-27 Texas Instruments Incorporated Bipolar transistor with high breakdown voltage collector
US6403432B1 (en) * 2000-08-15 2002-06-11 Taiwan Semiconductor Manufacturing Company Hardmask for a salicide gate process with trench isolation
US6831329B2 (en) * 2001-10-26 2004-12-14 Fairchild Semiconductor Corporation Quick punch through IGBT having gate-controllable DI/DT and reduced EMI during inductive turn off
US6979861B2 (en) * 2002-05-30 2005-12-27 Apd Semiconductor, Inc. Power device having reduced reverse bias leakage current
US7169634B2 (en) * 2003-01-15 2007-01-30 Advanced Power Technology, Inc. Design and fabrication of rugged FRED
JP2006041023A (ja) 2004-07-23 2006-02-09 Toshiba Corp 半導体装置およびその製造方法
JP5122762B2 (ja) * 2006-03-07 2013-01-16 株式会社東芝 電力用半導体素子、その製造方法及びその駆動方法
US20080157117A1 (en) * 2006-12-28 2008-07-03 Mcnutt Ty R Insulated gate bipolar transistor with enhanced conductivity modulation
EP2086012A1 (en) * 2007-12-19 2009-08-05 ABB Technology AG Reverse-conducting insulated gate bipolar transistor and method for manufacturing such a reverse-conducting insulated gate bipolar transistor
CN101976683B (zh) 2010-09-25 2011-12-21 浙江大学 一种绝缘栅双极型晶体管及其制造方法
JP5848142B2 (ja) * 2012-01-25 2016-01-27 ルネサスエレクトロニクス株式会社 縦型プレーナパワーｍｏｓｆｅｔの製造方法
CN103035519B (zh) 2012-07-27 2015-10-14 上海华虹宏力半导体制造有限公司 Igbt器件及其制作工艺方法
CN102969351B (zh) 2012-12-07 2015-07-08 株洲南车时代电气股份有限公司 一种平面栅型igbt芯片
CN104425245B (zh) * 2013-08-23 2017-11-07 无锡华润上华科技有限公司 反向导通绝缘栅双极型晶体管制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0755077A2 (en) * 1995-07-21 1997-01-22 Plessey Semiconductors Limited High power MOS guided devices and methods of manufacturing them
CN1525575A (zh) * 2003-02-26 2004-09-01 �����Զ�����ʽ���� 高耐电压场效应型半导体设备
CN102496573A (zh) * 2011-12-28 2012-06-13 上海先进半导体制造股份有限公司 沟槽绝缘栅型双极晶体管的制作方法
CN102969243A (zh) * 2012-12-07 2013-03-13 株洲南车时代电气股份有限公司 一种平面栅型igbt芯片制作方法

Also Published As

Publication number Publication date
EP3043387A4 (en) 2017-01-25
CN104425246A (zh) 2015-03-18
EP3043387B1 (en) 2022-05-04
US20160307995A1 (en) 2016-10-20
US9881994B2 (en) 2018-01-30
EP3043387A1 (en) 2016-07-13
WO2015027878A1 (zh) 2015-03-05
US20180102406A1 (en) 2018-04-12
US10084036B2 (en) 2018-09-25

Similar Documents

Publication Publication Date Title
US8373224B2 (en) Super-junction trench MOSFET with resurf stepped oxides and trenched contacts
US8697518B2 (en) Trench MOSFET with trench contact holes and method for fabricating the same
CN102623318B (zh) 半导体器件及其制造方法
CN106876485A (zh) 一种集成肖特基二极管的SiC双沟槽型MOSFET器件及其制备方法
US8557678B2 (en) Method for manufacturing semiconductor substrate of large-power device
US8492221B2 (en) Method for fabricating power semiconductor device with super junction structure
CN104425247B (zh) 一种绝缘栅双极型晶体管的制备方法
CN104425246B (zh) 绝缘栅双极型晶体管及其制备方法
CN103730493A (zh) 一种半导体功率器件的结构
CN103137473B (zh) 以具有外延层的衬底制造场终止型igbt器件的方法
CN108010964A (zh) 一种igbt器件及制造方法
CN105322027B (zh) 肖特基二极管及其制造方法
CN101807597B (zh) 一种自对准亚微米栅结构及其制作方法
CN102931081B (zh) 带场阻挡层的半导体器件的制造方法
CN105280493A (zh) 一种沟槽igbt器件的制造方法
US11631742B2 (en) Semiconductor structure and method for forming same
CN105679668A (zh) 一种沟槽igbt器件的制造方法
CN207781610U (zh) 功率半导体器件
CN105551944A (zh) 功率晶体管的制造方法
CN106206323B (zh) 碳化硅金属氧化物半导体场效应管及其制作方法
CN211295111U (zh) 超低导通电阻分离栅mosfet器件
CN102903743B (zh) 采用金属硅化物的功率半导体器件结构及制备方法
RU2368036C1 (ru) Безэпитаксиальная структура биполярного транзистора
CN104299989B (zh) 绝缘栅双极型晶体管及其制造方法
TW478163B (en) Power MOSFET device for reducing reverse current leakage transient and improving avalanche breakdown current and the manufacturing method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20171027

Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8

Applicant after: Wuxi Huarun Shanghua Technology Co., Ltd.

Address before: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8

Applicant before: Wuxi CSMC Semiconductor Co., Ltd.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant