DE69935100D1 - Verfahren zur Ätzung einer Metallisierung mittels einer harten Maske - Google Patents

Verfahren zur Ätzung einer Metallisierung mittels einer harten Maske

Info

Publication number
DE69935100D1
DE69935100D1 DE69935100T DE69935100T DE69935100D1 DE 69935100 D1 DE69935100 D1 DE 69935100D1 DE 69935100 T DE69935100 T DE 69935100T DE 69935100 T DE69935100 T DE 69935100T DE 69935100 D1 DE69935100 D1 DE 69935100D1
Authority
DE
Germany
Prior art keywords
metallization
etching
hard mask
mask
hard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69935100T
Other languages
English (en)
Other versions
DE69935100T2 (de
Inventor
Martin Gutsche
Peter Strobl
Mp Fe Pi Wege
Eike Lueken
Georg Stojakovic
Bruno Spuler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE69935100D1 publication Critical patent/DE69935100D1/de
Application granted granted Critical
Publication of DE69935100T2 publication Critical patent/DE69935100T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/18—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69935100T 1998-09-15 1999-08-12 Verfahren zur Ätzung einer Metallisierung mittels einer harten Maske Expired - Lifetime DE69935100T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US153390 1998-09-15
US09/153,390 US6177353B1 (en) 1998-09-15 1998-09-15 Metallization etching techniques for reducing post-etch corrosion of metal lines

Publications (2)

Publication Number Publication Date
DE69935100D1 true DE69935100D1 (de) 2007-03-29
DE69935100T2 DE69935100T2 (de) 2007-12-13

Family

ID=22547020

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69935100T Expired - Lifetime DE69935100T2 (de) 1998-09-15 1999-08-12 Verfahren zur Ätzung einer Metallisierung mittels einer harten Maske

Country Status (7)

Country Link
US (1) US6177353B1 (de)
EP (1) EP0987745B1 (de)
JP (1) JP4690512B2 (de)
KR (1) KR100676995B1 (de)
CN (1) CN1146967C (de)
DE (1) DE69935100T2 (de)
TW (1) TW457583B (de)

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US9683305B2 (en) * 2011-12-20 2017-06-20 Apple Inc. Metal surface and process for treating a metal surface
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CN102723273B (zh) * 2012-05-28 2015-03-11 上海华力微电子有限公司 一种扩大铝线干法刻蚀腐蚀缺陷工艺窗口的方法
CN102820261A (zh) * 2012-08-22 2012-12-12 上海宏力半导体制造有限公司 铝刻蚀的方法
JP2015056578A (ja) * 2013-09-13 2015-03-23 株式会社東芝 半導体装置の製造方法
US9633867B2 (en) 2015-01-05 2017-04-25 Lam Research Corporation Method and apparatus for anisotropic tungsten etching
US9576811B2 (en) 2015-01-12 2017-02-21 Lam Research Corporation Integrating atomic scale processes: ALD (atomic layer deposition) and ALE (atomic layer etch)
CN104658905B (zh) * 2015-02-27 2018-01-05 深圳市华星光电技术有限公司 一种刻蚀方法及基板
US9806252B2 (en) 2015-04-20 2017-10-31 Lam Research Corporation Dry plasma etch method to pattern MRAM stack
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US9984858B2 (en) 2015-09-04 2018-05-29 Lam Research Corporation ALE smoothness: in and outside semiconductor industry
US10727073B2 (en) 2016-02-04 2020-07-28 Lam Research Corporation Atomic layer etching 3D structures: Si and SiGe and Ge smoothness on horizontal and vertical surfaces
US10229837B2 (en) 2016-02-04 2019-03-12 Lam Research Corporation Control of directionality in atomic layer etching
US9991128B2 (en) 2016-02-05 2018-06-05 Lam Research Corporation Atomic layer etching in continuous plasma
US10269566B2 (en) 2016-04-29 2019-04-23 Lam Research Corporation Etching substrates using ale and selective deposition
US9837312B1 (en) 2016-07-22 2017-12-05 Lam Research Corporation Atomic layer etching for enhanced bottom-up feature fill
US10566212B2 (en) 2016-12-19 2020-02-18 Lam Research Corporation Designer atomic layer etching
US10559461B2 (en) 2017-04-19 2020-02-11 Lam Research Corporation Selective deposition with atomic layer etch reset
US9997371B1 (en) 2017-04-24 2018-06-12 Lam Research Corporation Atomic layer etch methods and hardware for patterning applications
US10832909B2 (en) 2017-04-24 2020-11-10 Lam Research Corporation Atomic layer etch, reactive precursors and energetic sources for patterning applications
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Also Published As

Publication number Publication date
KR100676995B1 (ko) 2007-01-31
TW457583B (en) 2001-10-01
US6177353B1 (en) 2001-01-23
CN1146967C (zh) 2004-04-21
JP2000323483A (ja) 2000-11-24
CN1270415A (zh) 2000-10-18
EP0987745B1 (de) 2007-02-14
KR20000023166A (ko) 2000-04-25
EP0987745A1 (de) 2000-03-22
JP4690512B2 (ja) 2011-06-01
DE69935100T2 (de) 2007-12-13

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

8381 Inventor (new situation)

Inventor name: GUTSCHE, MARTIN, 84405 DORFEN, DE

Inventor name: STROBL, PETER, GLEN ALLEN, VA 23060, US

Inventor name: WEGE, STEPHAN, 01328 DRESDEN, DE

Inventor name: LUEKEN, EIKE, 01445 RADOBOUL, DE

Inventor name: STOJAKOVIC, GEORG, POUGHKEEPSIE, NY 12601, US

Inventor name: SPULER, BRUNO, 01478 WEIXDORF DRESDEN, DE

8364 No opposition during term of opposition