DE69531121D1 - Integrierte Halbleiteranordnung - Google Patents

Integrierte Halbleiteranordnung

Info

Publication number
DE69531121D1
DE69531121D1 DE69531121T DE69531121T DE69531121D1 DE 69531121 D1 DE69531121 D1 DE 69531121D1 DE 69531121 T DE69531121 T DE 69531121T DE 69531121 T DE69531121 T DE 69531121T DE 69531121 D1 DE69531121 D1 DE 69531121D1
Authority
DE
Germany
Prior art keywords
semiconductor device
integrated semiconductor
integrated
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69531121T
Other languages
English (en)
Other versions
DE69531121T2 (de
Inventor
Kazuhiko Yoshida
Tatsuhiko Fujihira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Publication of DE69531121D1 publication Critical patent/DE69531121D1/de
Application granted granted Critical
Publication of DE69531121T2 publication Critical patent/DE69531121T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2884Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/14Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7808Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE1995631121 1994-02-17 1995-02-14 Integrierte Halbleiteranordnung Expired - Lifetime DE69531121T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2005994 1994-02-17
JP2005994 1994-02-17
JP11324994 1994-05-27
JP11324994A JP3226074B2 (ja) 1994-02-17 1994-05-27 半導体集積回路装置

Publications (2)

Publication Number Publication Date
DE69531121D1 true DE69531121D1 (de) 2003-07-31
DE69531121T2 DE69531121T2 (de) 2004-05-06

Family

ID=26356952

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1995631121 Expired - Lifetime DE69531121T2 (de) 1994-02-17 1995-02-14 Integrierte Halbleiteranordnung

Country Status (4)

Country Link
US (1) US5828081A (de)
EP (4) EP1293788A3 (de)
JP (1) JP3226074B2 (de)
DE (1) DE69531121T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114664704A (zh) * 2022-03-18 2022-06-24 东莞市中麒光电技术有限公司 Led芯片筛选方法及显示屏

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3746604B2 (ja) 1997-12-09 2006-02-15 株式会社ルネサステクノロジ 半導体装置およびその製造方法
DE69723225D1 (de) 1997-04-01 2003-08-07 St Microelectronics Srl Anordnung zum Prüfen eines Gateoxids
US6153892A (en) * 1998-02-12 2000-11-28 Nec Corporation Semiconductor device and method for manufacture thereof
CN100337119C (zh) * 2003-03-10 2007-09-12 盛群半导体股份有限公司 集成电路的检测方法
JP4967476B2 (ja) * 2005-07-04 2012-07-04 株式会社デンソー 半導体装置の検査方法
US7573687B2 (en) * 2006-11-21 2009-08-11 Denso Corporation Power semiconductor device
JP5196222B2 (ja) * 2007-05-28 2013-05-15 富士電機株式会社 ゲート耐圧試験装置及び方法
JP5382544B2 (ja) * 2010-08-17 2014-01-08 富士電機株式会社 半導体集積回路および半導体集積回路に対するゲートスクリーニング試験の方法
CN107065997B (zh) * 2017-02-09 2018-10-26 张帅 修调功率器件输入电阻的控制方法
JP6830385B2 (ja) 2017-03-24 2021-02-17 エイブリック株式会社 半導体回路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2905271A1 (de) 1979-02-12 1980-08-21 Philips Patentverwaltung Integrierte schaltungsanordnung in mos-technik mit feldeffekttransistoren
US5008725C2 (en) * 1979-05-14 2001-05-01 Internat Rectifer Corp Plural polygon source pattern for mosfet
US5130767C1 (en) * 1979-05-14 2001-08-14 Int Rectifier Corp Plural polygon source pattern for mosfet
US4974059A (en) * 1982-12-21 1990-11-27 International Rectifier Corporation Semiconductor high-power mosfet device
JP2922733B2 (ja) * 1992-10-14 1999-07-26 三菱電機株式会社 混成集積回路装置
JPH06151737A (ja) * 1992-10-30 1994-05-31 Toshiba Corp 半導体装置及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114664704A (zh) * 2022-03-18 2022-06-24 东莞市中麒光电技术有限公司 Led芯片筛选方法及显示屏

Also Published As

Publication number Publication date
EP0669537A1 (de) 1995-08-30
US5828081A (en) 1998-10-27
EP0669537B1 (de) 2003-06-25
DE69531121T2 (de) 2004-05-06
EP1293788A2 (de) 2003-03-19
EP1293788A3 (de) 2004-06-23
EP1677121A1 (de) 2006-07-05
JPH07283370A (ja) 1995-10-27
JP3226074B2 (ja) 2001-11-05
EP1677122A1 (de) 2006-07-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJI ELECTRIC SYSTEMS CO., LTD., TOKYO/TOKIO, JP

8320 Willingness to grant licences declared (paragraph 23)