JPH01160029A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH01160029A
JPH01160029A JP62319444A JP31944487A JPH01160029A JP H01160029 A JPH01160029 A JP H01160029A JP 62319444 A JP62319444 A JP 62319444A JP 31944487 A JP31944487 A JP 31944487A JP H01160029 A JPH01160029 A JP H01160029A
Authority
JP
Japan
Prior art keywords
lsi chip
wiring
electrode
insulating resin
projecting electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62319444A
Other languages
English (en)
Inventor
Hiroaki Fujimoto
博昭 藤本
Kenzo Hatada
畑田　賢造
Takao Ochi
岳雄 越智
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62319444A priority Critical patent/JPH01160029A/ja
Priority to EP88311869A priority patent/EP0321239A3/en
Priority to KR1019880016786A priority patent/KR920002075B1/ko
Publication of JPH01160029A publication Critical patent/JPH01160029A/ja
Pending legal-status Critical Current

Links

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置に関し、特にマイクロコンピュータ
や、ゲートアレイ等の多電極、狭ピッチ＋７）ＬＳ　Ｉ
チップの実装に関するものである。
従来の技術 ２　へ−７ 従来の技術を第２図とともに説明する。
まず第２図（ａ）に示す様に、セラミック、ガラス゛　
　等よシなる配線基板１４の導体配線１５を有する面に
、絶縁性樹脂１３を塗布する。導体配線１５は、０ｒ−
Ａｕ、ム］、ＩＴＯ等であり、絶縁性樹脂１３は熱硬化
あるいは紫外線硬化のエポキシ、アクリル等である。次
に、第２図（ｂ）に示す様にム田等よシなる突起電極１
２を有したＬＳＩチップ１１を、電極１２と導体配線１
５が一致する様に配線基板１４の絶縁性樹脂１３が塗布
された領域に設置し加圧ツール１６にてＬＳＩチップ１
１を加圧する。この時、ＬＳＩチップ１１の突起電極１
２は塑性変形し、絶縁性樹脂１３は周囲に押し出され、
ＬＳＩチップ１１の突起電極１２と導体配線１５は電気
的に接触する。次に加圧ツール１６をＬＳＩチップ１１
に加圧した状態で、絶縁性樹脂１３を硬化し、第２図（
Ｃ）に示す様に、加圧ツール１６を解除する。この時、
ＬＳＩＩチップ１１は配線基板１４に絶縁性樹脂によシ
固着されるとともに、ＬＳＩチップ１１の塑性変形され
た突起電極３　・＼−７ １２と導体配線１５は接触によシミ見向に接続される。
発明が解決しようとする問題点 前述した従来の技術では、ＬＳＩチップの突起電極を塑
性変形させている為、ＬＳＩチップを固着している絶縁
性樹脂が熱膨張した際に、突起電極と導体配線間に、す
きまが生じ、電気的な接続不良が生じ、耐熱性の低いも
のである。
問題点を解決するための手段 本発明は前記問題点を解決する為に、ＬＳＩチップを配
線基板に加圧する際に、ＬＳＩチップの突起電極を弾性
変形にとどめておき、ＬＳＩチップの突起電極と導体配
線を接続するものである。
作用 ＬＳＩチップの突起電極の弾性変形である為、仮に、絶
縁性樹脂が膨張し、絶縁性樹脂の寸法変化も生じても突
起電極の弾性回復にょシ、導体配線と突起電極は常に接
触した状態を保持するものである。
実施例 本発明の一実施例を、第１図と共に説明する。
まず第１図（＆）に示す様に、ガラス、セラミック等よ
りなり、導体配線５を有した、配線基板４の導体配線６
を含む領域に絶縁性樹脂３を塗布する。
配線基板４の厚みは、０．１〜２．Ｏｆｆπ程度１であ
り、導体配線５は、Ｃｒ−Ａｕ、Ａ５．ＩＴＯ等であシ
その厚みは０．１〜１０μｍ程度である。絶縁性樹脂３
はアクリル、エポキシ等の光硬化型であり、塗布はデイ
スペンサー、印刷等を用いる。次に第１図（ｂ）に示す
様に、Ａｕ、Ｃｕ、Ａ７．Ｉｎ、Ｉｎ合金等よシなる突
起電極２を有した、ＬＳＩチップ１を、突起電極２と導
体配線５が一致する様に配線基板４の絶縁性樹脂３が塗
布された領域に設置する。突起電極２の厚みは５〜３ｏ
μ程度であシその寸法は、３μ０〜６０μ０程度である
。次に突起電極２が弾性変形状態でとどまる様に、加圧
ツール６にてＬＳＩチップ１を加圧する。加圧力は、０
．５９　／電極〜１４／電極程度である。この時、絶縁
性樹脂３は周囲に押し出され、ＬＳＩチップ１の突起電
極２と導体配線６は電気的に接触する。
５ｉ＼−／ 次に、ＬＳＩチップ１を加圧した状態で、絶縁性樹脂３
を硬化する。硬化の方法は、配線基板４がガラス等の透
明基板の場合は、配線基板４裏面より紫外線を照射する
。また、セラミック等の不透明基板の場合は、ＬＳＩチ
ップ１の側面より紫外線を照射する。次に、第１図（ｃ
）　Ｋ示す様に、加圧ツール６を解除する。この時、Ｌ
ＳＩチップ１は配線基板４に固着されると同時に、突起
電極４と導体配線５は接触によシミ見向に接続される。
発明の効果 本発明では、ＬＳＩチップの突起電極を弾性変形の状態
で、配線基板の導体配線に接触させており、絶縁性樹脂
に熱膨張による寸法変化が生じ、ＬＳＩチップと配線基
板間の寸法変化が生じても、突起電極は弾性回復するた
め、常に突起電極と導体配線は接触した状態が保持され
、耐熱性が高く信頼性の高いものである。よって、パー
クデバイス等への適用が可能となるものである。
【図面の簡単な説明】
第１図は本発明の一実施例方法の工程断面図、６　・＼
−１ 第２図は従来の方法の工程断面図である。 １・・・・・・ＬＳＩチップ、２・・・・・・突起電極
、３・・・−・絶縁性樹脂、４・・・・・配線基板、５
・・・・−・導体配線、６・・・・−・加圧ツール。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名ｆ−
Ｌ５ｘす１，７゜ ２−−−突起を詠 ５−゛−杵俸配秩 ＩＩ−−−１ｙエナツ７゜

Claims (2)

    【特許請求の範囲】
  1. （１）導体配線を有する絶縁性基板の前記導体配線と半
    導体素子の電極が一致する様に、前記半導体素子が、前
    記絶縁性基板に、前記半導体素子と前記絶縁性基板間に
    形成された絶縁性樹脂により、前記半導体素子の電極が
    弾性変形した状態で固着され、かつ前記半導体素子の電
    極と前記導体配線が接触により電気的に接続されてなる
    半導体装置。
  2. （２）半導体素子の電極が突起電極である特許請求の範
    囲第１項記載の半導体装置。
JP62319444A 1987-12-17 1987-12-17 半導体装置 Pending JPH01160029A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP62319444A JPH01160029A (ja) 1987-12-17 1987-12-17 半導体装置
EP88311869A EP0321239A3 (en) 1987-12-17 1988-12-15 Fabricating method of semiconductor device
KR1019880016786A KR920002075B1 (ko) 1987-12-17 1988-12-16 반도체장치의 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62319444A JPH01160029A (ja) 1987-12-17 1987-12-17 半導体装置

Publications (1)

Publication Number Publication Date
JPH01160029A true JPH01160029A (ja) 1989-06-22

Family

ID=18110268

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62319444A Pending JPH01160029A (ja) 1987-12-17 1987-12-17 半導体装置

Country Status (3)

Country Link
EP (1) EP0321239A3 (ja)
JP (1) JPH01160029A (ja)
KR (1) KR920002075B1 (ja)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0449496B1 (en) * 1990-03-20 1994-07-20 Sharp Kabushiki Kaisha Method for mounting a semiconductor device
EP0644587B1 (en) * 1993-09-01 2002-07-24 Kabushiki Kaisha Toshiba Semiconductor package and fabrication method
US5886877A (en) 1995-10-13 1999-03-23 Meiko Electronics Co., Ltd. Circuit board, manufacturing method therefor, and bump-type contact head and semiconductor component packaging module using the circuit board
US6326241B1 (en) * 1997-12-29 2001-12-04 Visteon Global Technologies, Inc. Solderless flip-chip assembly and method and material for same
DE102004030813B4 (de) * 2004-06-25 2007-03-29 Infineon Technologies Ag Verfahren zur Verbindung einer integrierten Schaltung mit einem Substrat und entsprechende Schaltungsanordnung

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS601849A (ja) * 1983-06-17 1985-01-08 Sharp Corp 電子部品の接続方法
JPS60262430A (ja) * 1984-06-08 1985-12-25 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH0752741B2 (ja) * 1986-05-29 1995-06-05 松下電器産業株式会社 半導体装置

Also Published As

Publication number Publication date
EP0321239A3 (en) 1990-04-25
EP0321239A2 (en) 1989-06-21
KR890011079A (ko) 1989-08-12
KR920002075B1 (ko) 1992-03-10

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