DE69028903D1 - Ausgangsdatenpufferschaltung für integrierte Halbleiterschaltung - Google Patents

Ausgangsdatenpufferschaltung für integrierte Halbleiterschaltung

Info

Publication number
DE69028903D1
DE69028903D1 DE69028903T DE69028903T DE69028903D1 DE 69028903 D1 DE69028903 D1 DE 69028903D1 DE 69028903 T DE69028903 T DE 69028903T DE 69028903 T DE69028903 T DE 69028903T DE 69028903 D1 DE69028903 D1 DE 69028903D1
Authority
DE
Germany
Prior art keywords
output data
semiconductor integrated
data buffer
circuit
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69028903T
Other languages
English (en)
Inventor
Junji Yano
Tsukasa Miyawaki
Masami Atoh
Masakazu Gotou
Masakazu Iwashita
Michio Kaji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69028903D1 publication Critical patent/DE69028903D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE69028903T 1989-12-14 1990-12-14 Ausgangsdatenpufferschaltung für integrierte Halbleiterschaltung Expired - Lifetime DE69028903D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1324754A JPH03185921A (ja) 1989-12-14 1989-12-14 半導体集積回路

Publications (1)

Publication Number Publication Date
DE69028903D1 true DE69028903D1 (de) 1996-11-21

Family

ID=18169307

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69028903T Expired - Lifetime DE69028903D1 (de) 1989-12-14 1990-12-14 Ausgangsdatenpufferschaltung für integrierte Halbleiterschaltung

Country Status (5)

Country Link
US (1) US5194764A (de)
EP (2) EP0686975A1 (de)
JP (1) JPH03185921A (de)
KR (1) KR950001087B1 (de)
DE (1) DE69028903D1 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5334889A (en) * 1990-06-20 1994-08-02 Oki Electric Industry, Co., Ltd. CMOS output buffer circuit with less noise
US5491432A (en) * 1992-08-07 1996-02-13 Lsi Logic Corporation CMOS Differential driver circuit for high offset ground
ATE135510T1 (de) * 1992-09-18 1996-03-15 Siemens Ag Integrierte pufferschaltung
DE59207548D1 (de) * 1992-09-18 1997-01-02 Siemens Ag Integrierte Pufferschaltung
US5604453A (en) * 1993-04-23 1997-02-18 Altera Corporation Circuit for reducing ground bounce
JPH07129538A (ja) * 1993-10-29 1995-05-19 Mitsubishi Denki Semiconductor Software Kk 半導体集積回路
DE4447546C2 (de) * 1993-10-29 1996-06-27 Mitsubishi Electric Corp Integrierte Halbleiterschaltung
US5721875A (en) * 1993-11-12 1998-02-24 Intel Corporation I/O transceiver having a pulsed latch receiver circuit
JPH07182864A (ja) * 1993-12-21 1995-07-21 Mitsubishi Electric Corp 半導体記憶装置
JP2671787B2 (ja) * 1993-12-24 1997-10-29 日本電気株式会社 出力バッファ回路
DE4422784C2 (de) * 1994-06-29 1999-05-27 Texas Instruments Deutschland Schaltungsanordnung mit wenigstens einer Schaltungseinheit wie einem Register, einer Speicherzelle, einer Speicheranordnung oder dergleichen
KR970005570B1 (ko) * 1994-07-14 1997-04-17 현대전자산업 주식회사 데이타 출력버퍼
KR0129592B1 (ko) * 1994-09-09 1998-10-01 김주용 저잡음 출력 버퍼
US5434519A (en) * 1994-10-11 1995-07-18 International Business Machines Corporation Self-resetting CMOS off-chip driver
US5596284A (en) * 1994-11-10 1997-01-21 Brooktree Corporation System for, and method of, minimizing noise in an integrated circuit chip
JPH08228141A (ja) * 1995-02-21 1996-09-03 Kawasaki Steel Corp 出力バッファ回路
US5539336A (en) * 1995-05-01 1996-07-23 Lsi Logic Corporation High speed driver circuit with improved off transition feedback
US5825206A (en) * 1996-08-14 1998-10-20 Intel Corporation Five volt safe output buffer circuit that controls the substrate and gates of the pull-up devices
US6097220A (en) * 1997-06-11 2000-08-01 Intel Corporation Method and circuit for recycling charge
KR100475046B1 (ko) * 1998-07-20 2005-05-27 삼성전자주식회사 출력버퍼 및 그의 버퍼링 방법
US6459313B1 (en) 1998-09-18 2002-10-01 Lsi Logic Corporation IO power management: synchronously regulated output skew
US20030189448A1 (en) * 2002-04-08 2003-10-09 Silicon Video, Inc. MOSFET inverter with controlled slopes and a method of making
US6724224B1 (en) * 2003-04-07 2004-04-20 Pericom Semiconductor Corp. Bus relay and voltage shifter without direction control input
KR100842743B1 (ko) * 2006-10-27 2008-07-01 주식회사 하이닉스반도체 고집적 반도체 장치
JP5151413B2 (ja) * 2007-11-20 2013-02-27 富士通セミコンダクター株式会社 データ保持回路
CN105850043B (zh) 2013-12-27 2019-01-11 松下知识产权经营株式会社 半导体集成电路、锁存电路以及触发器
KR102290384B1 (ko) * 2015-02-16 2021-08-17 삼성전자주식회사 누설 전류 기반의 지연 회로
CN105162442B (zh) * 2015-10-08 2018-12-21 重庆中科芯亿达电子有限公司 一种功率管驱动集成电路

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA945641A (en) * 1970-04-27 1974-04-16 Tokyo Shibaura Electric Co. Logic circuit using complementary type insulated gate field effect transistors
JPS5787620A (en) * 1980-11-20 1982-06-01 Fujitsu Ltd Clock generating circuit
JPS57168319A (en) * 1981-04-09 1982-10-16 Fujitsu Ltd Parallel output buffer circuit
US4883986A (en) * 1981-05-19 1989-11-28 Tokyo Shibaura Denki Kabushiki Kaisha High density semiconductor circuit using CMOS transistors
US4556961A (en) * 1981-05-26 1985-12-03 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory with delay means to reduce peak currents
JPS5838032A (ja) * 1981-08-13 1983-03-05 Fujitsu Ltd Ｃ―ｍｏｓインバータ駆動用バッファ回路
JPS59148426A (ja) * 1983-02-15 1984-08-25 Nec Corp 同時動作タイミング制御回路
JPS60130920A (ja) * 1983-12-20 1985-07-12 Nec Corp 半導体集積論理回路
US4786824A (en) * 1984-05-24 1988-11-22 Kabushiki Kaisha Toshiba Input signal level detecting circuit
EP0194939B1 (de) * 1985-03-14 1992-02-05 Fujitsu Limited Halbleiterspeicheranordnung
JPS61214817A (ja) * 1985-03-20 1986-09-24 Toshiba Corp Ｃｍｏｓ集積回路
JPH07107978B2 (ja) * 1985-11-07 1995-11-15 ロ−ム株式会社 Ｃ−ｍｏｓ回路
JPH0799639B2 (ja) * 1987-07-31 1995-10-25 株式会社東芝 半導体集積回路
US4857765A (en) * 1987-11-17 1989-08-15 International Business Machines Corporation Noise control in an integrated circuit chip
US4992677A (en) * 1988-03-23 1991-02-12 Hitachi, Ltd. High speed MOSFET output buffer with low noise
US4924120A (en) * 1988-06-29 1990-05-08 Texas Instruments Incorporated Low noise output circuit
US4959563A (en) * 1988-06-29 1990-09-25 Texas Instruments Incorporated Adjustable low noise output circuit
KR910004735B1 (ko) * 1988-07-18 1991-07-10 삼성전자 주식회사 데이타 출력용 버퍼회로
JPH0289292A (ja) * 1988-09-26 1990-03-29 Toshiba Corp 半導体メモリ
US4975599A (en) * 1989-07-26 1990-12-04 International Business Machines Corporation Method and resulting devices for compensating for process variables in a CMOS device driver circuit

Also Published As

Publication number Publication date
KR910013535A (ko) 1991-08-08
JPH03185921A (ja) 1991-08-13
EP0432790A2 (de) 1991-06-19
KR950001087B1 (ko) 1995-02-08
EP0432790B1 (de) 1996-10-16
US5194764A (en) 1993-03-16
EP0432790A3 (en) 1992-09-30
EP0686975A1 (de) 1995-12-13

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Legal Events

Date Code Title Description
8332 No legal effect for de