JPS57168319A - Parallel output buffer circuit - Google Patents

Parallel output buffer circuit

Info

Publication number
JPS57168319A
JPS57168319A JP56053305A JP5330581A JPS57168319A JP S57168319 A JPS57168319 A JP S57168319A JP 56053305 A JP56053305 A JP 56053305A JP 5330581 A JP5330581 A JP 5330581A JP S57168319 A JPS57168319 A JP S57168319A
Authority
JP
Japan
Prior art keywords
signal line
groups
delay time
delay
discharge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56053305A
Other languages
Japanese (ja)
Inventor
Tetsuo Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56053305A priority Critical patent/JPS57168319A/en
Publication of JPS57168319A publication Critical patent/JPS57168319A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce a large transient current that flows to a bus signal line, by dividing plural signal lines into some groups comprising one or several pieces and making the time when the value of the signal line of each group varies different for each group of the signal lines. CONSTITUTION:A bus signal line 1 is divided into two groups A and B, and delay circuits DelA and DelB are provided at the front stage of a buffer Buf which delivers an output to each signal line. The delay time is set different between the groups A and B. The discharge currents IA and IB which flow toward the earth have different discharge times due to the capacitance of the signal line which varies by the output voltages VA and VB of the groups A and B respectively. As a result, the amplitude of the total discharge current IA+IB is reduced down to 1/2 that obtained in case the discharge current flows at the same time, and the pulse duration becomes double. Accordingly the fluctuation of potential caused to the earth by the current impulse is suppressed down to 1/2. The delay time difference of a delay circuit suffices a sufficiently small level since the pulse duration is small for the transient currents IA and IB, and this delay time difference gives no effect on the processing speed.
JP56053305A 1981-04-09 1981-04-09 Parallel output buffer circuit Pending JPS57168319A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56053305A JPS57168319A (en) 1981-04-09 1981-04-09 Parallel output buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56053305A JPS57168319A (en) 1981-04-09 1981-04-09 Parallel output buffer circuit

Publications (1)

Publication Number Publication Date
JPS57168319A true JPS57168319A (en) 1982-10-16

Family

ID=12939000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56053305A Pending JPS57168319A (en) 1981-04-09 1981-04-09 Parallel output buffer circuit

Country Status (1)

Country Link
JP (1) JPS57168319A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59229924A (en) * 1983-06-13 1984-12-24 Hitachi Ltd Logical circuit for integrated circuit
JPS60190020A (en) * 1984-03-12 1985-09-27 Hitachi Ltd Cmos integrated circuit device
JPS63168737A (en) * 1986-12-30 1988-07-12 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Dual circuit array body
JPH03185921A (en) * 1989-12-14 1991-08-13 Toshiba Corp Semiconductor integrated circuit
JP2012109940A (en) * 2010-10-28 2012-06-07 Sumitomo Electric Ind Ltd Drive circuit and optical transmission device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59229924A (en) * 1983-06-13 1984-12-24 Hitachi Ltd Logical circuit for integrated circuit
JPS60190020A (en) * 1984-03-12 1985-09-27 Hitachi Ltd Cmos integrated circuit device
JPS63168737A (en) * 1986-12-30 1988-07-12 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Dual circuit array body
JPH0451859B2 (en) * 1986-12-30 1992-08-20 Intaanashonaru Bijinesu Mashiinzu Corp
JPH03185921A (en) * 1989-12-14 1991-08-13 Toshiba Corp Semiconductor integrated circuit
JP2012109940A (en) * 2010-10-28 2012-06-07 Sumitomo Electric Ind Ltd Drive circuit and optical transmission device

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