DE3686721D1 - Verfahren zur herstellung einer kontaktoeffnung mit gewuenschter schraege in einer zusammengesetzten schicht, die mit photoresist maskiert ist. - Google Patents
Verfahren zur herstellung einer kontaktoeffnung mit gewuenschter schraege in einer zusammengesetzten schicht, die mit photoresist maskiert ist.Info
- Publication number
- DE3686721D1 DE3686721D1 DE8686430035T DE3686721T DE3686721D1 DE 3686721 D1 DE3686721 D1 DE 3686721D1 DE 8686430035 T DE8686430035 T DE 8686430035T DE 3686721 T DE3686721 T DE 3686721T DE 3686721 D1 DE3686721 D1 DE 3686721D1
- Authority
- DE
- Germany
- Prior art keywords
- slope
- layer
- oxidiser
- percentage
- dry
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 229920002120 photoresistant polymer Polymers 0.000 title 1
- 239000007800 oxidant agent Substances 0.000 abstract 3
- 239000002131 composite material Substances 0.000 abstract 2
- 239000000203 mixture Substances 0.000 abstract 2
- 238000001312 dry etching Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 150000002222 fluorine compounds Chemical class 0.000 abstract 1
- 239000008246 gaseous mixture Substances 0.000 abstract 1
- 239000005360 phosphosilicate glass Substances 0.000 abstract 1
- 238000001020 plasma etching Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP86430035A EP0263220B1 (de) | 1986-10-08 | 1986-10-08 | Verfahren zur Herstellung einer Kontaktöffnung mit gewünschter Schräge in einer zusammengesetzten Schicht, die mit Photoresist maskiert ist |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3686721D1 true DE3686721D1 (de) | 1992-10-15 |
Family
ID=8196403
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8686430035T Expired - Lifetime DE3686721D1 (de) | 1986-10-08 | 1986-10-08 | Verfahren zur herstellung einer kontaktoeffnung mit gewuenschter schraege in einer zusammengesetzten schicht, die mit photoresist maskiert ist. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4814041A (de) |
EP (1) | EP0263220B1 (de) |
JP (1) | JPH0626205B2 (de) |
DE (1) | DE3686721D1 (de) |
Families Citing this family (81)
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---|---|---|---|---|
JPH0691046B2 (ja) * | 1986-11-19 | 1994-11-14 | 日本電気株式会社 | 反応性イオンエツチング方法 |
US5234633A (en) * | 1987-12-28 | 1993-08-10 | Canon Kabushiki Kaisha | Cast molding die and process for producing information recording medium using the same |
JP2628339B2 (ja) * | 1988-05-13 | 1997-07-09 | 日本電信電話株式会社 | 半導体装置の製造方法 |
DE3915650A1 (de) * | 1989-05-12 | 1990-11-15 | Siemens Ag | Verfahren zur strukturierung einer auf einem halbleiterschichtaufbau angeordneten schicht |
EP0416809A3 (en) * | 1989-09-08 | 1991-08-07 | American Telephone And Telegraph Company | Reduced size etching method for integrated circuits |
JP2746289B2 (ja) * | 1989-09-09 | 1998-05-06 | 忠弘 大見 | 素子の作製方法並びに半導体素子およびその作製方法 |
US4978420A (en) * | 1990-01-03 | 1990-12-18 | Hewlett-Packard Company | Single chamber via etch through a dual-layer dielectric |
US5225376A (en) * | 1990-05-02 | 1993-07-06 | Nec Electronics, Inc. | Polysilicon taper process using spin-on glass |
US5068707A (en) * | 1990-05-02 | 1991-11-26 | Nec Electronics Inc. | DRAM memory cell with tapered capacitor electrodes |
EP0469370A3 (en) * | 1990-07-31 | 1992-09-09 | Gold Star Co. Ltd | Etching process for sloped side walls |
JP2794499B2 (ja) | 1991-03-26 | 1998-09-03 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US5203957A (en) * | 1991-06-12 | 1993-04-20 | Taiwan Semiconductor Manufacturing Company | Contact sidewall tapering with argon sputtering |
US5180689A (en) * | 1991-09-10 | 1993-01-19 | Taiwan Semiconductor Manufacturing Company | Tapered opening sidewall with multi-step etching process |
US5217567A (en) * | 1992-02-27 | 1993-06-08 | International Business Machines Corporation | Selective etching process for boron nitride films |
US5269880A (en) * | 1992-04-03 | 1993-12-14 | Northern Telecom Limited | Tapering sidewalls of via holes |
US5175127A (en) * | 1992-06-02 | 1992-12-29 | Micron Technology, Inc. | Self-aligned interlayer contact process using a plasma etch of photoresist |
US5549784A (en) * | 1992-09-04 | 1996-08-27 | Intel Corporation | Method for etching silicon oxide films in a reactive ion etch system to prevent gate oxide damage |
US5268332A (en) * | 1992-11-12 | 1993-12-07 | At&T Bell Laboratories | Method of integrated circuit fabrication having planarized dielectrics |
JP2787646B2 (ja) | 1992-11-27 | 1998-08-20 | 三菱電機株式会社 | 半導体装置の製造方法 |
US5308415A (en) * | 1992-12-31 | 1994-05-03 | Chartered Semiconductor Manufacturing Pte Ltd. | Enhancing step coverage by creating a tapered profile through three dimensional resist pull back |
KR0126801B1 (ko) * | 1993-12-22 | 1998-04-02 | 김광호 | 반도체 장치의 배선 형성방법 |
JP3529849B2 (ja) * | 1994-05-23 | 2004-05-24 | 富士通株式会社 | 半導体装置の製造方法 |
US5453403A (en) * | 1994-10-24 | 1995-09-26 | Chartered Semiconductor Manufacturing Pte, Ltd. | Method of beveled contact opening formation |
US6040247A (en) * | 1995-01-10 | 2000-03-21 | Lg Semicon Co., Ltd. | Method for etching contact |
KR0154702B1 (ko) * | 1995-06-09 | 1998-10-15 | 김광호 | 항복전압을 향상시킨 다이오드 제조 방법 |
US6396078B1 (en) | 1995-06-20 | 2002-05-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with a tapered hole formed using multiple layers with different etching rates |
JPH09153545A (ja) * | 1995-09-29 | 1997-06-10 | Toshiba Corp | 半導体装置及びその製造方法 |
US6294799B1 (en) * | 1995-11-27 | 2001-09-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating same |
US5940732A (en) * | 1995-11-27 | 1999-08-17 | Semiconductor Energy Laboratory Co., | Method of fabricating semiconductor device |
KR0179792B1 (ko) * | 1995-12-27 | 1999-04-15 | 문정환 | 고밀도 플라즈마 식각장비를 이용한 슬로프 콘택 홀 형성방법 |
KR0179791B1 (ko) * | 1995-12-27 | 1999-03-20 | 문정환 | 플래쉬 메모리 소자 및 그 제조방법 |
US5661083A (en) * | 1996-01-30 | 1997-08-26 | Integrated Device Technology, Inc. | Method for via formation with reduced contact resistance |
JPH09289250A (ja) * | 1996-04-24 | 1997-11-04 | Nec Corp | 半導体装置の製造方法 |
US5652172A (en) * | 1996-04-29 | 1997-07-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for controlling the etch profile of an aperture formed through a multi-layer insulator layer |
US5750441A (en) * | 1996-05-20 | 1998-05-12 | Micron Technology, Inc. | Mask having a tapered profile used during the formation of a semiconductor device |
KR19980064444A (ko) * | 1996-12-20 | 1998-10-07 | 윌리엄비.켐플러 | 다층 집적 회로 유전체 구조의 에칭 방법 |
US6084305A (en) * | 1997-10-06 | 2000-07-04 | Vlsi Technology, Inc. | Shaped etch-front for self-aligned contact |
US6143649A (en) * | 1998-02-05 | 2000-11-07 | Micron Technology, Inc. | Method for making semiconductor devices having gradual slope contacts |
TW421849B (en) * | 1998-02-23 | 2001-02-11 | Winbond Electronics Corp | Structure of multi-layered dielectric opening and its fabricating method |
US6074957A (en) | 1998-02-26 | 2000-06-13 | Micron Technology, Inc. | Methods of forming openings and methods of controlling the degree of taper of openings |
US6287751B2 (en) * | 1998-05-12 | 2001-09-11 | United Microelectronics Corp. | Method of fabricating contact window |
US6475836B1 (en) | 1999-03-29 | 2002-11-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US6326307B1 (en) * | 1999-11-15 | 2001-12-04 | Appllied Materials, Inc. | Plasma pretreatment of photoresist in an oxide etch process |
US7056624B2 (en) * | 2001-02-15 | 2006-06-06 | Dai Nippon Printing Co., Ltd. | Methods of manufacturing phase shift masks having etched substrate shifters with sidewalls rounded at top and bottom corners |
KR100425100B1 (ko) * | 2001-08-27 | 2004-03-30 | 엘지전자 주식회사 | 건식식각에 의한 그루브 제조방법 및 그를 이용한광통신용소자 |
KR20030050845A (ko) * | 2001-12-19 | 2003-06-25 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
ITMI20020931A1 (it) * | 2002-05-02 | 2003-11-03 | St Microelectronics Srl | Metodo per fabbricare circuiti elettronici integrati su un substrato semiconduttore |
US6858542B2 (en) * | 2003-01-17 | 2005-02-22 | Freescale Semiconductor, Inc. | Semiconductor fabrication method for making small features |
CN1525553A (zh) * | 2003-02-26 | 2004-09-01 | ���µ�����ҵ��ʽ���� | 半导体装置的制造方法 |
US7060624B2 (en) * | 2003-08-13 | 2006-06-13 | International Business Machines Corporation | Deep filled vias |
US7030008B2 (en) * | 2003-09-12 | 2006-04-18 | International Business Machines Corporation | Techniques for patterning features in semiconductor devices |
US7390740B2 (en) | 2004-09-02 | 2008-06-24 | Micron Technology, Inc. | Sloped vias in a substrate, spring-like contacts, and methods of making |
US20060086690A1 (en) * | 2004-10-21 | 2006-04-27 | Ming-Huan Tsai | Dielectric etching method to prevent photoresist damage and bird's beak |
DE102004052611A1 (de) * | 2004-10-29 | 2006-05-04 | Infineon Technologies Ag | Verfahren zur Herstellung einer mit einem Füllmaterial mindestens teilweise gefüllten Öffnung, Verfahren zur Herstellung einer Speicherzelle und Speicherzelle |
JP2007266030A (ja) * | 2006-03-27 | 2007-10-11 | Seiko Epson Corp | 半導体装置の製造方法および半導体装置 |
US8685861B2 (en) * | 2006-08-02 | 2014-04-01 | Globalfoundries Singapore Pte. Ltd. | Integrated circuit system with contact distribution film |
US20080070411A1 (en) * | 2006-09-20 | 2008-03-20 | John Ghekiere | Methods for uniformly etching films on a semiconductor wafer |
US7973413B2 (en) | 2007-08-24 | 2011-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate via for semiconductor device |
JP5326404B2 (ja) * | 2008-07-29 | 2013-10-30 | 富士通株式会社 | モールドの製造方法 |
US7998869B2 (en) * | 2008-10-31 | 2011-08-16 | Samsung Electronics Co., Ltd. | Contact patterning method with transition etch feedback |
JP5446388B2 (ja) * | 2009-03-31 | 2014-03-19 | サンケン電気株式会社 | 集積化半導体装置の製造方法 |
CN101937865B (zh) * | 2009-07-03 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | 沟槽的形成方法 |
US8610283B2 (en) * | 2009-10-05 | 2013-12-17 | International Business Machines Corporation | Semiconductor device having a copper plug |
US8703619B2 (en) * | 2012-01-19 | 2014-04-22 | Headway Technologies, Inc. | Taper-etching method and method of manufacturing near-field light generator |
CN102610496B (zh) * | 2012-03-31 | 2017-11-07 | 上海集成电路研发中心有限公司 | 大高宽比结构的去胶方法 |
JP2014013810A (ja) * | 2012-07-04 | 2014-01-23 | Seiko Epson Corp | 基板、基板の製造方法、半導体装置、及び電子機器 |
CN103779271B (zh) * | 2012-10-26 | 2017-04-05 | 中微半导体设备(上海)有限公司 | 一种倒锥形轮廓刻蚀方法 |
CN103811408B (zh) * | 2012-11-08 | 2016-08-17 | 中微半导体设备(上海)有限公司 | 一种深硅通孔刻蚀方法 |
US9159581B2 (en) | 2012-11-27 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a semiconductor device using a bottom antireflective coating (BARC) layer |
US9159580B2 (en) * | 2012-12-14 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a semiconductor device using multiple layer sets |
TWI513993B (zh) | 2013-03-26 | 2015-12-21 | Ind Tech Res Inst | 三軸磁場感測器、製作磁場感測結構的方法與磁場感測電路 |
EP2819162B1 (de) | 2013-06-24 | 2020-06-17 | IMEC vzw | Verfahren zur Herstellung von Kontaktbereichen auf einem Halbleitersubstrat |
CN104600027B (zh) * | 2015-01-30 | 2017-10-27 | 华进半导体封装先导技术研发中心有限公司 | 一种tsv通孔的制备工艺 |
US9917027B2 (en) * | 2015-12-30 | 2018-03-13 | Globalfoundries Singapore Pte. Ltd. | Integrated circuits with aluminum via structures and methods for fabricating the same |
CN105552091A (zh) * | 2016-03-09 | 2016-05-04 | 京东方科技集团股份有限公司 | 阵列基板及其制备方法、显示面板 |
CN106946769B (zh) * | 2017-04-16 | 2019-04-02 | 内蒙古佳瑞米精细化工有限公司 | 一种2-氟-5-三氟甲基吡啶的合成方法 |
US10157773B1 (en) * | 2017-11-28 | 2018-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure having layer with re-entrant profile and method of forming the same |
US10867842B2 (en) * | 2018-10-31 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for shrinking openings in forming integrated circuits |
CN110120382A (zh) * | 2019-05-23 | 2019-08-13 | 上海华虹宏力半导体制造有限公司 | 半导体器件及形成方法 |
CN111508835A (zh) * | 2020-04-26 | 2020-08-07 | 深圳市昭矽微电子科技有限公司 | 图形结构及其形成方法 |
CN112928069B (zh) * | 2021-02-05 | 2023-02-28 | 长鑫存储技术有限公司 | 半导体结构的制作方法及半导体结构 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3880684A (en) * | 1973-08-03 | 1975-04-29 | Mitsubishi Electric Corp | Process for preparing semiconductor |
JPS57100731A (en) * | 1980-12-15 | 1982-06-23 | Nec Corp | Manufacture of semiconductor device |
US4376672A (en) * | 1981-10-26 | 1983-03-15 | Applied Materials, Inc. | Materials and methods for plasma etching of oxides and nitrides of silicon |
US4461672A (en) * | 1982-11-18 | 1984-07-24 | Texas Instruments, Inc. | Process for etching tapered vias in silicon dioxide |
US4487652A (en) * | 1984-03-30 | 1984-12-11 | Motorola, Inc. | Slope etch of polyimide |
US4484979A (en) * | 1984-04-16 | 1984-11-27 | At&T Bell Laboratories | Two-step anisotropic etching process for patterning a layer without penetrating through an underlying thinner layer |
US4522681A (en) * | 1984-04-23 | 1985-06-11 | General Electric Company | Method for tapered dry etching |
US4631248A (en) * | 1985-06-21 | 1986-12-23 | Lsi Logic Corporation | Method for forming an electrical contact in an integrated circuit |
JPS6218054A (ja) * | 1985-07-17 | 1987-01-27 | Hitachi Ltd | 半導体装置の製造方法 |
US4676869A (en) * | 1986-09-04 | 1987-06-30 | American Telephone And Telegraph Company At&T Bell Laboratories | Integrated circuits having stepped dielectric regions |
JP3131058B2 (ja) * | 1992-12-25 | 2001-01-31 | 京セラ株式会社 | アルミナ質焼結体 |
-
1986
- 1986-10-08 DE DE8686430035T patent/DE3686721D1/de not_active Expired - Lifetime
- 1986-10-08 EP EP86430035A patent/EP0263220B1/de not_active Expired
-
1987
- 1987-07-20 JP JP62179271A patent/JPH0626205B2/ja not_active Expired - Lifetime
- 1987-09-22 US US07/099,856 patent/US4814041A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0626205B2 (ja) | 1994-04-06 |
JPS63104338A (ja) | 1988-05-09 |
US4814041A (en) | 1989-03-21 |
EP0263220A1 (de) | 1988-04-13 |
EP0263220B1 (de) | 1992-09-09 |
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Legal Events
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8332 | No legal effect for de |