DE3483579D1 - Verfahren zum herstellen einer leiterbahn. - Google Patents

Verfahren zum herstellen einer leiterbahn.

Info

Publication number
DE3483579D1
DE3483579D1 DE8484308210T DE3483579T DE3483579D1 DE 3483579 D1 DE3483579 D1 DE 3483579D1 DE 8484308210 T DE8484308210 T DE 8484308210T DE 3483579 T DE3483579 T DE 3483579T DE 3483579 D1 DE3483579 D1 DE 3483579D1
Authority
DE
Germany
Prior art keywords
producing
lead path
lead
path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484308210T
Other languages
English (en)
Inventor
Hirosi C O Patent Divi Oodaira
Haruko C O Patent Divis Suzuki
Masayuki C O Patent Divi Saito
Masayuki C O Patent Div Ohuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3483579D1 publication Critical patent/DE3483579D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/105—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by conversion of non-conductive material on or in the support into conductive material, e.g. by using an energy beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0106—Neodymium [Nd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1131—Sintering, i.e. fusing of metal particles to achieve or improve electrical conductivity
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/12—Using specific substances
    • H05K2203/121—Metallo-organic compounds
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Laser Beam Processing (AREA)
DE8484308210T 1984-02-10 1984-11-27 Verfahren zum herstellen einer leiterbahn. Expired - Lifetime DE3483579D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59023088A JPS60167491A (ja) 1984-02-10 1984-02-10 導体路形成方法

Publications (1)

Publication Number Publication Date
DE3483579D1 true DE3483579D1 (de) 1990-12-13

Family

ID=12100668

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484308210T Expired - Lifetime DE3483579D1 (de) 1984-02-10 1984-11-27 Verfahren zum herstellen einer leiterbahn.

Country Status (4)

Country Link
US (1) US4694138A (de)
EP (1) EP0159443B1 (de)
JP (1) JPS60167491A (de)
DE (1) DE3483579D1 (de)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60208891A (ja) * 1984-04-02 1985-10-21 日産化学工業株式会社 金属層パタ−ンの形成方法
DE3411797A1 (de) * 1984-03-30 1985-10-10 Bayer Ag, 5090 Leverkusen Verfahren zur kennzeichnung von kunststoffteilen
JPS6286891A (ja) * 1985-10-10 1987-04-21 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 基板上に回路を書込む方法
JPH01184942A (ja) * 1988-01-20 1989-07-24 Toshiba Corp トリミング素子とその電気短絡方法
JP2733244B2 (ja) * 1988-04-07 1998-03-30 株式会社日立製作所 配線形成方法
JPH0817269B2 (ja) * 1988-05-11 1996-02-21 株式会社ソフィアシステムズ 回路ライター
US5099090A (en) * 1988-05-11 1992-03-24 Ariel Electronics, Inc. Circuit writer
US5052102A (en) * 1989-06-19 1991-10-01 Shell Oil Company Laser induced electrical connection of integrated circuits
DE3922233A1 (de) * 1989-07-06 1991-01-17 Guenter Link Verfahren zur abscheidung von metallen aus metallorganischen verbindungen mittels photonenstrahlung
US4937425A (en) * 1989-08-29 1990-06-26 Hughes Aircraft Company Method of making a polarizing parabolic dish antenna reflector
US5077891A (en) * 1990-04-30 1992-01-07 Ag Communication Systems Corporation Method for reconstructing the conductor traces of a printed circuit board assembly
US5233157A (en) * 1990-09-11 1993-08-03 Hughes Aircraft Company Laser pattern ablation of fine line circuitry masters
US5153408A (en) * 1990-10-31 1992-10-06 International Business Machines Corporation Method and structure for repairing electrical lines
US5292558A (en) * 1991-08-08 1994-03-08 University Of Texas At Austin, Texas Process for metal deposition for microelectronic interconnections
JP3086066B2 (ja) * 1991-10-29 2000-09-11 富士通株式会社 クリーム状はんだの印刷方法及び電子部品のソルダリング方法
JPH05251121A (ja) * 1991-12-18 1993-09-28 Xerox Corp 多層配線組立体
JP3342906B2 (ja) * 1991-12-18 2002-11-11 ゼロックス・コーポレーション 電子装置及び電子スイッチ
JPH07302858A (ja) * 1994-04-28 1995-11-14 Toshiba Corp 半導体パッケージ
US5516458A (en) * 1994-08-30 1996-05-14 Eastman Kodak Company Coating composition used to prepare an electrically-conductive layer formed by a glow discharge process containing tin carboxylate, antimony alkoxide and film-forming binder
DE69623938T2 (de) * 1996-06-21 2003-05-22 Pirelli Cavi E Sistemi S.P.A., Mailand/Milano Gegen Wasserbäumchen widerstandsfähige Isolierungszusammensetzung
US6261927B1 (en) * 1999-04-30 2001-07-17 International Business Machines Corporation Method of forming defect-free ceramic structures using thermally depolymerizable surface layer
FR2804796B1 (fr) * 2000-02-04 2004-11-19 Gemplus Card Int Procede pour la realisation de connexions electriques notamment pour un dispositif electronique
GB0123676D0 (en) * 2001-10-02 2001-11-21 Poly Flex Circuits Ltd Method of manufacturing circuits
US6979478B1 (en) * 2002-08-01 2005-12-27 Hilemn, Llc Paint for silver film protection and method
DE10320090A1 (de) * 2003-05-05 2004-08-26 Infineon Technologies Ag Elektrisches Bauteil mit Leitungen aus karbonisiertem Kunststoff, sowie Verfahren und Vorrichtung zu seiner Herstellung
JP4589606B2 (ja) * 2003-06-02 2010-12-01 住友重機械工業株式会社 半導体装置の製造方法
DE102004020497B8 (de) * 2004-04-26 2006-06-14 Infineon Technologies Ag Verfahren zur Herstellung von Durchkontaktierungen und Halbleiterbauteil mit derartigen Durchkontaktierungen
US8323802B2 (en) * 2004-10-20 2012-12-04 E I Du Pont De Nemours And Company Light activatable polyimide compositions for receiving selective metalization, and methods and compositions related thereto
US20060083939A1 (en) * 2004-10-20 2006-04-20 Dunbar Meredith L Light activatable polyimide compositions for receiving selective metalization, and methods and compositions related thereto
DE102004052301A1 (de) * 2004-10-27 2006-05-11 Jens Freye Verfahren zur Herstellung von Leiterbahnstrukturen
DE102004052303A1 (de) * 2004-10-27 2006-05-11 Jens Freye Verfahren zur Herstellung von Funktionselementstrukturen
DE102004052300A1 (de) * 2004-10-27 2006-05-11 Jens Freye Verfahren zur Herstellung von Leiterbahnstrukturen
US7547849B2 (en) * 2005-06-15 2009-06-16 E.I. Du Pont De Nemours And Company Compositions useful in electronic circuitry type applications, patternable using amplified light, and methods and compositions relating thereto
US7504150B2 (en) * 2005-06-15 2009-03-17 E.I. Du Pont De Nemours & Company Polymer-based capacitor composites capable of being light-activated and receiving direct metalization, and methods and compositions related thereto
US20080213605A1 (en) * 2006-12-07 2008-09-04 Briney Gary C Multi-functional circuitry substrates and compositions and methods relating thereto
US8475924B2 (en) * 2007-07-09 2013-07-02 E.I. Du Pont De Nemours And Company Compositions and methods for creating electronic circuitry
DE102008052586A1 (de) * 2008-10-21 2010-04-22 Leibniz-Institut Für Neue Materialien Gemeinnützige Gmbh Zusammensetzung zur Herstellung optischer Elemente mit Gradientenstruktur
DE102008058535A1 (de) * 2008-11-21 2010-05-27 Tesa Se Verfahren zur Materialbearbeitung mit energiereicher Strahlung
US20100193950A1 (en) * 2009-01-30 2010-08-05 E.I.Du Pont De Nemours And Company Wafer level, chip scale semiconductor device packaging compositions, and methods relating thereto
DE102011007537A1 (de) * 2011-04-15 2012-10-18 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. In einem Kunststoffkörper eingebettetes Funktionselement und Verfahren zur elektrischen Kontaktierung eines in einem Kunststoffkörper eingebetteten Funktionselements
US20140097002A1 (en) * 2012-10-05 2014-04-10 Tyco Electronics Amp Gmbh Electrical components and methods and systems of manufacturing electrical components
US20180174940A1 (en) * 2016-12-19 2018-06-21 Intel Corporation Fine-featured traces for integrated circuit package support structures
US20180178322A1 (en) * 2016-12-28 2018-06-28 Metal Industries Research & Development Centre Laser processing device and laser processing method
CN110972406B (zh) * 2019-12-04 2020-07-28 广东工业大学 一种用于精细线路的修复方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1172891B (it) * 1978-07-04 1987-06-18 Fiat Spa Procedimento per rivestire con materiale antiusura una superficie metallica
US4181538A (en) * 1978-09-26 1980-01-01 The United States Of America As Represented By The United States Department Of Energy Method for making defect-free zone by laser-annealing of doped silicon
US4286250A (en) * 1979-05-04 1981-08-25 New England Instrument Company Laser formed resistor elements
US4338506A (en) * 1979-09-07 1982-07-06 Motorola, Inc. Method of trimming thick film capacitor
US4303698A (en) * 1980-02-25 1981-12-01 E. I. Du Pont De Nemours And Company Use of prolonged tack toners for the preparation of electric circuits
JPS5812392A (ja) * 1981-07-15 1983-01-24 株式会社日立製作所 平坦化配線
GB2113720B (en) * 1982-01-07 1985-12-04 Standard Telephones Cables Ltd Fabricating solder tracks
JPS58139405A (ja) * 1982-02-15 1983-08-18 アルプス電気株式会社 抵抗素子の製造方法

Also Published As

Publication number Publication date
US4694138A (en) 1987-09-15
EP0159443A2 (de) 1985-10-30
EP0159443B1 (de) 1990-11-07
JPS60167491A (ja) 1985-08-30
EP0159443A3 (en) 1987-03-11

Similar Documents

Publication Publication Date Title
DE3483579D1 (de) Verfahren zum herstellen einer leiterbahn.
DE3586732D1 (de) Verfahren zum herstellen einer dreidimentionaler halbleiteranordung.
DE3686600D1 (de) Verfahren zum herstellen einer harzumhuellten halbleiteranordnung.
DE3584757D1 (de) Verfahren zum herstellen einer zwei-wannen-cmos-halbleiterstruktur.
DE3583934D1 (de) Verfahren zum herstellen einer halbleiterverbundanordnung.
DE3587231D1 (de) Verfahren zum herstellen einer dmos-halbleiteranordnung.
DE3586109D1 (de) Verfahren zum herstellen einer verbindungsstruktur von einer halbleiteranordnung.
DE3583472D1 (de) Verfahren zum herstellen einer halbleiteranordnung mit gateelektrode.
DE3483280D1 (de) Verfahren zum herstellen einer mehrschicht-halbleiteranordnung.
DE3780369D1 (de) Verfahren zum herstellen einer halbleiterstruktur.
DE3686453D1 (de) Verfahren zum herstellen einer duennen halbleiterschicht.
DE3584071D1 (de) Verfahren zum aufrauhen einer flaeche.
DE3685970D1 (de) Verfahren zum herstellen eines halbleiterbauelements.
DE3577371D1 (de) Apparat zum herstellen einer halbleiteranordnung.
DE3578614D1 (de) Verfahren zum herstellen von chip-einfuegungsschichten.
DE3483531D1 (de) Verfahren zum herstellen einer integrierten halbleiterschaltkreisanordnung mit einem misfet.
DE3579174D1 (de) Verfahren zum herstellen einer halbleiterspeicherstruktur und halbleiterspeicherstruktur.
DE3382563D1 (de) Verfahren zum unterscheiden zwischen komplexen zeichenvorraeten.
DE3671324D1 (de) Verfahren zum herstellen einer halbleiteranordnung.
DE3582627D1 (de) Verfahren zum herstellen einer waermeschrumpfenden polypropylenfolie.
DE68906034D1 (de) Verfahren zum herstellen einer halbleiteranordnung.
DE3579770D1 (de) Verfahren zum herstellen eines eines verstaerkungsbauteils.
DE3574525D1 (de) Verfahren zum herstellen von kontakten auf einer halbleitervorrichtung.
DE3684202D1 (de) Verfahren zum herstellen einer passivierungsschicht.
DE3581565D1 (de) Verfahren zum steuern einer spritzgiessmaschine.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee