DE3579174D1 - Verfahren zum herstellen einer halbleiterspeicherstruktur und halbleiterspeicherstruktur. - Google Patents

Verfahren zum herstellen einer halbleiterspeicherstruktur und halbleiterspeicherstruktur.

Info

Publication number
DE3579174D1
DE3579174D1 DE8585300476T DE3579174T DE3579174D1 DE 3579174 D1 DE3579174 D1 DE 3579174D1 DE 8585300476 T DE8585300476 T DE 8585300476T DE 3579174 T DE3579174 T DE 3579174T DE 3579174 D1 DE3579174 D1 DE 3579174D1
Authority
DE
Germany
Prior art keywords
semiconductor storage
storage structure
producing
semiconductor
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585300476T
Other languages
English (en)
Inventor
Eaton, Jr
Cheng-Cheng Hu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thorn EMI North America Inc
Original Assignee
Thorn EMI North America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thorn EMI North America Inc filed Critical Thorn EMI North America Inc
Application granted granted Critical
Publication of DE3579174D1 publication Critical patent/DE3579174D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/082—Ion implantation FETs/COMs

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
  • Static Random-Access Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE8585300476T 1984-01-26 1985-01-24 Verfahren zum herstellen einer halbleiterspeicherstruktur und halbleiterspeicherstruktur. Expired - Lifetime DE3579174D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/574,056 US4570331A (en) 1984-01-26 1984-01-26 Thick oxide field-shield CMOS process

Publications (1)

Publication Number Publication Date
DE3579174D1 true DE3579174D1 (de) 1990-09-20

Family

ID=24294510

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585300476T Expired - Lifetime DE3579174D1 (de) 1984-01-26 1985-01-24 Verfahren zum herstellen einer halbleiterspeicherstruktur und halbleiterspeicherstruktur.

Country Status (4)

Country Link
US (1) US4570331A (de)
EP (1) EP0150993B1 (de)
JP (1) JPH0691220B2 (de)
DE (1) DE3579174D1 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4696092A (en) * 1984-07-02 1987-09-29 Texas Instruments Incorporated Method of making field-plate isolated CMOS devices
US4720467A (en) * 1986-09-29 1988-01-19 International Business Machines Corporation Method of forming a capacitor-transistor integrated circuit
US5223735A (en) * 1988-09-30 1993-06-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device in which circuit functions can be remedied or changed and the method for producing the same
JPH02172253A (ja) * 1988-12-24 1990-07-03 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2598328B2 (ja) * 1989-10-17 1997-04-09 三菱電機株式会社 半導体装置およびその製造方法
US5216281A (en) * 1990-04-05 1993-06-01 Ramtron Corporation Self sealed aligned contact incorporating a dopant source
US5043790A (en) * 1990-04-05 1991-08-27 Ramtron Corporation Sealed self aligned contacts using two nitrides process
US5104822A (en) * 1990-07-30 1992-04-14 Ramtron Corporation Method for creating self-aligned, non-patterned contact areas and stacked capacitors using the method
JPH06291181A (ja) * 1993-03-30 1994-10-18 Nippon Steel Corp 半導体装置の製造方法
US5498898A (en) * 1993-12-28 1996-03-12 Nippon Steel Corporation Semiconductor device using element isolation by field shield
US5610099A (en) * 1994-06-28 1997-03-11 Ramtron International Corporation Process for fabricating transistors using composite nitride structure
EP0718881B1 (de) * 1994-12-20 2003-07-16 STMicroelectronics, Inc. Isolierung durch aktive Transistoren mit geerdeten Torelektroden
US6380598B1 (en) 1994-12-20 2002-04-30 Stmicroelectronics, Inc. Radiation hardened semiconductor memory
JPH08293560A (ja) * 1995-04-24 1996-11-05 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5606202A (en) * 1995-04-25 1997-02-25 International Business Machines, Corporation Planarized gate conductor on substrates with above-surface isolation
US5834820A (en) * 1995-10-13 1998-11-10 Micron Technology, Inc. Circuit for providing isolation of integrated circuit active areas
US20050036363A1 (en) * 1996-05-24 2005-02-17 Jeng-Jye Shau High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
US5748547A (en) * 1996-05-24 1998-05-05 Shau; Jeng-Jye High performance semiconductor memory devices having multiple dimension bit lines
US7064376B2 (en) * 1996-05-24 2006-06-20 Jeng-Jye Shau High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
US6288423B1 (en) * 1997-04-18 2001-09-11 Nippon Steel Corporation Composite gate structure memory cell having increased capacitance
US5986314A (en) * 1997-10-08 1999-11-16 Texas Instruments Incorporated Depletion mode MOS capacitor with patterned Vt implants
US6091630A (en) * 1999-09-10 2000-07-18 Stmicroelectronics, Inc. Radiation hardened semiconductor memory
US6806123B2 (en) * 2002-04-26 2004-10-19 Micron Technology, Inc. Methods of forming isolation regions associated with semiconductor constructions
US6756619B2 (en) * 2002-08-26 2004-06-29 Micron Technology, Inc. Semiconductor constructions
US7112838B2 (en) * 2004-03-31 2006-09-26 Broadcom Corporation Multipurpose metal fill
US8993457B1 (en) 2014-02-06 2015-03-31 Cypress Semiconductor Corporation Method of fabricating a charge-trapping gate stack using a CMOS process flow
US20160178467A1 (en) * 2014-07-29 2016-06-23 Silicon Microstructures, Inc. Pressure sensor having cap-defined membrane

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4240093A (en) * 1976-12-10 1980-12-16 Rca Corporation Integrated circuit device including both N-channel and P-channel insulated gate field effect transistors
JPS607389B2 (ja) * 1978-12-26 1985-02-23 超エル・エス・アイ技術研究組合 半導体装置の製造方法
US4240845A (en) * 1980-02-04 1980-12-23 International Business Machines Corporation Method of fabricating random access memory device
US4441246A (en) * 1980-05-07 1984-04-10 Texas Instruments Incorporated Method of making memory cell by selective oxidation of polysilicon
DE3032632A1 (de) * 1980-08-29 1982-04-08 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung integrierter dynamischer ram-eintransistor-speicherzellen
US4380113A (en) * 1980-11-17 1983-04-19 Signetics Corporation Process for fabricating a high capacity memory cell
DE3044132A1 (de) * 1980-11-24 1982-07-15 Siemens AG, 1000 Berlin und 8000 München Dynamische halbleiter-speicherzelle mit wahlfreiem zugriff und verfahren zu ihrer herstellung
JPS57188866A (en) * 1981-05-18 1982-11-19 Hitachi Ltd Manufacture of semiconductor device
US4352236A (en) * 1981-07-24 1982-10-05 Intel Corporation Double field oxidation process
US4411058A (en) * 1981-08-31 1983-10-25 Hughes Aircraft Company Process for fabricating CMOS devices with self-aligned channel stops
US4507159A (en) * 1981-10-07 1985-03-26 Advanced Micro Devices, Inc. Method of manufacturing high capacity semiconductor capacitance devices
US4506436A (en) * 1981-12-21 1985-03-26 International Business Machines Corporation Method for increasing the radiation resistance of charge storage semiconductor devices
GB2114367A (en) * 1982-01-28 1983-08-17 Western Electric Co Semiconductor memory device
DE3205858A1 (de) * 1982-02-18 1983-08-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von dynamischen halbleiter-speicherzellen mit wahlfreiem zugriff (ram) nach der doppel-polysilizium-gate-technologie
US4466177A (en) * 1983-06-30 1984-08-21 International Business Machines Corporation Storage capacitor optimization for one device FET dynamic RAM cell

Also Published As

Publication number Publication date
US4570331A (en) 1986-02-18
JPH0691220B2 (ja) 1994-11-14
JPS60216577A (ja) 1985-10-30
EP0150993A2 (de) 1985-08-07
EP0150993A3 (en) 1986-10-15
EP0150993B1 (de) 1990-08-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee