DE3583472D1 - Verfahren zum herstellen einer halbleiteranordnung mit gateelektrode. - Google Patents
Verfahren zum herstellen einer halbleiteranordnung mit gateelektrode.Info
- Publication number
- DE3583472D1 DE3583472D1 DE8585110792T DE3583472T DE3583472D1 DE 3583472 D1 DE3583472 D1 DE 3583472D1 DE 8585110792 T DE8585110792 T DE 8585110792T DE 3583472 T DE3583472 T DE 3583472T DE 3583472 D1 DE3583472 D1 DE 3583472D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- gate electrode
- semiconductor arrangement
- semiconductor
- arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/082—Ion implantation FETs/COMs
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17865284A JPS6156459A (ja) | 1984-08-28 | 1984-08-28 | 半導体装置の製造方法 |
JP59178651A JPS6156448A (ja) | 1984-08-28 | 1984-08-28 | 相補型半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3583472D1 true DE3583472D1 (de) | 1991-08-22 |
Family
ID=26498758
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8585110792T Expired - Lifetime DE3583472D1 (de) | 1984-08-28 | 1985-08-28 | Verfahren zum herstellen einer halbleiteranordnung mit gateelektrode. |
Country Status (3)
Country | Link |
---|---|
US (1) | US4642878A (de) |
EP (1) | EP0173953B1 (de) |
DE (1) | DE3583472D1 (de) |
Families Citing this family (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3530065C2 (de) * | 1984-08-22 | 1999-11-18 | Mitsubishi Electric Corp | Verfahren zur Herstellung eines Halbleiters |
US4843023A (en) * | 1985-09-25 | 1989-06-27 | Hewlett-Packard Company | Process for forming lightly-doped-drain (LDD) without extra masking steps |
GB8527062D0 (en) * | 1985-11-02 | 1985-12-04 | Plessey Co Plc | Mos transistor manufacture |
US4760033A (en) * | 1986-04-08 | 1988-07-26 | Siemens Aktiengesellschaft | Method for the manufacture of complementary MOS field effect transistors in VLSI technology |
US4732865A (en) * | 1986-10-03 | 1988-03-22 | Tektronix, Inc. | Self-aligned internal mobile ion getter for multi-layer metallization on integrated circuits |
US4744859A (en) * | 1986-10-23 | 1988-05-17 | Vitelic Corporation | Process for fabricating lightly doped drain MOS devices |
US4757026A (en) * | 1986-11-04 | 1988-07-12 | Intel Corporation | Source drain doping technique |
US4885617A (en) * | 1986-11-18 | 1989-12-05 | Siemens Aktiengesellschaft | Metal-oxide semiconductor (MOS) field effect transistor having extremely shallow source/drain zones and silicide terminal zones, and a process for producing the transistor circuit |
JP2573201B2 (ja) * | 1987-02-26 | 1997-01-22 | 株式会社東芝 | 半導体素子の拡散層形成方法 |
JPH0834310B2 (ja) * | 1987-03-26 | 1996-03-29 | 沖電気工業株式会社 | 半導体装置の製造方法 |
US5024960A (en) * | 1987-06-16 | 1991-06-18 | Texas Instruments Incorporated | Dual LDD submicron CMOS process for making low and high voltage transistors with common gate |
US4753898A (en) * | 1987-07-09 | 1988-06-28 | Motorola, Inc. | LDD CMOS process |
US4771014A (en) * | 1987-09-18 | 1988-09-13 | Sgs-Thomson Microelectronics, Inc. | Process for manufacturing LDD CMOS devices |
US4907048A (en) * | 1987-11-23 | 1990-03-06 | Xerox Corporation | Double implanted LDD transistor self-aligned with gate |
IT1223571B (it) * | 1987-12-21 | 1990-09-19 | Sgs Thomson Microelectronics | Procedimento per la fabbricazione di dispositivi integrati cmos con lunghezze di porta ridotte |
JPH01173756A (ja) * | 1987-12-28 | 1989-07-10 | Toshiba Corp | 半導体装置の製造方法 |
IT1216476B (it) * | 1988-02-29 | 1990-03-08 | Sgs Thomson Microelectronics | Processo per l'ottenimento di transitori a canale n per alta tensione, particolarmente per memorie eeprom con tecnologia cmos. |
US4942449A (en) * | 1988-03-28 | 1990-07-17 | General Electric Company | Fabrication method and structure for field isolation in field effect transistors on integrated circuit chips |
US4908327A (en) * | 1988-05-02 | 1990-03-13 | Texas Instruments, Incorporated | Counter-doped transistor |
US4982257A (en) * | 1988-08-01 | 1991-01-01 | International Business Machines Corporation | Vertical bipolar transistor with collector and base extensions |
US4957875A (en) * | 1988-08-01 | 1990-09-18 | International Business Machines Corporation | Vertical bipolar transistor |
US5180682A (en) * | 1988-08-18 | 1993-01-19 | Seiko Epson Corporation | Semiconductor device and method of producing semiconductor device |
GB8820058D0 (en) * | 1988-08-24 | 1988-09-28 | Inmos Ltd | Mosfet & fabrication method |
US4876213A (en) * | 1988-10-31 | 1989-10-24 | Motorola, Inc. | Salicided source/drain structure |
US4978627A (en) * | 1989-02-22 | 1990-12-18 | Advanced Micro Devices, Inc. | Method of detecting the width of lightly doped drain regions |
US5013675A (en) * | 1989-05-23 | 1991-05-07 | Advanced Micro Devices, Inc. | Method of forming and removing polysilicon lightly doped drain spacers |
JP2760068B2 (ja) * | 1989-07-18 | 1998-05-28 | ソニー株式会社 | Mis型半導体装置の製造方法 |
US4994404A (en) * | 1989-08-28 | 1991-02-19 | Motorola, Inc. | Method for forming a lightly-doped drain (LDD) structure in a semiconductor device |
US5024959A (en) * | 1989-09-25 | 1991-06-18 | Motorola, Inc. | CMOS process using doped glass layer |
US5200351A (en) * | 1989-10-23 | 1993-04-06 | Advanced Micro Devices, Inc. | Method of fabricating field effect transistors having lightly doped drain regions |
FR2654258A1 (fr) * | 1989-11-03 | 1991-05-10 | Philips Nv | Procede pour fabriquer un dispositif a transistor mis ayant une electrode de grille en forme de "t" inverse. |
WO1991015030A1 (en) * | 1990-03-27 | 1991-10-03 | Sematech, Inc. | Staircase sidewall spacer for improved source/drain architecture |
US5102816A (en) * | 1990-03-27 | 1992-04-07 | Sematech, Inc. | Staircase sidewall spacer for improved source/drain architecture |
DE69132695T2 (de) * | 1990-05-11 | 2002-06-13 | Koninklijke Philips Electronics N.V., Eindhoven | CMOS-Verfahren mit Verwendung von zeitweilig angebrachten Siliciumnitrid-Spacern zum Herstellen von Transistoren (LDD) mit leicht dotiertem Drain |
US7253437B2 (en) * | 1990-12-25 | 2007-08-07 | Semiconductor Energy Laboratory Co., Ltd. | Display device having a thin film transistor |
US5821563A (en) | 1990-12-25 | 1998-10-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device free from reverse leakage and throw leakage |
JP2678094B2 (ja) * | 1991-03-01 | 1997-11-17 | シャープ株式会社 | ダイナミックランダムアクセスメモリ |
JP2994128B2 (ja) * | 1991-03-04 | 1999-12-27 | シャープ株式会社 | 半導体装置の製造方法 |
US5894158A (en) * | 1991-09-30 | 1999-04-13 | Stmicroelectronics, Inc. | Having halo regions integrated circuit device structure |
US5409847A (en) * | 1993-10-27 | 1995-04-25 | Matsushita Electric Industrial Co., Ltd. | Manufacturing method of CMOS transistor in which heat treatment at higher temperature is done prior to heat treatment at low temperature |
US6083810A (en) * | 1993-11-15 | 2000-07-04 | Lucent Technologies | Integrated circuit fabrication process |
JP2873660B2 (ja) * | 1994-01-08 | 1999-03-24 | 株式会社半導体エネルギー研究所 | 半導体集積回路の作製方法 |
US5622886A (en) * | 1994-03-31 | 1997-04-22 | Atmel Corporation | Method of making a high voltage rectifier for an integrated circuit chip |
US5460993A (en) * | 1995-04-03 | 1995-10-24 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of making NMOS and PMOS LDD transistors utilizing thinned sidewall spacers |
JP3399186B2 (ja) * | 1995-10-13 | 2003-04-21 | ソニー株式会社 | 不揮発性半導体記憶装置の製造方法 |
US5849622A (en) * | 1997-03-07 | 1998-12-15 | Advanced Micro Devices, Inc. | Method of forming a source implant at a contact masking step of a process flow |
US5861335A (en) * | 1997-03-21 | 1999-01-19 | Advanced Micro Devices, Inc. | Semiconductor fabrication employing a post-implant anneal within a low temperature high pressure nitrogen ambient to improve channel and gate oxide reliability |
US6060345A (en) * | 1997-04-21 | 2000-05-09 | Advanced Micro Devices, Inc. | Method of making NMOS and PMOS devices with reduced masking steps |
US6376879B2 (en) * | 1998-06-08 | 2002-04-23 | Kabushiki Kaisha Toshiba | Semiconductor device having MISFETs |
US6051865A (en) * | 1998-11-09 | 2000-04-18 | Advanced Micro Devices, Inc. | Transistor having a barrier layer below a high permittivity gate dielectric |
US6764917B1 (en) * | 2001-12-20 | 2004-07-20 | Advanced Micro Devices, Inc. | SOI device with different silicon thicknesses |
KR100528465B1 (ko) * | 2003-02-11 | 2005-11-15 | 삼성전자주식회사 | 모오스 전계 효과 트랜지스터의 제조 방법 |
KR100505676B1 (ko) * | 2003-03-10 | 2005-08-03 | 삼성전자주식회사 | Ldd 구조를 가지는 반도체 소자 제조 방법 |
US8089144B2 (en) | 2008-12-17 | 2012-01-03 | Denso Corporation | Semiconductor device and method for manufacturing the same |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4356623A (en) * | 1980-09-15 | 1982-11-02 | Texas Instruments Incorporated | Fabrication of submicron semiconductor devices |
US4366613A (en) * | 1980-12-17 | 1983-01-04 | Ibm Corporation | Method of fabricating an MOS dynamic RAM with lightly doped drain |
JPS57199221A (en) * | 1981-06-02 | 1982-12-07 | Toshiba Corp | Manufacture of semiconductor device |
US4435896A (en) * | 1981-12-07 | 1984-03-13 | Bell Telephone Laboratories, Incorporated | Method for fabricating complementary field effect transistor devices |
US4442591A (en) * | 1982-02-01 | 1984-04-17 | Texas Instruments Incorporated | High-voltage CMOS process |
JPS58158972A (ja) * | 1982-03-16 | 1983-09-21 | Toshiba Corp | 半導体装置の製造方法 |
JPS5936929A (ja) * | 1982-08-25 | 1984-02-29 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US4566175A (en) * | 1982-08-30 | 1986-01-28 | Texas Instruments Incorporated | Method of making insulated gate field effect transistor with a lightly doped drain using oxide sidewall spacer and double implantations |
JPS5952849A (ja) * | 1982-09-20 | 1984-03-27 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS5955054A (ja) * | 1982-09-24 | 1984-03-29 | Hitachi Ltd | 半導体装置の製造方法 |
US4536944A (en) * | 1982-12-29 | 1985-08-27 | International Business Machines Corporation | Method of making ROM/PLA semiconductor device by late stage personalization |
US4535528A (en) * | 1983-12-02 | 1985-08-20 | Hewlett-Packard Company | Method for improving reflow of phosphosilicate glass by arsenic implantation |
US4527325A (en) * | 1983-12-23 | 1985-07-09 | International Business Machines Corporation | Process for fabricating semiconductor devices utilizing a protective film during high temperature annealing |
US4555842A (en) * | 1984-03-19 | 1985-12-03 | At&T Bell Laboratories | Method of fabricating VLSI CMOS devices having complementary threshold voltages |
US4554726A (en) * | 1984-04-17 | 1985-11-26 | At&T Bell Laboratories | CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well |
US4561170A (en) * | 1984-07-02 | 1985-12-31 | Texas Instruments Incorporated | Method of making field-plate isolated CMOS devices |
-
1985
- 1985-08-28 US US06/770,179 patent/US4642878A/en not_active Expired - Lifetime
- 1985-08-28 EP EP85110792A patent/EP0173953B1/de not_active Expired
- 1985-08-28 DE DE8585110792T patent/DE3583472D1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0173953A2 (de) | 1986-03-12 |
EP0173953B1 (de) | 1991-07-17 |
US4642878A (en) | 1987-02-17 |
EP0173953A3 (en) | 1988-01-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8320 | Willingness to grant licences declared (paragraph 23) |