DE19983274T1 - Verfahren zum Herstellen eines Halbleiterbauteils - Google Patents

Verfahren zum Herstellen eines Halbleiterbauteils

Info

Publication number
DE19983274T1
DE19983274T1 DE19983274T DE19983274T DE19983274T1 DE 19983274 T1 DE19983274 T1 DE 19983274T1 DE 19983274 T DE19983274 T DE 19983274T DE 19983274 T DE19983274 T DE 19983274T DE 19983274 T1 DE19983274 T1 DE 19983274T1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19983274T
Other languages
English (en)
Other versions
DE19983274B4 (de
Inventor
Fumio Naito
Hisaya Imai
Hidenori Mochizuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Kasei Microsystems Co Ltd
Original Assignee
Asahi Kasei Microsystems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Kasei Microsystems Co Ltd filed Critical Asahi Kasei Microsystems Co Ltd
Priority claimed from PCT/JP1999/001731 external-priority patent/WO2000060661A1/ja
Publication of DE19983274T1 publication Critical patent/DE19983274T1/de
Application granted granted Critical
Publication of DE19983274B4 publication Critical patent/DE19983274B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42Simultaneous manufacture of periphery and memory cells
    • H10B41/43Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/48Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
DE1999183274 1999-04-01 1999-04-01 Verfahren zum Herstellen eines nichtflüchtigen Halbleiterspeicherbauteils Expired - Fee Related DE19983274B4 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1999/001731 WO2000060661A1 (fr) 1997-10-02 1999-04-01 Procede de production d'un dispositif a semi-conducteur

Publications (2)

Publication Number Publication Date
DE19983274T1 true DE19983274T1 (de) 2001-06-21
DE19983274B4 DE19983274B4 (de) 2004-10-28

Family

ID=14235371

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1999183274 Expired - Fee Related DE19983274B4 (de) 1999-04-01 1999-04-01 Verfahren zum Herstellen eines nichtflüchtigen Halbleiterspeicherbauteils

Country Status (3)

Country Link
US (1) US6472259B1 (de)
KR (1) KR100383703B1 (de)
DE (1) DE19983274B4 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001332637A (ja) * 2000-05-23 2001-11-30 Nec Corp 半導体記憶装置及びその製造方法
JP2002083883A (ja) * 2000-09-06 2002-03-22 Oki Electric Ind Co Ltd 不揮発性半導体記憶装置およびその製造方法
US7256449B2 (en) * 2003-05-20 2007-08-14 Samsung Electronics, Co., Ltd. EEPROM device for increasing a coupling ratio and fabrication method thereof
US20040232476A1 (en) * 2003-05-20 2004-11-25 Kang Sung-Taeg EEPROM cell structures having non-uniform channel-dielectric thickness and methods of making the same
KR100604850B1 (ko) * 2003-05-20 2006-07-31 삼성전자주식회사 균일하지 않은 채널 유전막 두께를 갖는 이이피롬 셀 구조및 그 제조방법
KR100518577B1 (ko) * 2003-05-26 2005-10-04 삼성전자주식회사 원 타임 프로그래머블 메모리 소자 및 이를 포함하는반도체 집적회로와 그 제조방법
JP4558557B2 (ja) * 2005-03-31 2010-10-06 富士通セミコンダクター株式会社 不揮発性半導体記憶装置
DE102006013209B4 (de) * 2006-03-22 2017-03-09 Austriamicrosystems Ag Verfahren zur Herstellung von Halbleiterbauelementen mit Oxidschichten und Halbleiterbauelement mit Oxidschichten
CN104952734B (zh) * 2015-07-16 2020-01-24 矽力杰半导体技术(杭州)有限公司 半导体结构及其制造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6223150A (ja) 1985-07-24 1987-01-31 Hitachi Ltd 半導体集積回路装置の製造方法
JPS6276668A (ja) 1985-09-30 1987-04-08 Toshiba Corp 半導体記憶装置
JPS63144577A (ja) 1986-12-09 1988-06-16 Toshiba Corp 不揮発性半導体記憶装置
US4851361A (en) 1988-02-04 1989-07-25 Atmel Corporation Fabrication process for EEPROMS with high voltage transistors
IT1237894B (it) 1989-12-14 1993-06-18 Sgs Thomson Microelectronics Processo per la fabbricazione di circuiti integrati comprendenti componenti elettronici di due tipi diversi aventi ciascuno coppie di elettrodi ricavati dagli stessi strati di silicio policristallino e separati da dielettrici diversi
JP3397903B2 (ja) * 1994-08-23 2003-04-21 新日本製鐵株式会社 不揮発性半導体記憶装置の製造方法
US5550072A (en) * 1994-08-30 1996-08-27 National Semiconductor Corporation Method of fabrication of integrated circuit chip containing EEPROM and capacitor
JP3366173B2 (ja) * 1995-07-31 2003-01-14 シャープ株式会社 不揮発性半導体メモリの製造方法
KR100239459B1 (ko) 1996-12-26 2000-01-15 김영환 반도체 메모리 소자 및 그 제조방법
US5837584A (en) * 1997-01-15 1998-11-17 Macronix International Co., Ltd. Virtual ground flash cell with asymmetrically placed source and drain and method of fabrication
US5963808A (en) * 1997-01-15 1999-10-05 Macronix International Co., Ltd. Method of forming an asymmetric bird's beak cell for a flash EEPROM
JP3556079B2 (ja) 1997-10-02 2004-08-18 旭化成マイクロシステム株式会社 半導体装置の製造方法
KR100275741B1 (ko) * 1998-08-31 2000-12-15 윤종용 비휘발성 기억소자의 제조방법

Also Published As

Publication number Publication date
KR100383703B1 (ko) 2003-05-14
KR20010052489A (ko) 2001-06-25
DE19983274B4 (de) 2004-10-28
US6472259B1 (en) 2002-10-29

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8607 Notification of search results after publication
8128 New person/name/address of the agent

Representative=s name: KRAMER - BARSKE - SCHMIDTCHEN, 81245 MUENCHEN

8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee
R079 Amendment of ipc main class

Free format text: PREVIOUS MAIN CLASS: H01L0021824700

Ipc: H01L0027115170