DE60025991D1 - Verfahren zum Bilden eines Bauelement-Isolationsgebietes - Google Patents

Verfahren zum Bilden eines Bauelement-Isolationsgebietes

Info

Publication number
DE60025991D1
DE60025991D1 DE60025991T DE60025991T DE60025991D1 DE 60025991 D1 DE60025991 D1 DE 60025991D1 DE 60025991 T DE60025991 T DE 60025991T DE 60025991 T DE60025991 T DE 60025991T DE 60025991 D1 DE60025991 D1 DE 60025991D1
Authority
DE
Germany
Prior art keywords
forming
isolation region
device isolation
region
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60025991T
Other languages
English (en)
Other versions
DE60025991T2 (de
Inventor
Naoki Ueda
Masayuki Hirata
Shinichi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of DE60025991D1 publication Critical patent/DE60025991D1/de
Application granted granted Critical
Publication of DE60025991T2 publication Critical patent/DE60025991T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Local Oxidation Of Silicon (AREA)
DE60025991T 1999-04-28 2000-04-28 Verfahren zum Bilden eines Bauelement-Isolationsgebiets Expired - Lifetime DE60025991T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP12109599 1999-04-28
JP12109599A JP3566880B2 (ja) 1999-04-28 1999-04-28 素子分離領域の形成方法

Publications (2)

Publication Number Publication Date
DE60025991D1 true DE60025991D1 (de) 2006-04-20
DE60025991T2 DE60025991T2 (de) 2006-10-19

Family

ID=14802763

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60025991T Expired - Lifetime DE60025991T2 (de) 1999-04-28 2000-04-28 Verfahren zum Bilden eines Bauelement-Isolationsgebiets

Country Status (6)

Country Link
US (1) US6323107B1 (de)
EP (1) EP1049154B1 (de)
JP (1) JP3566880B2 (de)
KR (1) KR100367051B1 (de)
DE (1) DE60025991T2 (de)
TW (1) TW473907B (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7289174B1 (en) 1995-07-17 2007-10-30 Seiko Epson Corporation Reflective type color liquid crystal device and an electronic apparatus using this
JP3702162B2 (ja) * 2000-09-25 2005-10-05 三洋電機株式会社 半導体装置の製造方法
JP2003100860A (ja) 2001-09-27 2003-04-04 Toshiba Corp 半導体装置
WO2003043078A2 (en) * 2001-11-13 2003-05-22 Advanced Micro Devices, Inc. Preferential corner rounding of trench structures using post-fill oxidation
KR100426485B1 (ko) * 2001-12-22 2004-04-14 주식회사 하이닉스반도체 플래쉬 메모리 셀의 제조 방법
US7439141B2 (en) * 2001-12-27 2008-10-21 Spansion, Llc Shallow trench isolation approach for improved STI corner rounding
US6890831B2 (en) * 2002-06-03 2005-05-10 Sanyo Electric Co., Ltd. Method of fabricating semiconductor device
KR100466189B1 (ko) * 2002-06-04 2005-01-13 주식회사 하이닉스반도체 플래시 메모리 셀의 제조 방법
KR100475081B1 (ko) * 2002-07-09 2005-03-10 삼성전자주식회사 Sonos형 eeprom 및 그 제조방법
JP2004095886A (ja) * 2002-08-30 2004-03-25 Fujitsu Ltd 半導体装置及びその製造方法
US20040065937A1 (en) * 2002-10-07 2004-04-08 Chia-Shun Hsiao Floating gate memory structures and fabrication methods
US7812375B2 (en) * 2003-05-28 2010-10-12 Samsung Electronics Co., Ltd. Non-volatile memory device and method of fabricating the same
KR100843244B1 (ko) 2007-04-19 2008-07-02 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR100719366B1 (ko) * 2005-06-15 2007-05-17 삼성전자주식회사 트렌치 소자분리막을 갖는 반도체 소자의 형성 방법
US20070262963A1 (en) * 2006-05-11 2007-11-15 Cypress Semiconductor Corporation Apparatus and method for recognizing a button operation on a sensing device
JP2008103420A (ja) * 2006-10-17 2008-05-01 Elpida Memory Inc 半導体装置の製造方法
US9006079B2 (en) * 2012-10-19 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming semiconductor fins with reduced widths

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258332A (en) * 1987-08-28 1993-11-02 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices including rounding of corner portions by etching
KR970053470A (ko) * 1995-12-29 1997-07-31 김주용 반도체소자의 소자분리막 제조방법
JP3414590B2 (ja) * 1996-06-20 2003-06-09 株式会社東芝 半導体装置の製造方法
US5834358A (en) * 1996-11-12 1998-11-10 Micron Technology, Inc. Isolation regions and methods of forming isolation regions
US5863827A (en) * 1997-06-03 1999-01-26 Texas Instruments Incorporated Oxide deglaze before sidewall oxidation of mesa or trench
US5880004A (en) * 1997-06-10 1999-03-09 Winbond Electronics Corp. Trench isolation process
US6103635A (en) * 1997-10-28 2000-08-15 Fairchild Semiconductor Corp. Trench forming process and integrated circuit device including a trench
US6054343A (en) * 1998-01-26 2000-04-25 Texas Instruments Incorporated Nitride trench fill process for increasing shallow trench isolation (STI) robustness
US6074932A (en) * 1998-01-28 2000-06-13 Texas Instruments - Acer Incorporated Method for forming a stress-free shallow trench isolation

Also Published As

Publication number Publication date
JP2000311938A (ja) 2000-11-07
EP1049154A3 (de) 2002-12-18
TW473907B (en) 2002-01-21
EP1049154A2 (de) 2000-11-02
KR20000071817A (ko) 2000-11-25
KR100367051B1 (ko) 2003-01-09
JP3566880B2 (ja) 2004-09-15
US6323107B1 (en) 2001-11-27
DE60025991T2 (de) 2006-10-19
EP1049154B1 (de) 2006-02-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition