CN208923105U - 表面贴装式半导体器件 - Google Patents

表面贴装式半导体器件 Download PDF

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CN208923105U
CN208923105U CN201821959781.7U CN201821959781U CN208923105U CN 208923105 U CN208923105 U CN 208923105U CN 201821959781 U CN201821959781 U CN 201821959781U CN 208923105 U CN208923105 U CN 208923105U
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chip
heat dissipation
bonding pad
dissipation bonding
type semiconductor
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马磊
党鹏
杨光
彭小虎
王新刚
庞朋涛
任斌
王妙妙
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Xi'an Hangsi Semiconductor Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features

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Abstract

本实用新型公开一种表面贴装式半导体器件,包括位于环氧绝缘体中的散热焊盘、芯片和导电焊盘,所述导电焊盘和芯片通过一引线连接,所述散热焊盘的中央区开有供芯片嵌入的沉槽,所述散热焊盘上开有连通沉槽的卡槽,所述卡槽中设有抵紧于芯片侧壁的弹片,所述沉槽槽壁与芯片之间设有导热绝缘弹性层;所述散热焊盘远离芯片的一侧开有分隔槽,所述分隔槽将散热焊盘远离芯片的一侧等分分隔形成至少2块焊盘单体,所述分隔槽中填充有导热绝缘条。本实用新型通过沉槽中设置的导热绝缘弹性层和卡槽中弹片的配合,方便工作人员拆卸、组装芯片和散热焊盘,避免出现废品;同时,通过分隔槽和导热绝缘条的设置,减小锡膏使用量、降低发生短路的概率。

Description

表面贴装式半导体器件
技术领域
本实用新型涉及表面贴装式半导体器件,属于无引脚封装技术领域。
背景技术
在半导体生产过程中,集成电路封装(IC package)是重要步骤之一,用以保护IC芯片并提供外部电性连接。
集成电路的封装型态的种类繁多,其中相当常见的一种封装型态是先提供散热焊盘,接着,将芯片贴附在芯片座上,以及通过引线线电性连接***之导电焊盘。接着,利用封胶材料包覆芯片、散热焊盘、以及导电焊盘的一部分上,并至少填满芯片与导线附近的空间,完成芯片之封装,封装完成后的芯片可透过导电焊盘而与外界组件电性连接。
然而,现有芯片是利用银浆来粘接于散热焊盘上,并需通过烘烤步骤来固化银浆,以固定芯片于散热焊盘上,因而具有银浆的使用成本,且耗费时间和人力,且一旦固化后,芯片即难以拆离散热焊盘,当发生芯片故障等问题时,只能报废芯片及散热焊盘。
实用新型内容
本实用新型的目的是提供表面贴装式半导体器件,通过沉槽中设置的导热绝缘弹性层和卡槽中弹片的配合,实现芯片在沉槽中的可拆卸式嵌合,方便工作人员拆卸、组装芯片和散热焊盘,避免出现废品;同时,通过分隔槽和导热绝缘条的设置,不仅能够减小锡膏使用量,降低发生短路的概率,还能保证散热焊盘的散热效果不受影响。
为达到上述目的,本实用新型采用的技术方案是:表面贴装式半导体器件,包括位于环氧绝缘体中的散热焊盘、芯片和导电焊盘,所述芯片位于散热焊盘上,位于散热焊盘周边设有若干个导电焊盘,所述导电焊盘和芯片通过一引线连接,所述散热焊盘的中央区开有供芯片嵌入的沉槽,所述散热焊盘上开有连通沉槽的卡槽,所述卡槽中设有抵紧于芯片侧壁的弹片,所述沉槽槽壁与芯片之间设有导热绝缘弹性层;所述散热焊盘远离芯片的一侧开有分隔槽,所述分隔槽宽度为0.1-0.3mm,所述分隔槽将散热焊盘远离芯片的一侧等分分隔形成至少2块焊盘单体,所述分隔槽中填充有导热绝缘条。
上述技术方案中进一步改进的方案如下:
1. 上述方案中,所述沉槽深度不大于芯片厚度。
2. 上述方案中,所述芯片侧壁上开有环形槽,所述导热绝缘弹性层上设有卡接于环形槽中的环形凸起部。
3. 上述方案中,所述弹片上至少开有一个贯通孔。
4. 上述方案中,所述导热绝缘条厚度小于分隔槽槽深。
5. 上述方案中,所述焊盘单体的面积不小于0.3*0.3mm2。
6. 上述方案中,所述导电焊盘和散热焊盘的间距为0.3mm。
7. 上述方案中,所述导电焊盘为T型块。
由于上述技术方案的运用,本实用新型与现有技术相比具有下列优点:
1、本实用新型表面贴装式半导体器件,通过在散热焊盘的中央区开设上沉槽,并在沉槽槽壁上设置上导热绝缘弹性层,同时,在沉槽的一侧开通具有弹片的卡槽,在将芯片安装进沉槽时,芯片挤压弹片压缩,从而使芯片能够嵌入沉槽中,此时,弹片具有回弹趋势,推动芯片向远离弹片的一侧位移,配合导热绝缘弹性层夹紧芯片,即能实现芯片的固定,且能方便工作人员拆卸重组,以降低报废率,十分方便;另外,导热绝缘弹性层还能填充沉槽槽壁与芯片之间的缝隙,以保证芯片与散热焊盘之间的热传导效率;同时,在远离芯片一侧的散热焊盘表面上开设分隔槽,通过不同形状的分隔槽将散热焊盘远离芯片的一部分等分分割成至少两块焊盘单体,在划分成多个焊盘单体后,焊盘单体远离芯片一侧的表面积小于原散热焊盘远离芯片一侧的表面积,从而减少锡膏的使用量,进而有效控制散热焊盘和导电焊盘之间的短路现象;而在分隔槽中填充设置上导热绝缘条后,分隔槽部分不会填充上导热效果较差的环氧绝缘树脂,以保证散热焊盘部分的散热功能不受影响;另外,随着锡膏使用量的减少,还能降低贴片成本。
2、本实用新型表面贴装式半导体器件,通过在芯片侧壁上开有环形槽,在导热绝缘弹性层上开有与其配合的环形凸起部,待芯片嵌入沉槽后,环形凸起部能够卡入环形槽中,不仅能够精确定位芯片嵌入位置,还能阻止芯片轻易脱离沉槽,稳定芯片位置。
3、本实用新型表面贴装式半导体器件,通过在弹片上开设贯通孔后,在后续环氧绝缘树脂注塑形成环氧绝缘体的过程中,环氧绝缘树脂能够通过贯通孔,填满卡槽,避免环氧绝缘树脂在注塑过程中压动弹片,而影响到芯片的稳定性。
4、本实用新型表面贴装式半导体器件,将导热绝缘条的厚度设置为小于分隔槽槽深,使得导热绝缘条不能充满分隔槽,从而在导热绝缘条远离芯片的一侧预留部分空间,此时,在进行贴片操作时,多余的部分锡膏能够进入分隔槽中,从而避免多余的锡膏向散热焊盘四周蔓延,而接触到导电焊盘,引起短路。
附图说明
附图1为本实用新型实施例1的表面贴装式半导体器件的结构示意图;
附图2为图1中A部分的放大图;
附图3为图1中B部分的放大图;
附图4为本实用新型实施例2的表面贴装式半导体器件的结构示意图;
附图5为图4中C部分的放大图。
以上附图中:1、散热焊盘;11、沉槽;12、卡槽;13、弹片;131、贯通孔;14、环形槽;15、分隔槽;151、导热绝缘条;16、焊盘单体;2、导热绝缘弹性层;21、环形凸起部;3、芯片;4、导电焊盘;5、引线;6、环氧绝缘体。
具体实施方式
实施例1:表面贴装式半导体器件,参照附图1-3,包括位于环氧绝缘体6中的散热焊盘1、芯片3和导电焊盘4,所述芯片3位于散热焊盘1上,位于散热焊盘1周边设有若干个导电焊盘4,所述导电焊盘4和芯片3通过一引线5连接,所述散热焊盘1的中央区开有供芯片3嵌入的沉槽11,所述散热焊盘1上开有连通沉槽11的卡槽12,所述卡槽12中设有抵紧于芯片3侧壁的弹片13,所述沉槽11槽壁与芯片3之间设有导热绝缘弹性层2;所述散热焊盘1远离芯片3的一侧开有分隔槽15,所述分隔槽15宽度为0.1-0.3mm,所述分隔槽15将散热焊盘1远离芯片3的一侧等分分隔形成至少2块焊盘单体16,所述分隔槽15中填充有导热绝缘条151。
上述沉槽11深度不大于芯片3厚度;上述芯片3侧壁上开有环形槽14,上述导热绝缘弹性层2上设有卡接于环形槽14中的环形凸起部21;上述弹片13上至少开有一个贯通孔131。
上述导热绝缘条151厚度小于分隔槽15槽深;
上述焊盘单体16的面积不小于0.3*0.3mm2,优选为0.3*0.3mm2
上述导电焊盘4和散热焊盘1的间距为0.3mm;上述导电焊盘4为T型块。
实施例2:表面贴装式半导体器件,参照附图4-5,包括位于环氧绝缘体6中的散热焊盘1、芯片3和导电焊盘4,所述芯片3位于散热焊盘1上,位于散热焊盘1周边设有若干个导电焊盘4,所述导电焊盘4和芯片3通过一引线5连接,所述散热焊盘1的中央区开有供芯片3嵌入的沉槽11,所述散热焊盘1上开有连通沉槽11的卡槽12,所述卡槽12中设有抵紧于芯片3侧壁的弹片13,所述沉槽11槽壁与芯片3之间设有导热绝缘弹性层2;所述散热焊盘1远离芯片3的一侧开有分隔槽15,所述分隔槽15宽度为0.1-0.3mm,所述分隔槽15将散热焊盘1远离芯片3的一侧等分分隔形成至少2块焊盘单体16,所述分隔槽15中填充有导热绝缘条151。
上述沉槽11深度不大于芯片3厚度;上述弹片13上至少开有一个贯通孔131。
上述导热绝缘条151厚度小于分隔槽15槽深;
上述焊盘单体16的面积不小于0.3*0.3mm2,优选为0.3*0.3mm2
上述导电焊盘4和散热焊盘1的间距为0.3mm。
采用上述组装式QFN结构时,通过沉槽11的开设,不仅能够定位芯片3安装位置,方便工作人员组装芯片3和散热焊盘1,还能利用沉槽11中的导热绝缘弹性层2和卡槽12中的弹片13的挤压配合固定住芯片3位置,从而实现芯片3和散热焊盘1的可拆卸式组装,降低报废率;同时,导热绝缘弹性层2还能利用自身的形变作用消除沉槽11槽壁和芯片3之间的缝隙,保证芯片3和散热焊盘1之间的导热效率;同时,通过分隔槽15的设置,使散热焊盘1远离芯片3的一侧表面等分分隔形成多块焊盘单体16,减少了散热焊盘1部分贴片时与PCB的接触面积,从而减少了锡膏的使用量;随着锡膏使用量的减少,一方面,降低了锡膏从散热焊盘1蔓延到导电焊盘4的概率,有效的控制了焊盘单体16与导电焊盘4之间的短路现象,另一方面,还能降低贴装成本。
另外,在导热绝缘弹性层2和芯片3侧壁上分别设置上相互卡接的环形凸起部21和环形槽14,从而进一步卡住嵌入沉槽11的芯片3,稳定芯片3的安装。
而由于分隔槽11的设置,在注塑封装时,环氧绝缘树脂会填充进分隔槽15中,导致散热焊盘1与PCB的接触导热面积缩小,而影响到其导热效果,因此,通过导热绝缘条111的设置,在保证散热焊盘1导热效果的同时,还能利用预留的分隔槽15部分容纳多余的部分锡膏,进一步降低发生短路的概率,改善贴片质量。
其中,将导电焊盘4设置为T型块时,在利用环氧绝缘树脂塑封时,T型块能够更好的与环氧绝缘体6结合,提高封装质量。
上述实施例只为说明本实用新型的技术构思及特点,其目的在于让熟悉此项技术的人士能够了解本实用新型的内容并据以实施,并不能以此限制本实用新型的保护范围。凡根据本实用新型精神实质所作的等效变化或修饰,都应涵盖在本实用新型的保护范围之内。

Claims (8)

1.一种表面贴装式半导体器件,包括位于环氧绝缘体(6)中的散热焊盘(1)、芯片(3)和导电焊盘(4),所述芯片(3)位于散热焊盘(1)上,位于散热焊盘(1)周边设有若干个导电焊盘(4),所述导电焊盘(4)和芯片(3)通过一引线(5)连接,其特征在于:所述散热焊盘(1)的中央区开有供芯片(3)嵌入的沉槽(11),所述散热焊盘(1)上开有连通沉槽(11)的卡槽(12),所述卡槽(12)中设有抵紧于芯片(3)侧壁的弹片(13),所述沉槽(11)槽壁与芯片(3)之间设有导热绝缘弹性层(2);所述散热焊盘(1)远离芯片(3)的一侧开有分隔槽(15),所述分隔槽(15)宽度为0.1-0.3mm,所述分隔槽(15)将散热焊盘(1)远离芯片(3)的一侧等分分隔形成至少2块焊盘单体(16),所述分隔槽(15)中填充有导热绝缘条(151)。
2.根据权利要求1所述的表面贴装式半导体器件,其特征在于:所述沉槽(11)深度不大于芯片(3)厚度。
3.根据权利要求1所述的表面贴装式半导体器件,其特征在于:所述芯片(3)侧壁上开有环形槽(14),所述导热绝缘弹性层(2)上设有卡接于环形槽(14)中的环形凸起部(21)。
4.根据权利要求1所述的表面贴装式半导体器件,其特征在于:所述弹片(13)上至少开有一个贯通孔(131)。
5.根据权利要求1所述的表面贴装式半导体器件,其特征在于:所述导热绝缘条(151)厚度小于分隔槽(15)槽深。
6.根据权利要求1所述的表面贴装式半导体器件,其特征在于:所述焊盘单体(16)的面积不小于0.3*0.3mm2
7.根据权利要求6所述的表面贴装式半导体器件,其特征在于:所述导电焊盘(4)和散热焊盘(1)的间距为0.3mm。
8.根据权利要求1所述的表面贴装式半导体器件,其特征在于:所述导电焊盘(4)为T型块。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110379784A (zh) * 2019-07-23 2019-10-25 王欣 一种半导体封装结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110379784A (zh) * 2019-07-23 2019-10-25 王欣 一种半导体封装结构

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