CN208970506U - 防短路的qfn封装结构 - Google Patents

防短路的qfn封装结构 Download PDF

Info

Publication number
CN208970506U
CN208970506U CN201821959783.6U CN201821959783U CN208970506U CN 208970506 U CN208970506 U CN 208970506U CN 201821959783 U CN201821959783 U CN 201821959783U CN 208970506 U CN208970506 U CN 208970506U
Authority
CN
China
Prior art keywords
heat dissipation
bonding pad
chip
dissipation bonding
separation trough
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201821959783.6U
Other languages
English (en)
Inventor
马磊
党鹏
杨光
彭小虎
王新刚
庞朋涛
任斌
王妙妙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xi'an Hangsi Semiconductor Co Ltd
Original Assignee
Xi'an Hangsi Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xi'an Hangsi Semiconductor Co Ltd filed Critical Xi'an Hangsi Semiconductor Co Ltd
Priority to CN201821959783.6U priority Critical patent/CN208970506U/zh
Application granted granted Critical
Publication of CN208970506U publication Critical patent/CN208970506U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本实用新型公开一种防短路QFN封装结构,包括位于环氧绝缘体中的散热焊盘、芯片和导电焊盘,所述芯片与散热焊盘之间设有银浆层,所述导电焊盘和芯片通过一引线连接,所述散热焊盘远离芯片的一侧开有分隔槽,所述分隔槽宽度为0.1‑0.3mm,所述分隔槽将散热焊盘远离芯片的一侧等分分隔形成至少2块焊盘单体,所述分隔槽中填充有导热绝缘条,所述分隔槽槽壁上开有若干个延伸至散热焊盘内的T形槽,所述导热绝缘条上设有填充于T形槽中的T形部。本实用新型通过分隔槽和导热绝缘条的设置,能够减小锡膏使用量,降低发生短路的概率,而通过T形槽和T形部的卡接配合,能够改善导热绝缘条与散热焊盘的连接质量,提高封装结构的使用性能。

Description

防短路的QFN封装结构
技术领域
本实用新型涉及一种防短路QFN封装结构,属于无引脚封装技术领域。
背景技术
QFN封装在PCB板中应用很广,QFN封装的应用极大的推动了电子技术的发展。QFN封装具有优异的热性能,主要是因为封装底部有大面积散热焊,为了能有效地将热量从芯片传导到PCB上,PCB底部必须设计与之相对应的散热焊盘以及散热过孔,散热焊盘提供了可靠的焊接面积,散热过孔提供了散热途径;常规的QFN封装在PCB中的设计通常有一个大面积的散热焊盘,这个散热焊盘通常接地,虽然这个散热焊盘可以起到芯片散热的作用,但往往由于焊盘过大,在贴片(SMT)过程中刷锡过多会导致这个QFN封装中央大的散热焊盘与其他的小的导电焊盘的短路现象。
实用新型内容
本实用新型的目的是提供一种防短路QFN封装结构,通过分隔槽和导热绝缘条的设置,不仅能够减小锡膏使用量,降低发生短路的概率,还能保证散热焊盘的散热效果不受影响;同时,通过分隔槽处T形槽及T形部的卡接配合,能够提高导热绝缘条和散热焊盘的连接效果,避免导热绝缘条脱离散热焊盘。
为达到上述目的,本实用新型采用的技术方案是:一种防短路QFN封装结构,包括位于环氧绝缘体中的散热焊盘、芯片和导电焊盘,所述芯片位于散热焊盘上,且所述芯片与散热焊盘之间设有银浆层,位于散热焊盘周边设有若干个导电焊盘,所述导电焊盘和芯片通过一引线连接,所述散热焊盘远离芯片的一侧开有分隔槽,所述分隔槽宽度为0.1-0.3mm,所述分隔槽将散热焊盘远离芯片的一侧等分分隔形成至少2块焊盘单体,所述分隔槽中填充有导热绝缘条,所述分隔槽槽壁上开有若干个延伸至散热焊盘内的T形槽,所述导热绝缘条上设有填充于T形槽中的T形部。
上述技术方案中进一步改进的方案如下:
1. 上述方案中,所述导热绝缘条厚度小于分隔槽槽深。
2. 上述方案中,所述焊盘单体的面积不小于0.3*0.3mm2
3. 上述方案中,所述导电焊盘和散热焊盘的间距为0.3mm。
4. 上述方案中,所述导电焊盘为T型块。
由于上述技术方案的运用,本实用新型与现有技术相比具有下列优点:
1、本实用新型防短路QFN封装结构,在远离芯片一侧的散热焊盘表面上开设分隔槽,通过不同形状的分隔槽将散热焊盘远离芯片的一部分等分分割成至少两块焊盘单体,在划分成多个焊盘单体后,焊盘单体远离芯片一侧的表面积小于原散热焊盘远离芯片一侧的表面积,从而减少锡膏的使用量,进而有效控制散热焊盘和导电焊盘之间的短路现象;同时,在分隔槽中填充设置上导热绝缘条后,分隔槽部分不会填充上导热效果较差的环氧绝缘树脂,以保证散热焊盘部分的散热功能不受影响,且随着锡膏使用量的减少,还能降低贴片成本;另外,导热绝缘条在通过注塑的方式填充进分隔槽中时,部分树脂能够进入T形槽中,形成T形部,从而利用T形部与T形槽的卡接稳固住导热绝缘条位置,避免由于注塑质量问题或外力作用导致导热绝缘条脱离分隔槽而影响到其使用。
2、本实用新型防短路QFN封装结构,将导热绝缘条的厚度设置为小于分隔槽槽深,使得导热绝缘条不能充满分隔槽,从而在导热绝缘条远离芯片的一侧预留部分空间,此时,在进行贴片操作时,多余的部分锡膏能够进入分隔槽中,从而避免多余的锡膏向散热焊盘四周蔓延,而接触到导电焊盘,引起短路。
附图说明
附图1为本实用新型实施例1的一种防短路QFN封装结构的结构示意图;
附图2为附图1A部分的放大图;
附图3为本实用新型实施例2的一种防短路QFN封装结构的结构示意图;
附图4为附图3B部分的放大图。
以上附图中:1、散热焊盘;11、分隔槽;111、T形槽;12、导热绝缘条;121、T形部;13、焊盘单体;2、银浆层;3、芯片;4、导电焊盘;5、引线;6、环氧绝缘体。
具体实施方式
实施例1:一种防短路QFN封装结构,参照附图1-2,包括位于环氧绝缘体6中的散热焊盘1、芯片3和导电焊盘4,所述芯片3位于散热焊盘1上,且所述芯片3与散热焊盘1之间设有银浆层2,位于散热焊盘1周边设有若干个导电焊盘4,所述导电焊盘4和芯片3通过一引线5连接,所述散热焊盘1远离芯片3的一侧开有分隔槽11,所述分隔槽11宽度为0.1-0.3mm,优选为0.2mm,所述分隔槽11将散热焊盘1远离芯片3的一侧等分分隔形成至少2块焊盘单体13,所述分隔槽11中填充有导热绝缘条12,所述分隔槽11槽壁上开有若干个延伸至散热焊盘1内的T形槽111,所述导热绝缘条12上设有填充于T形槽111中的T形部121。
上述导热绝缘条12厚度小于分隔槽11槽深;
上述焊盘单体13的面积不小于0.3*0.3mm2,优选为0.3*0.3mm2;上述导电焊盘4和散热焊盘1的间距为0.3mm;
上述导电焊盘4为T型块。
实施例2:一种防短路QFN封装结构,参照附图3-4,包括位于环氧绝缘体6中的散热焊盘1、芯片3和导电焊盘4,所述芯片3位于散热焊盘1上,且所述芯片3与散热焊盘1之间设有银浆层2,位于散热焊盘1周边设有若干个导电焊盘4,所述导电焊盘4和芯片3通过一引线5连接,所述散热焊盘1远离芯片3的一侧开有分隔槽11,所述分隔槽11宽度为0.1-0.3mm,优选为0.2mm,所述分隔槽11将散热焊盘1远离芯片3的一侧等分分隔形成至少2块焊盘单体13,所述分隔槽11中填充有导热绝缘条12,所述分隔槽11槽壁上开有若干个延伸至散热焊盘1内的T形槽111,所述导热绝缘条12上设有填充于T形槽111中的T形部121。
上述导热绝缘条12厚度小于分隔槽11槽深;
上述焊盘单体13的面积不小于0.3*0.3mm2,优选为0.3*0.3mm2
上述导电焊盘4和散热焊盘1的间距为0.3mm。
采用上述防短路QFN封装结构时,其通过分隔槽11的设置,使散热焊盘1远离芯片3的一侧表面等分分隔形成多块焊盘单体13,减少了散热焊盘1部分贴片时与PCB的接触面积,从而减少了锡膏的使用量;随着锡膏使用量的减少,一方面,降低了锡膏从散热焊盘1蔓延到导电焊盘4的概率,有效的控制了焊盘单体13与导电焊盘4之间的短路现象,另一方面,还能降低贴装成本;同时,T形部121和T形槽111的卡接配合能够提高导热绝缘条12与散热焊盘1的连接质量,保证导热绝缘条12的正常使用。
另外,由于分隔槽11的设置,在注塑封装时,环氧绝缘树脂会填充进分隔槽11中,导致散热焊盘1与PCB的接触导热面积缩小,而影响到其导热效果,因此,通过导热绝缘条12的设置,在保证散热焊盘1导热效果的同时,还能利用预留的分隔槽11部分容纳多余的部分锡膏,进一步降低发生短路的概率,改善贴片质量。
其中,将导电焊盘4设置为T型块时,在利用环氧绝缘树脂塑封时,T型块能够更好的与环氧绝缘体6结合,提高封装质量。
上述实施例只为说明本实用新型的技术构思及特点,其目的在于让熟悉此项技术的人士能够了解本实用新型的内容并据以实施,并不能以此限制本实用新型的保护范围。凡根据本实用新型精神实质所作的等效变化或修饰,都应涵盖在本实用新型的保护范围之内。

Claims (5)

1.一种防短路的QFN封装结构,包括位于环氧绝缘体(6)中的散热焊盘(1)、芯片(3)和导电焊盘(4),所述芯片(3)位于散热焊盘(1)上,且所述芯片(3)与散热焊盘(1)之间设有银浆层(2),位于散热焊盘(1)周边设有若干个导电焊盘(4),所述导电焊盘(4)和芯片(3)通过一引线(5)连接,其特征在于:所述散热焊盘(1)远离芯片(3)的一侧开有分隔槽(11),所述分隔槽(11)宽度为0.1-0.3mm,所述分隔槽(11)将散热焊盘(1)远离芯片(3)的一侧等分分隔形成至少2块焊盘单体(13),所述分隔槽(11)中填充有导热绝缘条(12),所述分隔槽(11)槽壁上开有若干个延伸至散热焊盘(1)内的T形槽(111),所述导热绝缘条(12)上设有填充于T形槽(111)中的T形部(121)。
2.根据权利要求1所述的一种防短路的QFN封装结构,其特征在于:所述导热绝缘条(12)厚度小于分隔槽(11)槽深。
3.根据权利要求1所述的一种防短路的QFN封装结构,其特征在于:所述焊盘单体(13)的面积不小于0.3*0.3mm2
4.根据权利要求3所述的一种防短路的QFN封装结构,其特征在于:所述导电焊盘(4)和散热焊盘(1)的间距为0.3mm。
5.根据权利要求1所述的一种防短路的QFN封装结构,其特征在于:所述导电焊盘(4)为T型块。
CN201821959783.6U 2018-11-27 2018-11-27 防短路的qfn封装结构 Active CN208970506U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201821959783.6U CN208970506U (zh) 2018-11-27 2018-11-27 防短路的qfn封装结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201821959783.6U CN208970506U (zh) 2018-11-27 2018-11-27 防短路的qfn封装结构

Publications (1)

Publication Number Publication Date
CN208970506U true CN208970506U (zh) 2019-06-11

Family

ID=66765802

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201821959783.6U Active CN208970506U (zh) 2018-11-27 2018-11-27 防短路的qfn封装结构

Country Status (1)

Country Link
CN (1) CN208970506U (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113451250A (zh) * 2021-06-23 2021-09-28 江苏盐芯微电子有限公司 一种qfn封装框架结构

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113451250A (zh) * 2021-06-23 2021-09-28 江苏盐芯微电子有限公司 一种qfn封装框架结构
CN113451250B (zh) * 2021-06-23 2022-07-12 江苏盐芯微电子有限公司 一种qfn封装框架结构

Similar Documents

Publication Publication Date Title
US9673138B2 (en) Semiconductor package structure having a heat sink frame connected to a lead frame
CN204102862U (zh) 一种基于腔体技术多芯片叠加封装装置
US7911067B2 (en) Semiconductor package system with die support pad
WO2017041689A1 (zh) 传感芯片封装组件和具有该传感芯片封装组件的电子设备
US8368192B1 (en) Multi-chip memory package with a small substrate
CN102194768A (zh) 基底、封装基底、半导体封装件及其制造方法
US20070170554A1 (en) Integrated circuit package system with multiple molding
CN208970506U (zh) 防短路的qfn封装结构
US7968371B2 (en) Semiconductor package system with cavity substrate
CN101114624A (zh) 散热型半导体封装件及其散热结构
US20150187683A1 (en) Qfn package and method for forming qfn package
CN208923108U (zh) Smt用防短路dfn器件封装结构
CN208923104U (zh) 基于qfn的芯片封装结构
CN208923105U (zh) 表面贴装式半导体器件
TW201308548A (zh) 小基板多晶片記憶體封裝構造
CN212625542U (zh) 一种daf膜封装结构
CN203826369U (zh) 一种半导体引线框架
CN110648991B (zh) 一种用于框架封装芯片的转接板键合结构及其加工方法
CN109904125A (zh) 耐高温qfn封装结构的制备方法
CN204732390U (zh) 载板级半导体芯片嵌入式封装结构
US20050184365A1 (en) High density lead arrangement package structure
CN206532770U (zh) 芯片封装的新型sop结构
CN105932017A (zh) 一种超薄3d封装的半导体器件、其加工方法以及加工方法中的半成品
CN205282466U (zh) 一种立方半导体封装
CN204348705U (zh) 一种高可靠性低成本的半导体芯片封装体

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant