CN202395750U - Differential reference voltage buffer - Google Patents
Differential reference voltage buffer Download PDFInfo
- Publication number
- CN202395750U CN202395750U CN2011204985964U CN201120498596U CN202395750U CN 202395750 U CN202395750 U CN 202395750U CN 2011204985964 U CN2011204985964 U CN 2011204985964U CN 201120498596 U CN201120498596 U CN 201120498596U CN 202395750 U CN202395750 U CN 202395750U
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- China
- Prior art keywords
- transistor
- common mode
- feedback circuit
- mode feedback
- reference voltage
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Abstract
The utility model provides a differential reference voltage buffer comprising a control part, a copy buffering part, and a main buffering part connected in series between the control part and the copy buffering part, wherein the control part comprises a fully differential operational amplifier and a common-mode feedback circuit; the output end of the common-mode feedback circuit is connected to the common-mode feedback input end of the fully differential operational amplifier; the main buffering part comprises first and second transistors sharing a bias current; the output end of the fully differential operational amplifier is connected to the gates of the first and second transistors; the sources of the first and second transistors are connected to the input end of the common-mode feedback circuit; the copy buffering part comprises fourth and fifth transistors sharing a biasing current; the gates of the fourth and fifth transistors are connected to the gates of the first and second transistors, respectively; and the sources of the fourth and fifth transistors output reference voltages, respectively. The differential reference voltage buffer provided in the utility model is high in response speed, low noise and power consumption, and capable of improving the performance and accuracy of a data converter.
Description
Technical field
The utility model relates to integrated circuit fields, is specifically related to a kind of differential reference voltage buffer.
Background technology
Reference voltage (Voltage Reference) typically refers to the voltage of the high stability that in circuit, is used as voltage reference, is also referred to as reference voltage.In many integrated circuits and circuit unit,, all need precision and the stable benchmark voltage source like digital to analog converter (DAC), analog to digital converter (ADC), linear voltage regulator and switching regulator.Desirable reference voltage source does not receive power supply and Influence of Temperature, in circuit, stable voltage can be provided.
In data converting circuit, reference voltage has very high requirement as the benchmark of data-measuring to its speed and precision.Yet in the data converter of high-speed, high precision, because a large amount of uses of switched-capacitor circuit all will have very big voltage fluctuation on reference voltage and the power line, this has had a strong impact on the performance and the precision of whole data converter.
How to guarantee reference voltage quickly recover to stable level after to capacitor charge and discharge, insensitive and consume the least possible energy and become whole data converter key for design to little voltage disturbance.
The utility model content
The purpose of the utility model is to provide that a kind of response speed is fast, the differential reference voltage buffer of low noise and low-power consumption.
To achieve these goals, the utility model provides a kind of differential reference voltage buffer, comprises control section, host buffer part and duplicates buffer portion, and said host buffer partly is serially connected with control section and duplicates between the buffer portion, wherein:
Said control section comprises fully differential operational amplifier and common mode feedback circuit, and the output of said common mode feedback circuit is connected to the common-mode feedback input of said fully differential operational amplifier;
Said host buffer partly comprises the first transistor and the transistor seconds of series connection; Shared one road bias current of said the first transistor and transistor seconds; The positive-negative output end of said fully differential operational amplifier is connected to the grid of said the first transistor and transistor seconds respectively, and the source electrode of said the first transistor and transistor seconds is connected to the input of said common mode feedback circuit;
Saidly duplicate the 4th transistor and the 5th transistor that buffer portion comprises series connection; Shared one road bias current of said the 4th transistor and the 5th transistor; Said the 4th transistor and the 5th transistorized grid are connected to the grid of said the first transistor and transistor seconds respectively, and said the 4th transistor and the 5th transistorized source electrode are exported positive and negative two reference voltages respectively.
As preferably, the source electrode that the positive-negative input end of said fully differential operational amplifier is used for respectively receiving input reference voltage and being connected to said the first transistor and transistor seconds through third and fourth resistance respectively through first and second resistance is with the formation negative feedback.
As preferably; Said common mode feedback circuit has positive and negative two inputs, a common mode electrical level input; Said common mode electrical level input is in order to receiving the common-mode voltage of outside input, and said common mode feedback circuit forces first voltage that the source electrode of said the first transistor and the transistor seconds of said host buffer part exports and the average of second voltage to equal said common-mode voltage.
As preferably; Said common mode feedback circuit comprises operational amplifier and the 5th resistance and the 6th resistance that are connected respectively to the positive input terminal of said operational amplifier; The other end of said the 5th resistance and the 6th resistance is respectively the positive-negative input end of said common mode feedback circuit; The negative input end of said operational amplifier is the common mode electrical level input of said common mode feedback circuit, and the output of said operational amplifier is the output of said common mode feedback circuit.
As preferably; Said common mode feedback circuit comprises first differential pair that is made up of the 7th transistor and the 8th transistor and second differential pair that is made up of the 9th transistor and the tenth transistor; Said the 8th transistor is connected with the 9th transistorized grid and this grid is the common mode electrical level input of common mode feedback circuit; Said the 8th transistor is connected with the 9th transistor drain and is connected to the 11 transistor drain; The said the 11 transistorized grid is connected to drain electrode and is the output of common mode feedback circuit, and said the 7th transistor and the tenth transistorized grid are respectively the positive-negative input end of said common mode feedback circuit.
As preferably, said host buffer part comprises that also the 3rd transistor, said the first transistor are connected between power supply and the transistor seconds, and the 3rd transistor is connected between transistor seconds and the ground.
As preferably, said host buffer part comprises also that decoupling capacitor, said decoupling capacitor are connected between the grid of power supply and the first transistor respectively, between the grid of the first transistor and transistor seconds and between transistor seconds and the ground.
As preferably, the first transistor and shared one road bias current of transistor seconds in the said host buffer part, and all adopt the nmos pass transistor realization.
As preferably, the said buffer portion that duplicates also comprises the 6th transistor, and said the 4th transistor is connected between power supply and the 5th transistor, and the 6th transistor is connected between the 5th transistor and the ground.
As preferably, said the 4th transistor and shared one road bias current of the 5th transistor that duplicates in the buffer portion, and all adopt nmos pass transistor to realize.
In the differential reference voltage buffer of the utility model, control section and host buffer part are according to the input voltage size and preferably produce two bias voltages through negative feedback, and this bias voltage is delivered to behind the big capacitor decoupling of preferred use and duplicated buffer portion.Duplicate buffer portion and utilize two reference voltages of this bias voltage output.Because duplicating buffer portion has been open loop circuit, therefore have response speed and stronger capacitance drive capability faster.Each buffer portion all comprises two source followers, and its shared one road bias current, thereby has saved the power consumption expense greatly.
Description of drawings
Accompanying drawing 4 is the circuit diagram of another embodiment of the common mode feedback circuit 11 in the control section;
Embodiment
Be elaborated below in conjunction with the preferred embodiment of accompanying drawing to the utility model.
Fig. 1 is the circuit diagram of the differential reference voltage buffer of the utility model, and is as shown in Figure 1, and it comprises control section 1, host buffer part 2 and duplicate buffer portion 3 these three parts that host buffer part 2 is serially connected with control section 1 and duplicates between the buffer portion 3.
Resistance R
1And R
2One terminates to for example gnd and reference voltage Vr, and the other end is connected to the input of fully differential operational amplifier 10 with formation " virtual earth ", thereby the voltage on line 13 and the line 14 satisfies following formula:
Thereby have:
Because two inputs of common mode feedback circuit 11 are received respectively on line 13 and 14, but so on common mode feedback circuit 11 forced lines 13 and the line 14 average of voltage equal outside received on the line 15 and import common mode electrical level V
Cm, therefore have:
V
13+V
14＝2V
cm
Therefore the voltage on line 13 and the line 14 is:
Host buffer partly comprises three nmos pass transistor M
1, M
2And M
3M
1Come the voltage on the output line 13, M as source follower
2As the voltage on the source follower output line 14, M
3Be current source transistor, adopt nmos pass transistor can realize bigger mutual conductance.M
1, M
2Grid end 17 and 16 be connected to control section 1 respectively the positive-negative output end of fully differential operational amplifier 10 to form close loop negative feedback, M
1With M
2The voltage of grid end confirms that by the output of the fully differential operational amplifier 10 of control section 1 its size is:
V
17＝V
13+V
GS1
V
16＝V
14+V
GS2
Can connect one group of decoupling capacitor 20 on line 16 and the line 17, this group electric capacity will reduce the impedance of line 16 and line 17 greatly under high frequency situations, thereby reduce noise.
Two source follower M of host buffer part 2
1And M
2Share M
3The bias current that provides, thus the power consumption expense significantly reduced.
Duplicate buffer portion 3 and comprise three transistor M
4, M
5And M
6M
4Come the reference voltage V on the output line 31 as source follower
Refp, M
5As the negative reference voltage V on the source follower output line 30
Refn, M
6It is current source transistor.Identical with host buffer part 2, M
4And M
5The bias voltage of grid end is brought in by positive and negative two outputs of the fully differential operational amplifier 10 of control section 1 equally and is provided.Yet different with host buffer part 2 is: two reference voltages that duplicate buffer portion 3 outputs do not feed back to the input of the fully differential operational amplifier 10 of control section 1.In other words, duplicate buffer portion 3 and work in open loop situations, thereby have response speed faster.V under the stable state
RefpAnd V
RefnValue be:
V
refp＝V
17-V
GS4＝V
13+V
GS1-V
GS4
V
refn＝V
16+V
GS5＝V
14+V
GS2-V
GS5
When design, the dimension scale of duplicating the buffer portion 3 and the source follower transistor of host buffer part 2 can be identical with the dimension scale of current source transistor, so V
GS1=V
GS4, V
GS2=V
GS5Thereby, two reference voltage V of output
RefpAnd V
RefnValue equate with magnitude of voltage on line 13, the line 14, that is:
In addition on the one hand, duplicate two source follower M of buffer portion 3
4And M
5Share M
6The bias current that provides, thus the power consumption expense significantly reduced.
Fig. 2 is the circuit diagram of an embodiment of the fully differential operational amplifier 10 in the control section 1.This amplifier adopts classical current mirror type structure, and its positive-negative input end is differential pair M '
1, M '
2The grid end.Input voltage is by differential pair M '
1, M '
2Transfer to behind the electric current by current mirror M '
5, M '
6Mirror image output.The common-mode feedback input of this fully differential operational amplifier is the current source transistor M ' of output
7, M '
8The grid end.
Fig. 3 is the circuit diagram of an embodiment of the common mode feedback circuit 11 in the control section 1.
As shown in Figure 3; Common mode feedback circuit 11 comprises operational amplifier 113 and first resistance 110 and second resistance 111 that are connected respectively to the positive input terminal of operational amplifier 113; First resistance 110 is identical with second resistance, 111 values, and the voltage on the center line 13 that its other end will receive control section 1 respectively and the line 14 is also averaged to it and to be delivered to line 112.The negative input end of operational amplifier 113 is the common mode electrical level input of common mode feedback circuit 11, and the output of said operational amplifier 113 is the output of said common mode feedback circuit 11, and operational amplifier 113 is with the common-mode voltage V of the voltage on the line 112 with outside input
CmCompare, and control the common-mode feedback end of fully differential operational amplifier 10 through output.After loop stability, the voltage on the line 112 will and V
CmEquate.
Fig. 4 is the circuit diagram of the another one embodiment of the common mode feedback circuit 11 in the control section 1.
As shown in Figure 4, common mode feedback circuit comprises by the 7th transistor M "
1With the 8th transistor M "
2First difference that constitutes reaches by the 9th transistor M "
3With the tenth transistor M "
4Second differential pair that constitutes, the 8th transistor M "
2With the 9th transistor M "
3Grid be connected and this grid is the common mode electrical level input of common mode feedback circuit 11, the 8th transistor M "
2With the 9th transistor M "
3Drain electrode be connected and be connected to the 11 transistor M "
5Drain electrode, the 11 transistor M "
5Grid be connected to drain electrode and be the output of common mode feedback circuit 11.
The 7th transistor M "
1With the tenth transistor M "
4Grid be respectively the positive-negative input end of common mode feedback circuit 11, M "
1And M "
4With receiving " from the voltage on control section center line 13 and the line 14 and through differential pair M
1, M "
2And M "
3, M "
4To the voltage that receives average and with the common-mode voltage V of outside input
CmControl the common-mode feedback end of fully differential operational amplifier 10 relatively, then through output.After loop stability, the mean value of voltage equals V on line 13 and the line 14
Cm
The above is merely the preferred embodiment of the utility model; The utility model is not limited to above-mentioned particular implementation example; Do not deviating under the utility model spirit and the nature thereof; Skilled personnel can make various corresponding changes and distortion according to the utility model, but these corresponding changes and distortion all should belong within the utility model accompanying claims protection range.
Claims (10)
1. a differential reference voltage buffer is characterized in that, comprising: control section (1), host buffer part (2) with duplicate buffer portion (3), said host buffer partly (2) is serially connected with control section (1) and duplicates between the buffer portion (3), wherein,
Said control section (1) comprises fully differential operational amplifier (10) and common mode feedback circuit (11), and the output of said common mode feedback circuit (11) is connected to the common-mode feedback input of said fully differential operational amplifier (10);
Said host buffer part (2) comprises the first transistor and the transistor seconds of series connection; Shared one road bias current of said the first transistor and transistor seconds; The positive-negative output end of said fully differential operational amplifier (10) is connected to the grid of said the first transistor and transistor seconds respectively, and the source electrode of said the first transistor and transistor seconds is connected to the input of said common mode feedback circuit (11);
Saidly duplicate the 4th transistor and the 5th transistor that buffer portion (3) comprises series connection; Shared one road bias current of said the 4th transistor and the 5th transistor; Said the 4th transistor and the 5th transistorized grid are connected to the grid of said the first transistor and transistor seconds respectively, and said the 4th transistor and the 5th transistorized source electrode are exported positive and negative two reference voltages respectively.
2. differential reference voltage buffer as claimed in claim 1; It is characterized in that the source electrode that the positive-negative input end of said fully differential operational amplifier (10) is used for respectively receiving input reference voltage and being connected to said the first transistor and transistor seconds through third and fourth resistance respectively through first and second resistance is with the formation negative feedback.
3. differential reference voltage buffer as claimed in claim 1; It is characterized in that; Said common mode feedback circuit (11) has positive and negative two inputs, a common mode electrical level input; Said common mode electrical level input is in order to receive the common-mode voltage of outside input, and the said the first transistor of the said host buffer part of said common mode feedback circuit (11) pressure and first voltage of the source electrode output of transistor seconds and the average of second voltage equal said common-mode voltage.
4. differential reference voltage buffer as claimed in claim 3; It is characterized in that; Said common mode feedback circuit (11) comprises operational amplifier (113) and is connected respectively to the 5th resistance and the 6th resistance of the positive input terminal of said operational amplifier (113); The other end of said the 5th resistance and the 6th resistance is respectively the positive-negative input end of said common mode feedback circuit (11); The negative input end of said operational amplifier (113) is the common mode electrical level input of said common mode feedback circuit (11), and the output of said operational amplifier (113) is the output of said common mode feedback circuit (11).
5. differential reference voltage buffer as claimed in claim 3; It is characterized in that; Said common mode feedback circuit (11) comprises first differential pair that is made up of the 7th transistor and the 8th transistor and second differential pair that is made up of the 9th transistor and the tenth transistor; Said the 8th transistor is connected with the 9th transistorized grid and this grid is the common mode electrical level input of common mode feedback circuit (11); Said the 8th transistor is connected with the 9th transistor drain and is connected to the 11 transistor drain; The said the 11 transistorized grid is connected to drain electrode and is the output of common mode feedback circuit (11), and said the 7th transistor and the tenth transistorized grid are respectively the positive-negative input end of said common mode feedback circuit (11).
6. differential reference voltage buffer as claimed in claim 1 is characterized in that, said host buffer part (2) also comprises the 3rd transistor, and said the first transistor is connected between power supply and the transistor seconds, and the 3rd transistor is connected between transistor seconds and the ground.
7. differential reference voltage buffer as claimed in claim 1; It is characterized in that; Said host buffer part (2) also comprises decoupling capacitor (20), and said decoupling capacitor is connected between the grid of power supply and the first transistor respectively, between the grid of the first transistor and transistor seconds and between transistor seconds and the ground.
8. differential reference voltage buffer as claimed in claim 1 is characterized in that, the first transistor and shared one road bias current of transistor seconds in the said host buffer part (2), and all adopt nmos pass transistor to realize.
9. differential reference voltage buffer as claimed in claim 1; It is characterized in that; The said buffer portion (3) that duplicates also comprises the 6th transistor, and said the 4th transistor is connected between power supply and the 5th transistor, and the 6th transistor is connected between the 5th transistor and the ground.
10. differential reference voltage buffer as claimed in claim 1 is characterized in that, said the 4th transistor and shared one road bias current of the 5th transistor that duplicates in the buffer portion (3), and all adopt nmos pass transistor to realize.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204985964U CN202395750U (en) | 2011-12-02 | 2011-12-02 | Differential reference voltage buffer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204985964U CN202395750U (en) | 2011-12-02 | 2011-12-02 | Differential reference voltage buffer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202395750U true CN202395750U (en) | 2012-08-22 |
Family
ID=46670649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011204985964U Withdrawn - After Issue CN202395750U (en) | 2011-12-02 | 2011-12-02 | Differential reference voltage buffer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202395750U (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102412824A (en) * | 2011-12-02 | 2012-04-11 | 上海贝岭股份有限公司 | Differential reference voltage buffer |
| CN103716049A (en) * | 2013-12-30 | 2014-04-09 | 上海贝岭股份有限公司 | Bias-current generating circuit |
| CN103825598A (en) * | 2012-11-19 | 2014-05-28 | 飞思卡尔半导体公司 | Inter-rail difference buffer input stage |
| CN104702268A (en) * | 2015-02-04 | 2015-06-10 | 芯原微电子(上海)有限公司 | Voltage buffer circuit and circuit including voltage buffer circuit to be used for driving loads to be switched along with time sequence |
| CN106292818A (en) * | 2016-08-24 | 2017-01-04 | 西安电子科技大学 | Be suitable to fully differential generating circuit from reference voltage and the Wireless Telecom Equipment of pipeline ADC |
| CN106656161A (en) * | 2016-12-08 | 2017-05-10 | 中国电子科技集团公司第五十八研究所 | Rail-to-rail self-adaptive quick response buffer circuit |
| CN115291662A (en) * | 2022-08-02 | 2022-11-04 | 西安交通大学 | Threshold voltage generation circuit with adjustable range |
-
2011
- 2011-12-02 CN CN2011204985964U patent/CN202395750U/en not_active Withdrawn - After Issue
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102412824A (en) * | 2011-12-02 | 2012-04-11 | 上海贝岭股份有限公司 | Differential reference voltage buffer |
| CN102412824B (en) * | 2011-12-02 | 2014-01-15 | 上海贝岭股份有限公司 | Differential reference voltage buffer |
| CN103825598B (en) * | 2012-11-19 | 2018-11-13 | 恩智浦美国有限公司 | Differential buffers input stage between rail |
| CN103825598A (en) * | 2012-11-19 | 2014-05-28 | 飞思卡尔半导体公司 | Inter-rail difference buffer input stage |
| CN103716049B (en) * | 2013-12-30 | 2017-10-10 | 上海贝岭股份有限公司 | Bias current generative circuit |
| CN103716049A (en) * | 2013-12-30 | 2014-04-09 | 上海贝岭股份有限公司 | Bias-current generating circuit |
| CN104702268B (en) * | 2015-02-04 | 2017-08-08 | 芯原微电子(上海)有限公司 | The circuit that voltage buffer circuit and driving load with it switch with sequential |
| CN104702268A (en) * | 2015-02-04 | 2015-06-10 | 芯原微电子(上海)有限公司 | Voltage buffer circuit and circuit including voltage buffer circuit to be used for driving loads to be switched along with time sequence |
| CN106292818A (en) * | 2016-08-24 | 2017-01-04 | 西安电子科技大学 | Be suitable to fully differential generating circuit from reference voltage and the Wireless Telecom Equipment of pipeline ADC |
| CN106292818B (en) * | 2016-08-24 | 2017-09-08 | 西安电子科技大学 | Fully differential generating circuit from reference voltage and Wireless Telecom Equipment suitable for pipeline ADC |
| CN106656161A (en) * | 2016-12-08 | 2017-05-10 | 中国电子科技集团公司第五十八研究所 | Rail-to-rail self-adaptive quick response buffer circuit |
| CN115291662A (en) * | 2022-08-02 | 2022-11-04 | 西安交通大学 | Threshold voltage generation circuit with adjustable range |
| CN115291662B (en) * | 2022-08-02 | 2023-07-04 | 西安交通大学 | Threshold voltage generating circuit with adjustable range |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20120822 Effective date of abandoning: 20140115 |
|
| RGAV | Abandon patent right to avoid regrant |