CN106292818A - Be suitable to fully differential generating circuit from reference voltage and the Wireless Telecom Equipment of pipeline ADC - Google Patents
Be suitable to fully differential generating circuit from reference voltage and the Wireless Telecom Equipment of pipeline ADC Download PDFInfo
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- CN106292818A CN106292818A CN201610710476.3A CN201610710476A CN106292818A CN 106292818 A CN106292818 A CN 106292818A CN 201610710476 A CN201610710476 A CN 201610710476A CN 106292818 A CN106292818 A CN 106292818A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
The present invention relates to a kind of fully differential generating circuit from reference voltage being suitable to pipeline ADC and Wireless Telecom Equipment.This fully differential generating circuit from reference voltage 10, including: initial reference voltage input VREF, power end VDD, earth terminal GND, Full differential operational amplifier A1, the first level shifter V1, second electrical level shift unit V2, common mode feedback circuit CMFB, the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6 and the first switching tube M1, second switch pipe M2.The embodiment of the present invention is capable of preferable PSRR, has good stability, and can be quickly established to steady statue.Export the reference voltage of the high amplitude of oscillation simultaneously.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of fully differential reference voltage being suitable to pipeline ADC
Produce circuit and Wireless Telecom Equipment.
Background technology
Along with video and the fast development of wireless communication technology, Wireless Telecom Equipment is to analog-digital converter (Analog-
To-digital converter, be called for short ADC) performance propose more strict requirements.ADC is meeting two-forty high accuracy
In the case of also need to have both good exchange performance and if sampling ability.The ADC i.e. pipeline ADC possessing pipeline organization exists
The aspects such as sampling rate, conversion accuracy, power consumption are capable of the most compromise, have therefore obtained extensively in high-speed, high precision field
Application.
In pipeline ADC, the effect of generating circuit from reference voltage has two: (1) provides in each stage pipeline structure and compares
The threshold voltage of relatively device；(2) multiplication surplus gain (MultiplyingDigital to Analog Converter, letter are provided
Claim MDAC) reference voltage when differing from.Reference voltage needs the biggest driving force and is quickly established to steady statue, thus
Ensure that MDAC quickly sets up.Along with the sample rate of pipeline ADC and improving constantly of precision, the performance of reference voltage is to ADC's
Conversion performance will produce significantly more impact.
Existing generating circuit from reference voltage is frequently with two single end operational amplifier and high speed voltage buffer (buffer)
Realize the output of reference voltage.But the output voltage swing of this structural reference voltage is limited, and it is easily subject to two single-ended fortune
Put the impact of each imbalance, so that output reference voltage glances off.
Accordingly, it would be desirable to a kind of new generating circuit from reference voltage, there is good stability, and can be quickly established to
Steady statue, realizes the high amplitude of oscillation output of reference voltage simultaneously.
Summary of the invention
In order to solve the above-mentioned problems in the prior art, the invention provides and a kind of be suitable to the poorest of pipeline ADC
Divide generating circuit from reference voltage and Wireless Telecom Equipment, it is possible to realize preferable PSRR (Power Supply
Rejection Ratio, is called for short PSRR), there is good stability, and steady statue can be quickly established to.The most defeated
Go out the reference voltage of the high amplitude of oscillation.
An embodiment provides a kind of fully differential generating circuit from reference voltage 10 being suitable to pipeline ADC,
Including: initial reference voltage input VREF, power end VDD, earth terminal GND, Full differential operational amplifier A1, first level move
Position device V1, second electrical level shift unit V2, common mode feedback circuit CMFB, the first resistance R1, the second resistance R2, the 3rd resistance R3, the
Four resistance R4, the 5th resistance R5, the 6th resistance R6 and the first switching tube M1, second switch pipe M2；Wherein, described first switching tube
M1, described 5th resistance R5, described 6th resistance R6 and described second switch pipe M2 are sequentially connected in series in described power end VDD and institute
State between earth terminal GND；
Described first resistance R1 and described second resistance R2 is sequentially connected in series in described earth terminal GND and described first switching tube
Between the node that M1 and described 5th resistance R5 concatenation are formed；Described 3rd resistance R3 and described 4th resistance R4 is sequentially connected in series
In described initial reference voltage input VREFConcatenate with described 6th resistance R6 and described second switch pipe M2 at the node formed
Between；
The positive input terminal Vin+ of described Full differential operational amplifier A1 is electrically connected to described first resistance R1 and described second
At the node A that resistance R2 concatenation is formed, its negative input end Vin-is electrically connected to described 3rd resistance R3 and described 4th resistance R4
At the node B that concatenation is formed, its negative output terminal Vout-and described first level shifter V1 is sequentially connected in series to described first switch
The control end of pipe M1, its positive output end Vout+ and described second electrical level shift unit V2 is sequentially connected in series to described second switch pipe M2
Control end；
The input of described common mode feedback circuit CMFB is electrically connected to described 5th resistance R5 and described 6th resistance R6 string
Connect at the node C of formation and its outfan is electrically connected to described Full differential operational amplifier A1.
In one embodiment of the invention, described first switching tube M1 is NMOS tube, and described second switch pipe M2 is
PMOS.
In one embodiment of the invention, the source of described NMOS tube is connected with the substrate terminal of described NMOS tube；Described
The source of PMOS is connected with the substrate terminal of described PMOS.
In one embodiment of the invention, the 3rd electric capacity C3 and the 4th electric capacity C4 is also included；Described 3rd electric capacity C1's
One end is electrically connected to the control end of described first switching tube M1 and the other end is electrically connected to described earth terminal GND；Described 4th electricity
Hold one end of C4 and be electrically connected to the control end of described second switch pipe M2 and the other end is electrically connected to described earth terminal GND.
In one embodiment of the invention, described Full differential operational amplifier A1 includes: the 3rd switching tube M3, the 4th open
Close pipe M4, the 5th switching tube M5, the 6th switching tube M6, the 7th switching tube M7, the 8th switching tube M8, the 9th switching tube M9, the tenth
Switching tube M10, the 11st switching tube M11, twelvemo close pipe M12, the 13rd switching tube M13, the 14th switching tube M14, the
15 switching tube M15, sixteenmo close pipe M16, the 17th switching tube M17 and eighteenmo closes pipe M18；Wherein, the described 3rd
Switching tube M3, described 4th switching tube M4 and described 8th switching tube M8 are sequentially connected in series in described power end VDD and described ground connection
Between end GND, the control end of described 3rd switching tube M3 is electrically connected to the first bias voltage Vb1, described 4th switching tube M4's
Controlling end and electrically connect described negative input end Vin-, the control end of described 8th switching tube M8 is electrically connected to described 4th switching tube M4
At the node of described 8th switching tube M8 concatenation formation；
Described 5th switching tube M5 and described 9th switching tube M9 is sequentially connected in series in described 3rd switching tube M3 and described
At the node that four switching tube M4 concatenations are formed and between described earth terminal GND, the control end electrical connection of described 5th switching tube M5
Described positive input terminal Vin+, the control end of described 9th switching tube M9 is electrically connected to described 5th switching tube M5 and opens with the described 9th
Close at the node that pipe M9 concatenation is formed；
The transmission ends of described 6th switching tube M6 is electrically connected described 5th switching tube M5 and described 9th switching tube M9
At the node Y that concatenation is formed and earth terminal GND and its control end and be electrically connected to the control end of described 8th switching tube M8；Described
The transmission ends of seven switching tube M7 is electrically connected described 4th switching tube M4 and described 8th switching tube M8 and concatenates the nodes X formed
Place and earth terminal GND and its control end are electrically connected to the control end of described 9th switching tube M9；
Described 17th switching tube M17, described 15th switching tube M15, described 13rd switch M13, the described 11st
Switch M11 and described tenth switching tube M10 is sequentially connected in series between described power end VDD and described earth terminal GND, and the described tenth
The control end of seven switching tube M17 is electrically connected to the control end electrical connection of the second bias voltage Vb2, described 15th switching tube M15
To the 3rd bias voltage Vb3, the control end of described 13rd switching tube M13 is electrically connected to the 4th bias voltage Vb4, and the described tenth
The control end of one switching tube M11 is electrically connected to described 4th switching tube M4 and described 8th switching tube M8 and concatenates the nodes X formed
Place, the end that controls of described tenth switching tube M10 is electrically connected to the input of described common mode feedback circuit CMFB, described negative output terminal
Vout-is electrically connected at the node of described 15th switching tube M15 and described 13rd switch M13 concatenation formation；
Described eighteenmo closes pipe M18, described sixteenmo closes pipe M16, described 14th switch M14 and the described 12nd
Switching tube M12 is sequentially connected in series and concatenates with described 11st switching tube M11 and described tenth switching tube M10 in described power end VDD
Between the node formed, described eighteenmo closes the control end of pipe M18 and electrically connects described second bias voltage Vb2, and described the
Sixteenmo closes the control end electricity of control end the electrical connection described 3rd bias voltage Vb3, described 14th switching tube M14 of pipe M16
Connecting described 4th bias voltage Vb4, described twelvemo is closed pipe M12 and is electrically connected to described 5th switching tube M5 and the described 9th
The node Y place that switching tube M9 concatenation is formed, described positive output end Vout+ is electrically connected to described sixteenmo pass pipe M16 and described
At the node that 14th switch M14 concatenation is formed.
In one embodiment of the invention, described 3rd switching tube M3, described 4th switching tube M4, described 5th switch
Pipe M5, described 15th switching tube M15, described sixteenmo close pipe M16, described 17th switching tube M17 and the described 18th
Switching tube M18 is PMOS, described 6th switching tube M6, described 7th switching tube M7, described 8th switching tube M8, the described 9th
Switching tube M9, described tenth switching tube M10, described 11st switching tube M11, described twelvemo close pipe M12, the described 13rd
Switching tube M13, described 14th switching tube M14 are NMOS tube.
In one embodiment of the invention, described first level shifter V1 includes: the first switch K1, second switch
K2, the 3rd switch K3, the 4th switch K4, the first electric capacity C1, the 5th electric capacity C5 and the first DC source Vbp1；Wherein, described
One switch K1 and described second switch K2 is sequentially connected in series in described first DC source Vbp1 and described Full differential operational amplifier
Between the described negative output terminal Vout-of A1, described 3rd switch K3 and described 4th switch K4 is sequentially connected in series in described power end
Between the control end of VDD and described first switching tube M1；One end of described first electric capacity C1 is electrically connected to described fully differential computing
The described negative output terminal Vout-of amplifier A1 and the other end are electrically connected to the control end of described first switching tube M1, and the described 5th
One end of electric capacity C5 is electrically connected at the node that described first switch K1 and described second switch K2 concatenation is formed and other end electricity
It is connected at the node of described 3rd switch K3 and described 4th switch K4 concatenation formation.
In one embodiment of the invention, described second electrical level shift unit V2 includes: the 5th switch K5, the 6th switch
K6, the 7th switch K7, the 8th switch K8, the second electric capacity C2, the 6th electric capacity C6 and the second DC source Vbn1；Wherein, described
Five switch K5 and described 6th switch K6 are sequentially connected in series in described second DC source Vbn1 and described Full differential operational amplifier
Between the described positive output end Vout+ of A1, described 7th switch K7 and described 8th switch K8 is sequentially connected in series in described earth terminal
Between the control end of GND and described second switch pipe M2；One end of described second electric capacity C2 is electrically connected to described fully differential computing
The described positive output end Vout+ of amplifier A1 and the other end are electrically connected to the control end of described second switch pipe M2, and the described 6th
One end of electric capacity C6 is electrically connected at the node of described 5th switch K5 and described 6th switch K6 concatenation formation and other end electricity
It is connected at the node of described 7th switch K7 and described 8th switch K8 concatenation formation.
In one embodiment of the invention, also include: the 19th switching tube M19, the 20th switching tube M20, the 7th electricity
Resistance R7 and the 8th resistance R8；Described 19th switching tube M19, described 7th resistance R7, described 8th resistance R8 and described second
Ten switching tube M20 are sequentially connected in series between described power end VDD and described earth terminal GND, and the described 19th opens the light pipe M19's
Controlling end and be electrically connected to the described first control end opening the light pipe M1, the described 20th control end opening the light pipe M20 is electrically connected to institute
State the node output that the second control end opening the light pipe M2, described 19th switching tube M19 and described 7th resistance R7 concatenation are formed
Reference voltage high level HVREF, the node that described 8th resistance R8 and described 20th switching tube M20 concatenation are formed exports reference
Voltage low level LVREF。
Another embodiment of the present invention provides a kind of Wireless Telecom Equipment, including analog-digital converter, wherein, described mould
Intend digital converter and include arbitrary described fully differential generating circuit from reference voltage 10 in above-described embodiment.
Compared with prior art, beneficial effects of the present invention:
(1) source electrode that the output buffer of fully differential generating circuit from reference voltage of the present invention is only made up of transistor M1 and M2
Follower realizes, and circuit structure is simple, and can be reference voltage HVREFAnd LVREFThere is provided the biggest driving electric current, to realize relatively
Fast reference voltage is set up.
(2) the Full differential operational amplifier A1 in the fully differential generating circuit from reference voltage of the present invention is by using transistor
M6-M9 forms positive feedback loop, thus obtains great DC open-loop voltage gain, for fully differential generating circuit from reference voltage
Feedback circuit provides available sufficiently large loop gain.
(3) due to decay and the effect of feedback factor of series capacitance, the loop of fully differential generating circuit from reference voltage increases
Benefit is a value the lowest.Fully differential generating circuit from reference voltage of the present invention has good stability, and can quickly set up
To steady statue, thus ensure the quick foundation of MDAC.
(4) generating circuit from reference voltage of the present invention uses fully differential structure, can effectively resist the impact of common-mode noise,
The reference voltage of the high amplitude of oscillation can be exported simultaneously.
Accompanying drawing explanation
Fig. 1 is the electricity of a kind of fully differential generating circuit from reference voltage being suitable to pipeline ADC that the embodiment of the present invention provides
Line structure schematic diagram；
Fig. 2 is suitable to the fully differential generating circuit from reference voltage of pipeline ADC for the another kind that the embodiment of the present invention provides
Electrical block diagram；
The electrical block diagram of a kind of Full differential operational amplifier that Fig. 3 provides for the embodiment of the present invention；
The electrical block diagram of a kind of first level shifter that Fig. 4 provides for the embodiment of the present invention；
The electrical block diagram of a kind of second electrical level shift unit that Fig. 5 provides for the embodiment of the present invention；
Fig. 6 provide for the embodiment of the present invention another be suitable to the fully differential generating circuit from reference voltage of pipeline ADC
Electrical block diagram；
The circuit theory schematic diagram of a kind of level shifter that Fig. 7 provides for the embodiment of the present invention；
The friendship of a kind of fully differential generating circuit from reference voltage being suitable to pipeline ADC that Fig. 8 provides for the embodiment of the present invention
Stream schematic equivalent circuit.
Detailed description of the invention
Below in conjunction with specific embodiment, the present invention done further detailed description, but embodiments of the present invention are not limited to
This.
Embodiment one
Referring to Fig. 1 to Fig. 6, Fig. 1 is a kind of fully differential reference electricity being suitable to pipeline ADC that the embodiment of the present invention provides
Pressure produces the electrical block diagram of circuit, and Fig. 2 is suitable to the fully differential of pipeline ADC for the another kind that the embodiment of the present invention provides
The electrical block diagram of generating circuit from reference voltage, a kind of Full differential operational amplifier that Fig. 3 provides for the embodiment of the present invention
Electrical block diagram, the electrical block diagram of a kind of first level shifter that Fig. 4 provides for the embodiment of the present invention, figure
The electrical block diagram of the 5 a kind of second electrical level shift units provided for the embodiment of the present invention, Fig. 6 provides for the embodiment of the present invention
Another be suitable to the electrical block diagram of fully differential generating circuit from reference voltage of pipeline ADC.
Specifically, referring to Fig. 1, this fully differential generating circuit from reference voltage 10 includes: initial reference voltage input
VREF, power end VDD, earth terminal GND, Full differential operational amplifier A1, the first level shifter V1, second electrical level shift unit V2,
Common mode feedback circuit CMFB, the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5, the 6th
Resistance R6 and the first switching tube M1, second switch pipe M2；Wherein, described first switching tube M1, described 5th resistance R5, described
Six resistance R6 and described second switch pipe M2 are sequentially connected in series between described power end VDD and described earth terminal GND；Described first
Resistance R1 and described second resistance R2 is sequentially connected in series in described earth terminal GND and described first switching tube M1 and described 5th resistance
Between the node that R5 concatenation is formed；Described 3rd resistance R3 and described 4th resistance R4 is sequentially connected in series in described initial reference
Voltage input end VREFConcatenate the node formed with described 6th resistance R6 and described second switch pipe M2 between；Described the poorest
The positive input terminal Vin+ dividing operational amplifier A1 is electrically connected to described first resistance R1 and described second resistance R2 and concatenates formation
At node A, its negative input end Vin-is electrically connected to described 3rd resistance R3 and the node B of described 4th resistance R4 concatenation formation
Place, its negative output terminal Vout-and described first level shifter V1 is sequentially connected in series the control end to described first switching tube M1, its
Positive output end Vout+ and described second electrical level shift unit V2 is sequentially connected in series the control end to described second switch pipe M2；Described common
The input of cmfb circuit CMFB is electrically connected at the node C of described 5th resistance R5 and described 6th resistance R6 concatenation formation
And its outfan is electrically connected to described Full differential operational amplifier A1.
Alternatively, described first switching tube M1 is NMOS tube, and described second switch pipe M2 is PMOS.Further, institute
The substrate terminal of the source and described NMOS tube of stating NMOS tube is connected；The source of described PMOS connects with the substrate terminal of described PMOS
Connect.
Preferably, referring to Fig. 2, this fully differential generating circuit from reference voltage 10 also includes the 3rd electric capacity C3 and the 4th electric capacity
C4；One end of described 3rd electric capacity C1 is electrically connected to the control end of described first switching tube M1 and the other end be electrically connected to described in connect
Ground end GND；One end of described 4th electric capacity C4 is electrically connected to the control end of described second switch pipe M2 and the other end is electrically connected to
Described earth terminal GND.
Alternatively, refer to Fig. 3, described Full differential operational amplifier A1 include: the 3rd switching tube M3, the 4th switching tube
M4, the 5th switching tube M5, the 6th switching tube M6, the 7th switching tube M7, the 8th switching tube M8, the 9th switching tube M9, the tenth switch
Pipe M10, the 11st switching tube M11, twelvemo close pipe M12, the 13rd switching tube M13, the 14th switching tube M14, the 15th
Switching tube M15, sixteenmo close pipe M16, the 17th switching tube M17 and eighteenmo closes pipe M18；Wherein, described 3rd switch
Pipe M3, described 4th switching tube M4 and described 8th switching tube M8 are sequentially connected in series in described power end VDD and described earth terminal GND
Between, the control end of described 3rd switching tube M3 is electrically connected to the first bias voltage Vb1, the control of described 4th switching tube M4
End electrically connects described negative input end Vin-, and the control end of described 8th switching tube M8 is electrically connected to described 4th switching tube M4 and institute
State at the node that the 8th switching tube M8 concatenation is formed；
Described 5th switching tube M5 and described 9th switching tube M9 is sequentially connected in series in described 3rd switching tube M3 and described
At the node that four switching tube M4 concatenations are formed and between described earth terminal GND, the control end electrical connection of described 5th switching tube M5
Described positive input terminal Vin+, the control end of described 9th switching tube M9 is electrically connected to described 5th switching tube M5 and opens with the described 9th
Close at the node that pipe M9 concatenation is formed；
The transmission ends of described 6th switching tube M6 is electrically connected described 5th switching tube M5 and described 9th switching tube M9
At the node Y that concatenation is formed and earth terminal GND and its control end and be electrically connected to the control end of described 8th switching tube M8；Described
The transmission ends of seven switching tube M7 is electrically connected described 4th switching tube M4 and described 8th switching tube M8 and concatenates the nodes X formed
Place and earth terminal GND and its control end are electrically connected to the control end of described 9th switching tube M9；
Described 17th switching tube M17, described 15th switching tube M15, described 13rd switch M13, the described 11st
Switch M11 and described tenth switching tube M10 is sequentially connected in series between described power end VDD and described earth terminal GND, and the described tenth
The control end of seven switching tube M17 is electrically connected to the control end electrical connection of the second bias voltage Vb2, described 15th switching tube M15
To the 3rd bias voltage Vb3, the control end of described 13rd switching tube M13 is electrically connected to the 4th bias voltage Vb4, and the described tenth
The control end of one switching tube M11 is electrically connected to described 4th switching tube M4 and described 8th switching tube M8 and concatenates the nodes X formed
Place, the end that controls of described tenth switching tube M10 is electrically connected to the input of described common mode feedback circuit CMFB, described negative output terminal
Vout-is electrically connected at the node of described 15th switching tube M15 and described 13rd switch M13 concatenation formation；
Described eighteenmo closes pipe M18, described sixteenmo closes pipe M16, described 14th switch M14 and the described 12nd
Switching tube M12 is sequentially connected in series and concatenates with described 11st switching tube M11 and described tenth switching tube M10 in described power end VDD
Between the node formed, described eighteenmo closes the control end of pipe M18 and electrically connects described second bias voltage Vb2, and described the
Sixteenmo closes the control end electricity of control end the electrical connection described 3rd bias voltage Vb3, described 14th switching tube M14 of pipe M16
Connecting described 4th bias voltage Vb4, described twelvemo is closed pipe M12 and is electrically connected to described 5th switching tube M5 and the described 9th
The node Y place that switching tube M9 concatenation is formed, described positive output end Vout+ is electrically connected to described sixteenmo pass pipe M16 and described
At the node that 14th switch M14 concatenation is formed.
Wherein, described 3rd switching tube M3, described 4th switching tube M4, described 5th switching tube M5, the described 15th open
Close pipe M15, described sixteenmo closes pipe M16, described 17th switching tube M17 and described eighteenmo pass pipe M18 is PMOS,
Described 6th switching tube M6, described 7th switching tube M7, described 8th switching tube M8, described 9th switching tube M9, the described tenth
Switching tube M10, described 11st switching tube M11, described twelvemo close pipe M12, described 13rd switching tube M13, described the
14 switching tube M14 are NMOS tube.
Alternatively, refer to Fig. 4, described first level shifter V1 include: first switch K1, second switch K2, the 3rd
Switch K3, the 4th switch K4, the first electric capacity C1, the 5th electric capacity C5 and the first DC source Vbp1；Wherein, described first switch K1
It is sequentially connected in series in described in described first DC source Vbp1 and described Full differential operational amplifier A1 with described second switch K2
Between negative output terminal Vout-, described 3rd switch K3 and described 4th switch K4 is sequentially connected in series in described power end VDD with described
Between the control end of the first switching tube M1；One end of described first electric capacity C1 is electrically connected to described Full differential operational amplifier A1's
Described negative output terminal Vout-and the other end are electrically connected to the control end of described first switching tube M1, the one of described 5th electric capacity C5
End is electrically connected at the node that described first switch K1 and described second switch K2 concatenation is formed and the other end is electrically connected to described
At the node that 3rd switch K3 and described 4th switch K4 concatenation are formed.
Alternatively, refer to Fig. 5, described second electrical level shift unit V2 include: the 5th switch K5, the 6th switch K6, the 7th
Switch K7, the 8th switch K8, the second electric capacity C2, the 6th electric capacity C6 and the second DC source Vbn1；Wherein, described 5th switch K5
It is sequentially connected in series in described in described second DC source Vbn1 and described Full differential operational amplifier A1 with described 6th switch K6
Between positive output end Vout+, described 7th switch K7 and described 8th switch K8 is sequentially connected in series in described earth terminal GND with described
Between the control end of second switch pipe M2；One end of described second electric capacity C2 is electrically connected to described Full differential operational amplifier A1
Described positive output end Vout+ and the other end be electrically connected to the control end of described second switch pipe M2, described 6th electric capacity C6's
One end is electrically connected at the node of described 5th switch K5 and described 6th switch K6 concatenation formation and the other end is electrically connected to institute
State at the node of the 7th switch K7 and described 8th switch K8 concatenation formation.
Alternatively, referring to Fig. 6, this fully differential generating circuit from reference voltage 10 also includes: the 19th switching tube M19,
20 switching tube M20, the 7th resistance R7 and the 8th resistance R8；Described 19th switching tube M19, described 7th resistance R7, described
8th resistance R8 and described 20th switching tube M20 is sequentially connected in series between described power end VDD and described earth terminal GND, and
Described 19th end that controls opening the light pipe M19 is electrically connected to the described first control end opening the light pipe M1, and the described 20th opens the light pipe
The end that controls of M20 is electrically connected to the described second control end opening the light pipe M2, described 19th switching tube M19 and described 7th resistance
The node output reference voltage high level HV that R7 concatenation is formedREF, described 8th resistance R8 and described 20th switching tube M20 string
Connect node output reference voltage low level LV of formationREF。
The present embodiment, the source electrode that the output buffer of fully differential generating circuit from reference voltage is consisted of transistor M1 and M2
Follower realizes, and circuit structure is simple, and can be reference voltage HVREFAnd LVREFThere is provided the biggest driving electric current, to realize relatively
Fast reference voltage is set up；Full differential operational amplifier A1 is by using transistor M6-M9 to form positive feedback loop, thus obtains
Obtaining great DC open-loop voltage gain, the feedback circuit for fully differential generating circuit from reference voltage provides available sufficiently large
Loop gain；Due to decay and the effect of feedback factor of series capacitance, the loop of fully differential generating circuit from reference voltage increases
Benefit is a value the lowest.Therefore, fully differential generating circuit from reference voltage of the present invention has good stability, and can be quickly
Set up steady statue, thus ensure the quick foundation of MDAC.
Embodiment two
Referring again to Fig. 1 to Fig. 6, and a kind of level that referring also to Fig. 7 to Fig. 8, Fig. 7 provide for the embodiment of the present invention
The circuit theory schematic diagram of shift unit；Fig. 8 is suitable to the fully differential ginseng of pipeline ADC for the yet a further that the embodiment of the present invention provides
Examine the electrical block diagram of voltage generation circuit.The fully differential of the present invention is joined on the basis of above-described embodiment by the present embodiment
Examine voltage generation circuit 10 to be described in detail.Specific as follows:
Referring to Fig. 1, the fully differential generating circuit from reference voltage 10 that the embodiment of the present invention provides is that a closed loop feedback is returned
Road.Described closed feedback loop is mainly by a Full differential operational amplifier A1,2 level shifters and 2 output buffers
Constitute.Wherein, the first transistor M1 the source follower formed and the source follower formed by transistor seconds M2 are defeated
Go out buffer.Described the first transistor M1 is nmos pass transistor, and transistor seconds M2 is PMOS transistor.
Concrete circuit connecting relation is as follows:
The positive input terminal Vin+ of Full differential operational amplifier A1 is connected to one end of the first resistance R1, and the first resistance R1's is another
One end ground connection.The negative input end Vin-of Full differential operational amplifier A1 is connected to one end of the 3rd resistance R3, the 3rd resistance R3's
The other end is connected to initial reference voltage VREF(VREFProduced by band-gap reference and generating circuit from reference voltage).
The negative output terminal Vout-of Full differential operational amplifier A1 connects one end of the V1 of the first level shifter, the first electricity
The other end of translational shifting device V1 is connected to the grid of the first transistor M1.The drain electrode of described the first transistor M1 connects supply voltage；
Together with source electrode is connected to substrate, output reference voltage high level HVREF。
The positive output end Vout+ of Full differential operational amplifier A1 is connected to one end of second electrical level shift unit V2, the second electricity
The other end of translational shifting device V2 is connected to the grid of transistor seconds M2.The drain electrode of described transistor seconds M2 connects power supply electricity
Pressure；Source electrode links together with substrate, output reference voltage low level LVREF。
Described the first transistor M1 and the source of transistor seconds M2 and substrate link together, and decrease what Vth brought
Non-linear.
One end of second resistance R2 is connected to the positive input terminal vout+ of Full differential operational amplifier A1, and the other end is connected to
The source electrode of the first transistor M1.One end of 4th resistance R4 is connected to the negative input end Vout-of Full differential operational amplifier A1, separately
One end is connected to the source electrode of transistor seconds M2.
One end of 5th resistance R5 is connected to the source electrode of the first transistor M1, the other end and the 6th resistance R6 and is connected to one
Rising, the other end of the 6th resistance R6 is connected to the source electrode of transistor seconds M2.
The node C that 5th resistance R5 and the 6th resistance R6 links together is electric with the common-mode feedback of Full differential operational amplifier
The input on road (CMFB) is connected.The outfan of common mode feedback circuit (CMFB) is connected to the tenth crystalline substance of Full differential operational amplifier
The grid of body pipe M10.
Wherein, common mode feedback circuit (CMFB) makes the common mode value of output reference voltage maintain VDD/2.
One end of 3rd electric capacity C3 is connected to the grid of the first transistor M1, other end ground connection；One end of 4th electric capacity C4
It is connected to the grid of transistor seconds M2, other end ground connection.
Described 3rd electric capacity C3 and the 4th electric capacity C4 is grid decoupling capacitance.The grid of the first transistor M1 is by decoupling electricity
Appearance C3 realizes ground and decouples, and the grid of transistor seconds M2 realizes ground by decoupling capacitance C4 and decouples.This grid is by solving
Coupling electric capacity realizes the structure that ground decouples good buffer action, reduces the power line coupling to outfan, improves
The PSRR of circuit.
Referring again to Fig. 1, the reference voltage high level HV of ADC in the present embodimentREFThe source formed by the first transistor M1
Pole follower output, reference voltage low level LVREFThe source follower output formed by transistor seconds M2.
In order to meet the design accuracy requirement of MDAC, output reference voltage to realize a high output voltage swing, first crystal
The grid voltage of pipe M1 need to be higher than VDD, and the grid voltage of transistor seconds M2 need to be less than GND.In order to give as output buffer
Transistor provide rational DC point, positive output end and negative output terminal at Full differential operational amplifier introduce respectively
Level shifter V1 and V2.
Referring to Fig. 7, level shifter V1 and include electric capacity C1 and C5, one end of electric capacity C5 is by switch K1 and DC voltage
Vbp1 is switched on or switched off, and is switched on or switched off by one end of switch K2 and electric capacity C1；The other end of electric capacity C5 is by switch K3
It is switched on or switched off with supply voltage VDD, and is switched on or switched off by the other end of switch K4 and electric capacity C1.One end of electric capacity C1 is also
Being connected to the negative output terminal Vout-of Full differential operational amplifier, the other end is additionally coupled to the grid of the first transistor M1.
Level shifter V2 includes electric capacity C2 and C6, one end of electric capacity C6 connected by switch K5 and DC voltage Vbn1 or
Disconnect, and be switched on or switched off by one end of switch K6 and electric capacity C2；The other end of electric capacity C6 is connected with ground GND by switch K7
Or disconnect, and it is switched on or switched off by the other end of switch K8 and electric capacity C2.One end of electric capacity C2 is additionally attached to fully differential computing
The positive output end Vout+ of amplifier, the other end is additionally coupled to the grid of transistor seconds M2.
Wherein, Φ 1 and Φ 2 is that the biphase of level shifter does not overlap clock, Vbp1 and Vbn1 is DC voltage.Φ 1 is controlled
The Guan Bi of system switch K1, K3, K5, K7 and unlatching；Φ 2 controls Guan Bi and the unlatching of switch K2, K4, K6, K8.
Level shifter V1 makes voltage Vout1-add C5 (VDD-Vbp1)/(C1+C5), level than voltage Vout-
Shift unit V2 makes voltage Vout1+ reduce C6 (Vbn1-0)/(C2+C6) than voltage Vout+.By adjusting Vbp1 and Vbn1
Size so that the first transistor M1 and transistor seconds M2 as output buffer are biased in suitable DC operation
Point, thus provide output electric current for output reference voltage.
From the above mentioned, the source follower that the present embodiment is only made up of transistor M1 and M2 as the circuit of outfan is real
Existing, circuit structure is simple, and can be that reference voltage HVREF and LVREF provides the biggest driving electric current, to realize joining faster
Examine Voltage Establishment.Further, the source follower being made up of transistor M1 and M2 has the highest input impedance and relatively low output
Impedance, can drive the switched capacitor network in comparator and the capacitive load in MDAC.
The structure of the Full differential operational amplifier A1 being described below in described generating circuit from reference voltage:
Described Full differential operational amplifier uses two-layer configuration, and first order pre-amplification stage utilizes positive feedback structure to improve entirety
Gain, the second level is the amplifier of tube-in-tube structure.
Referring again to Fig. 3, for the circuit diagram of described Full differential operational amplifier, in the circuit, node Vin+ and
Vin-is respectively positive input terminal and the negative input end of amplifier, and nodes X and Y are positive output end and the negative output of pre-amplification stage respectively
End, node Vout+ and Vout-is respectively positive output end and the negative output terminal of amplifier, and node VDD and GND connects supply voltage respectively
And ground voltage.
The operational amplifier of this embodiment includes: third transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th
Transistor M6, the 7th transistor M7, the 8th transistor M8, the 9th transistor M9, the tenth transistor M10, the 11st transistor
M11, the tenth two-transistor M12, the 13rd transistor M13, the 14th transistor M14, the 15th transistor M15, the 16th crystalline substance
Body pipe M16, the 17th transistor M17, the 18th transistor M18, transistor M3-M5, M15-M18 are PMOS transistor, crystal
Pipe M6-M14 is nmos pass transistor, wherein,
The grid of third transistor M3 receives the input Vb1 of the first bias voltage, and drain electrode receives the 4th transistor M4's
Source electrode and the source electrode of the 5th transistor M5, the source ground of third transistor M3.
The grid of the 4th transistor M4 receives negative input end Vin-, and the grid of the 6th transistor M6, the 8th crystalline substance are received in drain electrode
The grid of body pipe M8 and the drain electrode of the 7th transistor M7.The source electrode of the 4th transistor M4 receives the drain electrode and of third transistor M3
The source electrode of five transistor M5.
The grid of the 5th transistor M5 receives positive input terminal Vin+, and the grid of the 7th transistor M7, the 9th crystalline substance are received in drain electrode
The grid of body pipe M9 and the drain electrode of the 6th transistor M6.The source electrode of the 5th transistor M5 receives the drain electrode and of third transistor M3
The source electrode of four transistor M4.
The grid of the 6th transistor M6 receives the drain electrode of the 4th transistor M4, the grid of the 8th transistor M8, and the 7th crystalline substance
The drain electrode of body pipe M7.The drain electrode of the 5th transistor M5, the grid of the 7th transistor M7 and are received in the drain electrode of the 6th transistor M6
The grid of nine transistor M9.The source ground of the 6th transistor M6.
The grid of the 7th transistor M7 receives the drain electrode of the 5th transistor M5, the grid of the 9th transistor M9, and the 6th crystalline substance
The drain electrode of body pipe M6.The drain electrode of the 4th transistor M4, the grid of the 6th transistor M6 and are received in the drain electrode of the 7th transistor M7
The grid of eight transistor M8.The source ground of the 7th transistor M7.
The grid of the 8th transistor M8 receives the drain electrode of itself, and with the grid of the 6th transistor M6, the 7th transistor
The grid of M7 connects.The source ground of the 8th transistor M8.
The grid of the 9th transistor M9 receives the drain electrode of itself, and with the grid of the 7th transistor M7, the 6th transistor
The grid of M6 connects.The source ground of the 9th transistor M9.
The grid of the tenth transistor M10 receives common-mode feedback outfan CMFB, and the source of the 11st transistor M11 is received in drain electrode
Pole and the source electrode of the tenth two-transistor M12, the source ground of the tenth transistor M10.
The grid of the 11st transistor M11 receives the positive output end X of pre-amplification stage, and the 13rd transistor M13 is received in drain electrode
Drain electrode, the source electrode of the 11st transistor M11 receives source electrode and the drain electrode of the tenth transistor M10 of the tenth two-transistor M12.
The grid of the tenth two-transistor M12 receives the negative output terminal Y of pre-amplification stage, and the 14th transistor M14 is received in drain electrode
Drain electrode, the source electrode of the tenth two-transistor M12 receives source electrode and the drain electrode of the tenth transistor M10 of the 11st transistor M11.
The grid of the 13rd transistor M13 receives the input Vb4 of the 4th bias voltage, and the 15th transistor is received in drain electrode
The drain electrode of M15, the source electrode of the 13rd transistor receives the drain electrode of the 17th transistor M17.
The grid of the 14th transistor M14 receives the input Vb4 of the 4th bias voltage, and the 14th transistor is received in drain electrode
The drain electrode of M14, the source electrode of the 14th transistor receives the drain electrode of the 16th transistor M16.
The grid of the 15th transistor M15 receives the input Vb3 of the 3rd bias voltage, and the 13rd transistor is received in drain electrode
The drain electrode of M13, the source electrode of the 15th transistor receives the drain electrode of the 17th transistor M17.
The grid of the 16th transistor M16 receives the input Vb3 of the 3rd bias voltage, and the 14th transistor is received in drain electrode
The drain electrode of M14, the source electrode of the 16th transistor receives the drain electrode of the 18th transistor M18.
The grid of the 17th transistor M17 receives the input Vb2 of the second bias voltage, and the 15th transistor is received in drain electrode
The source electrode of M15, the source electrode of the 17th transistor M17 receives power supply.
The grid of the 18th transistor M18 receives the input Vb2 of the second bias voltage, and the 16th transistor is received in drain electrode
The source electrode of M16, the source electrode of the 18th transistor M18 receives power supply.
Wherein, transistor M3-M9 constitutes the pre-amplification stage of described Full differential operational amplifier, and transistor M10-M18 is constituted
The second level tube-in-tube structure of described Full differential operational amplifier.
The pre-amplification stage circuit of the Full differential operational amplifier A1 of the present invention has two feedback paths, and Article 1 is by
The series current feedback of the common source node of four transistor M4 and the 5th transistor M5, this feedback network is negative feedback；Second
Article being the shunt voltage feedback connecting the 6th transistor M6 and the 7th transistor M7 grid and drain electrode, this feedback network is positive and negative
Feedback.
When positive feedback coefficient is more than degeneration factor, whole pre-amplification stage shows as positive feedback.When positive feedback coefficient is little
When degeneration factor, whole pre-amplification stage shows as negative feedback.
Output impedance at the positive output nodes X of pre-amplification stage is:
Same, the output impedance at negative output node Y is:
Wherein, gm6, gm7, gm8, gm9 are the mutual conductance of transistor M6, M7, M8, M9 respectively.
In the present embodiment, load transistor M8's and M9 of pre-amplification stage is equal sized, the size phase of transistor M6 and M7
Deng, and the size being slightly larger in dimension than M6 and M7 of M8 and M9.Therefore, the mutual conductance of the M8 mutual conductance slightly larger than M6, M9 is slightly larger than M7.
The output impedance of pre-amplification stage tends to a numerical value the biggest, and pre-amplification stage feedback network shows as positive feedback, thus obtains
DC open-loop gain greatly.
The second level of the present embodiment is Telescopic cascode amplifier, it is provided that gain at (gm ro)2/ 2 orders of magnitude.Enter
One step improves the gain of described Full differential operational amplifier.
From the above mentioned, the Full differential operational amplifier A1 of the present invention is by using transistor M6-M9 to form positive and negative being fed back to
Road, thus obtain great DC open-loop voltage gain, providing for the feedback circuit of fully differential generating circuit from reference voltage can profit
Sufficiently large loop gain.
Referring again to Fig. 6, as the preferred scheme of one, the embodiment of the present invention provides another kind of reference voltage to produce electricity
Road.Increasing open-loop branch 2 on the basis of Fig. 1, open-loop branch 2 replicates according to branch road 1 with the breadth length ratio relation of K:1.Open
Electric current on ring branch road 2 is K:1 with the current ratio relation on branch road 1.
Wherein, the drain electrode of the 19th transistor M19 is connected to power vd D, and grid is connected with the grid of the first transistor M1
Together.The source electrode of the 19th transistor M19 links together with substrate, output reference voltage high level HVREF。
The grounded drain of the 20th transistor M20, grid links together with the grid of transistor seconds M2.20th is brilliant
The source electrode of body pipe M20 links together with substrate, output reference voltage LVREF.
One end of 7th resistance R7 is connected to the source electrode of the 19th transistor, and one end of the other end and the 8th resistance R8 connects
Together.The other end of the 8th resistance R8 is connected to the source electrode of the 20th transistor M20.
From the above mentioned, the open-loop branch 2 of the outfan of generating circuit from reference voltage preferably is followed by source electrode
Device realizes.The source follower of open-loop branch 2 has good buffer action, it is to avoid the shadow of voltage dithering and closed feedback loop
Ring, make output reference voltage more stable.The power line coupling to outfan can be reduced simultaneously, improve circuit
PSRR。
Derive HV below according to the fully differential generating circuit from reference voltage shown in Fig. 1REFAnd LVREFExpression formula.
Resistor satisfied following relation in described feedback circuit:
R1=R2=R3=R4
R5=R6
Empty open circuit (Intrinsic virtual cutoff) effect according to operational amplifier, lists fully differential computing and puts
At the node A that big device A1 positive input terminal is corresponding, row nodal voltage equation is:
Listing row nodal voltage equation at the node B that Full differential operational amplifier A1 negative input end is corresponding is:
(VREF-Vin-)/R3=(Vin--LVREF)/R4
Imaginary short effect (Intrinsic virtual short) according to operational amplifier, can obtain:
Vin+=Vin-
By the symmetry of fully differential generating circuit from reference voltage, the voltage at node C can be obtained and meet:
Vcom=(HVREF+LVREF)/2
Wherein, Vcom is the intermediate value of height reference voltage, and the output common mode voltage of Full differential operational amplifier A1.
Output reference voltage high level HV can be obtained by above formulaREFWith reference voltage low level LVREFExpression formula:
HVREF=Vcom+VREF/2
LVREF=Vcom-VREF/2
VREF=HVREF-LVREF
Found out by expression formula, output reference voltage HVREFAnd LVREFIt is amplifier output common mode voltage Vcom and initial reference electricity
Pressure VREFFunction.Wherein, common mode feedback circuit (CMFB) makes the intermediate value Vcom of output reference voltage maintain VDD/2, and
And initial reference voltage VREFProduced by band-gap reference and generating circuit from reference voltage.
From the above mentioned, fully differential generating circuit from reference voltage of the present invention can export reference voltage high level HV accuratelyREF
With reference voltage low level LVREF。
Being analyzed the stability of fully differential generating circuit from reference voltage below, Fig. 8 is that fully differential reference voltage produces
The ac equivalent circuit figure of circuit, wherein, the impact of level shifter is not paid attention to.
According to Fig. 8, list the loop gain of generating circuit from reference voltage:
Wherein, gA1RoA1Representing the gain of Full differential operational amplifier A1, C3/ (C3+C1) item is that operational amplifier A 1 is drawn
The gain entered is through series capacitance C1, the pad value of C3, and the output gain of integrated circuit is attenuated as original C3/ (C1+
C3)。1/(1+1/(gM2(R5//RdsM2))) it is the transfer function of source follower, gain can there be is certain decay.R3/(R3
+ R4) represent that output voltage feeds back to the voltage of Full differential operational amplifier input, i.e. feedback factor.
Finding out from expression formula, due to decay and the effect of feedback factor of series capacitance, fully differential reference voltage produces electricity
The loop gain on road is a value the lowest.
From the above mentioned, fully differential generating circuit from reference voltage of the present invention has good stability, and can quickly set up
To steady statue, thus ensure the quick foundation of MDAC.
Further, the generating circuit from reference voltage of the present invention uses fully differential structure, can effectively resist the shadow of common-mode noise
Ring, the reference voltage of the high amplitude of oscillation can be exported simultaneously.
Embodiment three
Present invention also offers a kind of Wireless Telecom Equipment, change Wireless Telecom Equipment and include analog-digital converter, wherein,
Described analog-digital converter includes arbitrary described fully differential generating circuit from reference voltage 10 in above-described embodiment.
Above content is to combine concrete preferred implementation further description made for the present invention, it is impossible to assert
Being embodied as of the present invention is confined to these explanations.For general technical staff of the technical field of the invention,
On the premise of present inventive concept, it is also possible to make some simple deduction or replace, all should be considered as belonging to the present invention's
Protection domain.
Claims (10)
1. the fully differential generating circuit from reference voltage (10) being suitable to pipeline ADC, it is characterised in that including: initial reference
Voltage input end (VREF), power end (VDD), earth terminal (GND), Full differential operational amplifier (A1), the first level shifter
(V1), second electrical level shift unit (V2), common mode feedback circuit (CMFB), the first resistance (R1), the second resistance (R2), the 3rd resistance
(R3), the 4th resistance (R4), the 5th resistance (R5), the 6th resistance (R6) and the first switching tube (M1), second switch pipe (M2)；Its
In, described first switching tube (M1), described 5th resistance (R5), described 6th resistance (R6) and described second switch pipe (M2) depend on
Secondary it is serially connected with between described power end (VDD) and described earth terminal (GND)；
Described first resistance (R1) and described second resistance (R2) are sequentially connected in series in described earth terminal (GND) and described first switch
Between the node that pipe (M1) and described 5th resistance (R5) concatenation are formed；Described 3rd resistance (R3) and described 4th resistance
(R4) it is sequentially connected in series in described initial reference voltage input (VREF) and described 6th resistance (R6) and described second switch pipe
(M2) between the node that concatenation is formed；
The positive input terminal (Vin+) of described Full differential operational amplifier (A1) is electrically connected to described first resistance (R1) and described
Node (A) place that two resistance (R2) concatenation is formed, its negative input end (Vin-) is electrically connected to described 3rd resistance (R3) and described
Node (B) place that 4th resistance (R4) concatenation is formed, its negative output terminal (Vout-) is with described first level shifter (V1) successively
The control end of concatenation extremely described first switching tube (M1), its positive output end (Vout+) depends on described second electrical level shift unit (V2)
The control end of secondary concatenation extremely described second switch pipe (M2)；
The input of described common mode feedback circuit (CMFB) is electrically connected to described 5th resistance (R5) and described 6th resistance (R6)
Node (C) place and its outfan that concatenation is formed are electrically connected to described Full differential operational amplifier (A1).
Circuit the most according to claim 1 (10), it is characterised in that described first switching tube (M1) is NMOS tube, described
Second switch pipe (M2) is PMOS.
Circuit the most according to claim 2 (10), it is characterised in that the source of described NMOS tube and the lining of described NMOS tube
Bottom connects；The source of described PMOS is connected with the substrate terminal of described PMOS.
Circuit the most according to claim 1 (10), it is characterised in that also include the 3rd electric capacity (C3) and the 4th electric capacity
(C4)；One end of described 3rd electric capacity (C1) is electrically connected to the control end of described first switching tube (M1) and the other end is electrically connected to
Described earth terminal (GND)；One end of described 4th electric capacity (C4) is electrically connected to the control end of described second switch pipe (M2) and another
One end is electrically connected to described earth terminal (GND).
Circuit the most according to claim 1 (10), it is characterised in that described Full differential operational amplifier (A1) including: the
Three switching tubes (M3), the 4th switching tube (M4), the 5th switching tube (M5), the 6th switching tube (M6), the 7th switching tube (M7), the 8th
Switching tube (M8), the 9th switching tube (M9), the tenth switching tube (M10), the 11st switching tube (M11), twelvemo close pipe
(M12), the 13rd switching tube (M13), the 14th switching tube (M14), the 15th switching tube (M15), sixteenmo close pipe
(M16), the 17th switching tube (M17) and eighteenmo close pipe (M18)；Wherein,
Described 3rd switching tube (M3), described 4th switching tube (M4) and described 8th switching tube (M8) are sequentially connected in series in described electricity
Between source (VDD) and described earth terminal (GND), the control end of described 3rd switching tube (M3) is electrically connected to the first bias voltage
(Vb1), the control end of described 4th switching tube (M4) electrically connects described negative input end (Vin-), described 8th switching tube (M8)
Control end to be electrically connected at the node of described 4th switching tube (M4) and described 8th switching tube (M8) concatenation formation；
Described 5th switching tube (M5) and described 9th switching tube (M9) are sequentially connected in series in described 3rd switching tube (M3) and described
At the node that 4th switching tube (M4) concatenation is formed and between described earth terminal (GND), the control of described 5th switching tube (M5)
End electrically connects described positive input terminal (Vin+), and the control end of described 9th switching tube (M9) is electrically connected to described 5th switching tube
(M5) concatenate with described 9th switching tube (M9) at the node formed；
The transmission ends of described 6th switching tube (M6) is electrically connected described 5th switching tube (M5) and described 9th switching tube
(M9) concatenate node (Y) place formed and earth terminal (GND) and it controls end and is electrically connected to the control of described 8th switching tube (M8)
End processed；The transmission ends of described 7th switching tube (M7) is electrically connected described 4th switching tube (M4) and described 8th switching tube
(M8) concatenate node (X) place formed and earth terminal (GND) and it controls end and is electrically connected to the control of described 9th switching tube (M9)
End processed；
Described 17th switching tube (M17), described 15th switching tube (M15), described 13rd switch (M13), the described tenth
One switch (M11) and described tenth switching tube (M10) be sequentially connected in series in described power end (VDD) and described earth terminal (GND) it
Between, the control end of described 17th switching tube (M17) is electrically connected to the second bias voltage (Vb2), described 15th switching tube
(M15) control end is electrically connected to the 3rd bias voltage (Vb3), and the control end of described 13rd switching tube (M13) is electrically connected to
4th bias voltage (Vb4), the control end of described 11st switching tube (M11) is electrically connected to described 4th switching tube (M4) and institute
Stating node (X) place that the 8th switching tube (M8) concatenation is formed, the control end of described tenth switching tube (M10) is electrically connected to described common
The input of cmfb circuit (CMFB), described negative output terminal (Vout-) is electrically connected to described 15th switching tube (M15) and institute
State at the node that the 13rd switch (M13) concatenation is formed；
Described eighteenmo closes pipe (M18), described sixteenmo closes pipe (M16), described 14th switch (M14) and the described tenth
Two switching tubes (M12) are sequentially connected in series in described power end (VDD) and described 11st switching tube (M11) and described tenth switching tube
(M10), between the node that concatenation is formed, described eighteenmo closes the control end of pipe (M18) and electrically connects described second bias voltage
(Vb2), described sixteenmo closes the control end of pipe (M16) and electrically connects described 3rd bias voltage (Vb3), and the described 14th switchs
The control end of pipe (M14) electrically connects described 4th bias voltage (Vb4), and described twelvemo is closed pipe (M12) and is electrically connected to described
5th switching tube (M5) concatenates node (Y) place formed with described 9th switching tube (M9), and described positive output end (Vout+) is electrically connected
It is connected to described sixteenmo close at the node of pipe (M16) and described 14th switch (M14) concatenation formation.
Circuit the most according to claim 5 (10), it is characterised in that described 3rd switching tube (M3), described 4th switch
Pipe (M4), described 5th switching tube (M5), described 15th switching tube (M15), described sixteenmo close pipe (M16), described the
It is PMOS that 17 switching tubes (M17) and described eighteenmo close pipe (M18), described 6th switching tube (M6), the described 7th opens
Close pipe (M7), described 8th switching tube (M8), described 9th switching tube (M9), described tenth switching tube (M10), the described 11st
Switching tube (M11), described twelvemo close pipe (M12), described 13rd switching tube (M13), described 14th switching tube (M14)
For NMOS tube.
Circuit the most according to claim 1 (10), it is characterised in that described first level shifter (V1) including: first
Switch (K1), second switch (K2), the 3rd switch (K3), the 4th switch (K4), the first electric capacity (C1), the 5th electric capacity (C5) and the
One DC source (Vbp1)；Wherein, described first switch (K1) and described second switch (K2) are sequentially connected in series in described first straight
Between stream power supply (Vbp1) and the described negative output terminal (Vout-) of described Full differential operational amplifier (A1), described 3rd switch
(K3) and described 4th switch (K4) be sequentially connected in series in described power end (VDD) and described first switching tube (M1) control end it
Between；One end of described first electric capacity (C1) is electrically connected to the described negative output terminal of described Full differential operational amplifier (A1)
(Vout-) and the other end is electrically connected to the control end of described first switching tube (M1), one end of described 5th electric capacity (C5) is electrically connected
It is connected at the node of described first switch (K1) and described second switch (K2) concatenation formation and the other end is electrically connected to described the
At the node that three switches (K3) and described 4th switch (K4) concatenation are formed.
Circuit the most according to claim 1 (10), it is characterised in that described second electrical level shift unit (V2) including: the 5th
Switch (K5), the 6th switch (K6), the 7th switch (K7), the 8th switch (K8), the second electric capacity (C2), the 6th electric capacity (C6) and the
Two DC sources (Vbn1)；Wherein, described 5th switch (K5) and the described 6th switchs (K6) and is sequentially connected in series in described second straight
Between stream power supply (Vbn1) and the described positive output end (Vout+) of described Full differential operational amplifier (A1), described 7th switch
(K7) and described 8th switch (K8) be sequentially connected in series in described earth terminal (GND) and described second switch pipe (M2) control end it
Between；One end of described second electric capacity (C2) is electrically connected to the described positive output end (Vout of described Full differential operational amplifier (A1)
+) and the other end be electrically connected to the control end of described second switch pipe (M2), one end of described 6th electric capacity (C6) is electrically connected to institute
State at the node of the 5th switch (K5) and described 6th switch (K6) concatenation formation and the other end is electrically connected to described 7th switch
(K7) concatenate at the node formed with described 8th switch (K8).
Circuit the most according to claim 1 (10), it is characterised in that also include: the 19th switching tube (M19), the 20th
Switching tube (M20), the 7th resistance (R7) and the 8th resistance (R8)；Described 19th switching tube (M19), described 7th resistance
(R7), described 8th resistance (R8) and described 20th switching tube (M20) are sequentially connected in series and connect with described in described power end (VDD)
Between ground end (GND), and the described 19th control end opening the light pipe (M19) is electrically connected to the described first control opening the light pipe (M1)
End, the described 20th control end opening the light pipe (M20) is electrically connected to the described second control end opening the light pipe (M2), and the described 19th
The node output reference voltage high level (HV that switching tube (M19) and described 7th resistance (R7) concatenation are formedREF), the described 8th
The node output reference voltage low level (LV that resistance (R8) and described 20th switching tube (M20) concatenation are formedREF)。
10. a Wireless Telecom Equipment, including analog-digital converter, it is characterised in that described analog-digital converter includes
Fully differential generating circuit from reference voltage (10) as described in any one of claim 1～9.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN109814367A (en) * | 2018-12-29 | 2019-05-28 | 西安电子科技大学 | A kind of time-to-digit converter with gate ena-bung function |
| CN110224700A (en) * | 2019-05-05 | 2019-09-10 | 西安电子科技大学 | A kind of high speed complementation type dual power supply operational amplifier |
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