CN102412824B - Differential reference voltage buffer - Google Patents
Differential reference voltage buffer Download PDFInfo
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- CN102412824B CN102412824B CN201110397553.1A CN201110397553A CN102412824B CN 102412824 B CN102412824 B CN 102412824B CN 201110397553 A CN201110397553 A CN 201110397553A CN 102412824 B CN102412824 B CN 102412824B
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- feedback circuit
- mode feedback
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Abstract
The invention provides a differential reference voltage buffer, which comprises a control section, a copy buffer section, and a main buffer section connected in series between the control section and the copy buffer section, wherein the control section comprises a full differential operational amplifier and a common-mode feedback circuit, and an output end the common-mode feedback circuit is connected to a common-mode feedback input end of the full differential operational amplifier; the main buffer section comprises a first transistor and a second transistor sharing bias current on a same branch, an output end of the full differential operational amplifier is connected to grid electrodes of the first and second transistors, and source electrodes of the first and second transistors are connected to an input end of the common-mode feedback circuit; and the copy buffer section comprises a fourth transistor and a fifth transistor sharing bias current on a same branch, grid electrodes of the fourth and fifth transistors are respectively connected to the grid electrodes of the first and second transistor, and source electrodes of the fourth and fifth transistors respectively output a reference voltage. The differential reference voltage buffer provided by the invention has fast response speed, low noise and low power consumption, and can increase the performance and precision of a data converter.
Description
Technical field
The present invention relates to integrated circuit fields, be specifically related to a kind of differential reference voltage buffer.
Background technology
Reference voltage (Voltage Reference), typically refers to the voltage of the high stability that is used as voltage reference in circuit, also referred to as reference voltage.In many integrated circuits and circuit unit, as digital to analog converter (DAC), analog to digital converter (ADC), linear voltage regulator and switching regulator, all need precision and stable reference voltage source.Desirable reference voltage source is not subject to the impact of power supply and temperature, in circuit, can provide stable voltage.
In data converting circuit, the benchmark that reference voltage quantizes as data, has very high requirement to its speed and precision.Yet, in the data converter of high-speed, high precision, due to a large amount of uses of switched-capacitor circuit, on reference voltage and power line, all will there is very large voltage fluctuation, this has had a strong impact on performance and the precision of whole data converter.
How to guarantee reference voltage quickly recover to stable level after to capacitor charge and discharge, insensitive and consume the key that the least possible energy has become whole data converter design to little voltage disturbance.
Summary of the invention
The object of the present invention is to provide the differential reference voltage buffer of a kind of fast response time, low noise and low-power consumption.
To achieve these goals, the invention provides a kind of differential reference voltage buffer, comprise control section, host buffer part and copy buffer portion, described host buffer is partly serially connected with control section and copies between buffer portion, wherein:
Described control section comprises Full differential operational amplifier and common mode feedback circuit, and the output of described common mode feedback circuit is connected to the common-mode feedback input of described Full differential operational amplifier;
Described host buffer partly comprises the first transistor and the transistor seconds of series connection, described the first transistor and transistor seconds share a road bias current, the positive-negative output end of described Full differential operational amplifier is connected to respectively the grid of described the first transistor and transistor seconds, and the source electrode of described the first transistor and transistor seconds is connected to the input of described common mode feedback circuit;
Describedly copy the 4th transistor and the 5th transistor that buffer portion comprises series connection, described the 4th transistor and the 5th transistor share a road bias current, described the 4th transistor and the 5th transistorized grid are connected to respectively the grid of described the first transistor and transistor seconds, and described the 4th transistor and the 5th transistorized source electrode are exported respectively positive and negative two reference voltages.
As preferably, the positive-negative input end of described Full differential operational amplifier for the source electrode that receives input reference voltage and be connected to described the first transistor and transistor seconds by the third and fourth resistance respectively by the first and second resistance respectively to form negative feedback.
As preferably, described common mode feedback circuit has positive and negative two inputs, a common mode electrical level input, described common mode electrical level input is in order to receive the common-mode voltage of outside input, and described common mode feedback circuit forces the described the first transistor of described host buffer part and the first voltage of the source electrode output of transistor seconds and the average of second voltage to equal described common-mode voltage.
As preferably, described common mode feedback circuit comprises operational amplifier and is connected respectively to the 5th resistance and the 6th resistance of the positive input terminal of described operational amplifier, the other end of described the 5th resistance and the 6th resistance is respectively the positive-negative input end of described common mode feedback circuit, the negative input end of described operational amplifier is the common mode electrical level input of described common mode feedback circuit, the output that the output of described operational amplifier is described common mode feedback circuit.
As preferably, described common mode feedback circuit comprises the first differential pair consisting of the 7th transistor and the 8th transistor and the second differential pair consisting of the 9th transistor and the tenth transistor, described the 8th transistor and the 9th common mode electrical level input that transistorized grid is connected and this grid is common mode feedback circuit, described the 8th transistor is connected and is connected to the 11 transistorized drain electrode with the 9th transistorized drain electrode, described the 11 transistorized grid is connected to and drains and be the output of common mode feedback circuit, described the 7th transistor and the tenth transistorized grid are respectively the positive-negative input end of described common mode feedback circuit.
As preferably, described host buffer part also comprises the 3rd transistor, and described the first transistor is connected between power supply and transistor seconds, and the 3rd transistor is connected between transistor seconds and ground.
As preferably, described host buffer part also comprises that decoupling capacitor, described decoupling capacitor are connected to respectively between power supply and the grid of the first transistor, between the first transistor and the grid of transistor seconds and between transistor seconds and ground.
As preferably, the first transistor in described host buffer part and transistor seconds share a road bias current, and all adopt nmos pass transistor to realize.
As preferably, described in copy buffer portion and also comprise the 6th transistor, described the 4th transistor is connected between power supply and the 5th transistor, the 6th transistor is connected between the 5th transistor and ground.
As preferably, described in the 4th transistor and the 5th transistor that copy in buffer portion share a road bias current, and all adopt nmos pass transistor to realize.
In differential reference voltage buffer of the present invention, control section and host buffer part are according to input voltage size and preferably by negative feedback, produce two bias voltages, and this bias voltage is delivered to and copied buffer portion after preferably using large capacitor decoupling.Copy buffer portion and utilize two reference voltages of this bias voltage output.Owing to copying buffer portion, be open loop circuit, therefore there is response speed and stronger capacitance drive capability faster.Each buffer portion all comprises two source followers, and its shared road bias current, thereby has greatly saved power consumption expense.
Accompanying drawing explanation
The circuit diagram that accompanying drawing 1 is differential reference voltage buffer of the present invention;
Accompanying drawing 2 is the circuit diagram of an embodiment of the Full differential operational amplifier 10 in control section;
Accompanying drawing 3 is the circuit diagram of an embodiment of the common mode feedback circuit 11 in control section;
Accompanying drawing 4 is the circuit diagram of another embodiment of the common mode feedback circuit 11 in control section;
Embodiment
Below in conjunction with accompanying drawing to a preferred embodiment of the present invention will be described in detail.
Fig. 1 is the circuit diagram of differential reference voltage buffer of the present invention, and as shown in Figure 1, it comprises control section 1, host buffer part 2 and copy buffer portion 3 these three parts, and host buffer part 2 is serially connected with control section 1 and copies between buffer portion 3.
Resistance R
1and R
2one end is received for example gnd and reference voltage Vr, and the other end is connected to the input of Full differential operational amplifier 10 to form " virtual earth ", thereby line 13 meets following formula with the voltage on line 14:
Thereby have:
Because two inputs of common mode feedback circuit 11 are received respectively on line 13 and 14, thus common mode feedback circuit 11 can forced line 13 and line 14 on the average of voltage equal outside input common mode electrical level V received on line 15
cm, therefore have:
V
13+V
14＝2V
cm
Therefore line 13 with the voltage on line 14 is:
Host buffer partly comprises three nmos pass transistor M
1, M
2and M
3.M
1as source follower, come the voltage on output line 13, M
2as the voltage on source follower output line 14, M
3be current source transistor, adopt nmos pass transistor can realize larger mutual conductance.M
1, M
2grid end 17 and 16 be connected to respectively control section 1 the positive-negative output end of Full differential operational amplifier 10 to form close loop negative feedback, M
1with M
2the voltage of grid end determined by the output of the Full differential operational amplifier 10 of control section 1, and its size is:
V
17＝V
13+V
GS1
V
16＝V
14+V
GS2
On line 16 and line 17, can connect one group of decoupling capacitor 20, this group electric capacity will greatly reduce the impedance of line 16 and line 17 under high frequency situations, thereby reduce noise.
Two source follower M of host buffer part 2
1and M
2share M
3the bias current providing, thus power consumption expense significantly reduced.
Copy buffer portion 3 and comprise three transistor M
4, M
5and M
6.M
4as source follower, carry out the reference voltage V on output line 31
refp, M
5as the negative reference voltage V on source follower output line 30
refn, M
6it is current source transistor.Identical with host buffer part 2, M
4and M
5the bias voltage of grid end is brought in and is provided by positive and negative two outputs of the Full differential operational amplifier 10 of control section 1 equally.Yet different from host buffer part 2: two reference voltages that copy buffer portion 3 outputs do not feed back to the input of the Full differential operational amplifier 10 of control section 1.In other words, copy buffer portion 3 and work in open loop situations, thereby there is response speed faster.V under stable state
refpand V
refnvalue be:
V
refp＝V
17-V
GS4＝V
13+V
GS1-V
GS4
V
refn＝V
16+V
GS5＝V
14+V
GS2-V
GS5
When design, the dimension scale that copies buffer portion 3 and the source follower transistor of host buffer part 2 can be identical with the dimension scale of current source transistor, so V
gS1=V
gS4, V
gS2=V
gS5thereby, two reference voltage V of output
refpand V
refnvalue equate with the magnitude of voltage on line 13, line 14, that is:
In addition on the one hand, copy two source follower M of buffer portion 3
4and M
5share M
6the bias current providing, thus power consumption expense significantly reduced.
Fig. 2 is the circuit diagram of an embodiment of the Full differential operational amplifier 10 in control section 1.This amplifier adopts classical current mirror type structure, and its positive-negative input end is differential pair M '
1, M '
2grid end.Input voltage is by differential pair M '
1, M '
2transfer to after electric current by current mirror M '
5, M '
6mirror image output.The current source transistor M ' that the common-mode feedback input of this Full differential operational amplifier is output
7, M '
8grid end.
Fig. 3 is the circuit diagram of an embodiment of the common mode feedback circuit 11 in control section 1.
As shown in Figure 3, common mode feedback circuit 11 comprises operational amplifier 113 and is connected respectively to the first resistance 110 and second resistance 111 of the positive input terminal of operational amplifier 113, the first resistance 110 is identical with the second resistance 111 values, and its other end will receive respectively center line 13 and the voltage on line 14 of control section 1 and it be averaged and delivers to line 112.The negative input end of operational amplifier 113 is the common mode electrical level input of common mode feedback circuit 11, and the output of described operational amplifier 113 is the output of described common mode feedback circuit 11, and operational amplifier 113 is the common-mode voltage V with outside input by the voltage on line 112
cmcompare, and by output, control the common-mode feedback end of Full differential operational amplifier 10.After loop stability, the voltage on line 112 will and V
cmequate.
Fig. 4 is the circuit diagram of the another one embodiment of the common mode feedback circuit 11 in control section 1.
As shown in Figure 4, common mode feedback circuit comprises by the 7th transistor M "
1with the 8th transistor M "
2the first difference forming and by the 9th transistor M "
3with the tenth transistor M "
4the second differential pair forming, the 8th transistor M "
2with the 9th transistor M "
3grid be connected and this grid is the common mode electrical level input of common mode feedback circuit 11, the 8th transistor M "
2with the 9th transistor M "
3drain electrode be connected and be connected to the 11 transistor M "
5drain electrode, the 11 transistor M "
5grid be connected to and drain and be the output of common mode feedback circuit 11.
The 7th transistor M "
1with the tenth transistor M "
4grid be respectively the positive-negative input end of common mode feedback circuit 11, M "
1and M "
4to receive from the voltage on control section center line 13 and line 14 and by differential pair M "
1, M "
2and M "
3, M "
4to the voltage receiving average and with the common-mode voltage V of outside input
cmrelatively, then by output, control the common-mode feedback end of Full differential operational amplifier 10.After loop stability, on line 13 and line 14, the mean value of voltage equals V
cm.
The foregoing is only the preferred embodiments of the present invention; the present invention is not limited to above-mentioned particular implementation example; do not deviating under spirit of the present invention and real situation thereof; skilled personnel can make according to the present invention various corresponding changes and distortion, but these corresponding changes and distortion all should belong to claims protection range of the present invention within.
Claims (10)
1. a differential reference voltage buffer, comprise: control section (1), host buffer part (2) and copy buffer portion (3), described host buffer part (2) is serially connected with control section (1) and copies between buffer portion (3), wherein
Described control section (1) comprises Full differential operational amplifier (10) and common mode feedback circuit (11), and the output of described common mode feedback circuit (11) is connected to the common-mode feedback input of described Full differential operational amplifier (10);
Described host buffer part (2) comprises the first transistor and the transistor seconds of series connection, described the first transistor and transistor seconds share a road bias current, the positive-negative output end of described Full differential operational amplifier (10) is connected to respectively the grid of described the first transistor and transistor seconds, and the source electrode of described the first transistor and transistor seconds is connected to the input of described common mode feedback circuit (11);
Describedly copy the 4th transistor and the 5th transistor that buffer portion (3) comprises series connection, described the 4th transistor and the 5th transistor share a road bias current, described the 4th transistor and the 5th transistorized grid are connected to respectively the grid of described the first transistor and transistor seconds, and described the 4th transistor and the 5th transistorized source electrode are exported respectively positive and negative two reference voltages.
2. differential reference voltage buffer as claimed in claim 1, it is characterized in that, the source electrode that the positive-negative input end of described Full differential operational amplifier (10) is used for being received input reference voltage and being connected to described the first transistor and transistor seconds by the third and fourth resistance respectively by the first and second resistance is respectively to form negative feedback.
3. differential reference voltage buffer as claimed in claim 1, it is characterized in that, described common mode feedback circuit (11) has positive and negative two inputs, a common mode electrical level input, described common mode electrical level input is in order to receive the common-mode voltage of outside input, and described common mode feedback circuit (11) forces the described the first transistor of described host buffer part and the first voltage of the source electrode output of transistor seconds and the average of second voltage to equal described common-mode voltage.
4. differential reference voltage buffer as claimed in claim 3, it is characterized in that, described common mode feedback circuit (11) comprises operational amplifier (113) and is connected respectively to the 5th resistance and the 6th resistance of the positive input terminal of described operational amplifier (113), the other end of described the 5th resistance and the 6th resistance is respectively the positive-negative input end of described common mode feedback circuit (11), the negative input end of described operational amplifier (113) is the common mode electrical level input of described common mode feedback circuit (11), the output of described operational amplifier (113) is the output of described common mode feedback circuit (11).
5. differential reference voltage buffer as claimed in claim 3, it is characterized in that, described common mode feedback circuit (11) comprises the first differential pair consisting of the 7th transistor and the 8th transistor and the second differential pair consisting of the 9th transistor and the tenth transistor, described the 8th transistor is connected with the 9th transistorized grid and this grid is the common mode electrical level input of common mode feedback circuit (11), described the 8th transistor is connected and is connected to the 11 transistorized drain electrode with the 9th transistorized drain electrode, described the 11 transistorized grid is connected to and drains and be the output of common mode feedback circuit (11), described the 7th transistor and the tenth transistorized grid are respectively the positive-negative input end of described common mode feedback circuit (11).
6. differential reference voltage buffer as claimed in claim 1, it is characterized in that, described host buffer part (2) also comprises the 3rd transistor, and described the first transistor is connected between power supply and transistor seconds, and the 3rd transistor is connected between transistor seconds and ground.
7. differential reference voltage buffer as claimed in claim 1, it is characterized in that, described host buffer part (2) also comprises decoupling capacitor (20), and described decoupling capacitor is connected to respectively between power supply and the grid of the first transistor, between the first transistor and the grid of transistor seconds and between transistor seconds and ground.
8. differential reference voltage buffer as claimed in claim 1, is characterized in that, the first transistor in described host buffer part (2) and transistor seconds share a road bias current, and all adopts nmos pass transistor to realize.
9. differential reference voltage buffer as claimed in claim 1, it is characterized in that, the described buffer portion (3) that copies also comprises the 6th transistor, and described the 4th transistor is connected between power supply and the 5th transistor, and the 6th transistor is connected between the 5th transistor and ground.
10. differential reference voltage buffer as claimed in claim 1, is characterized in that, described in copy the 4th transistor in buffer portion (3) and the 5th transistor shares a road bias current, and all adopt nmos pass transistor to realize.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110397553.1A CN102412824B (en) | 2011-12-02 | 2011-12-02 | Differential reference voltage buffer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110397553.1A CN102412824B (en) | 2011-12-02 | 2011-12-02 | Differential reference voltage buffer |
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| CN102412824B true CN102412824B (en) | 2014-01-15 |
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Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103036578B (en) * | 2012-12-25 | 2014-11-12 | 上海贝岭股份有限公司 | Transmitting terminal circuit for high speed digital communication |
| CN103888093B (en) * | 2014-04-17 | 2017-04-19 | 苏州坤信微电子科技有限公司 | Common-mode level reset circuit for differential signals |
| CN104270150B (en) * | 2014-09-17 | 2017-09-15 | 东南大学 | High-speed low-power-consumption reference voltage output buffer applied to production line analog-digital converter |
| CN107534440B (en) * | 2015-04-02 | 2018-12-25 | 美高森美半导体无限责任公司 | universal input buffer |
| CN106230433A (en) * | 2016-09-20 | 2016-12-14 | 天津大学 | High-speed-differential Voltage Reference Buffer |
| CN106487374B (en) * | 2016-12-31 | 2022-09-20 | 唯捷创芯(天津)电子技术股份有限公司 | High-speed analog voltage signal buffer, chip and communication terminal |
| CN108874006B (en) * | 2017-05-10 | 2020-03-24 | 深圳清华大学研究院 | Reference voltage driving circuit |
| US9997230B1 (en) * | 2017-06-20 | 2018-06-12 | Elite Semiconductor Memory Technology Inc. | Reference voltage pre-processing circuit and reference voltage pre-processing method for a reference voltage buffer |
| US10367486B2 (en) * | 2017-10-26 | 2019-07-30 | Linear Technology Holding Llc | High speed on-chip precision buffer with switched-load rejection |
| CN110603732B (en) * | 2018-04-12 | 2023-05-26 | 深圳市汇顶科技股份有限公司 | Operational amplifier and control method thereof |
| CN108958345B (en) * | 2018-08-23 | 2020-08-07 | 中国电子科技集团公司第二十四研究所 | Differential reference voltage buffer |
| TWI696347B (en) * | 2019-05-02 | 2020-06-11 | 九暘電子股份有限公司 | Common mode voltage level shifting and locking circuit |
| CN114153263B (en) * | 2021-11-30 | 2023-01-24 | 杭州海康威视数字技术股份有限公司 | Low-voltage differential signaling LVDS transmitter, chip, LVDS interface and terminal equipment |
| CN116470910B (en) * | 2023-06-16 | 2024-01-23 | 深圳前海深蕾半导体有限公司 | Current-mode audio frequency digital-to-analog converter |
| CN117294298B (en) * | 2023-09-19 | 2024-07-02 | 苏州纳芯微电子股份有限公司 | Buffer circuit and driving device |
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| CN202395750U (en) * | 2011-12-02 | 2012-08-22 | 上海贝岭股份有限公司 | Differential reference voltage buffer |
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| US7327166B2 (en) * | 2005-08-18 | 2008-02-05 | Texas Intruments Incorporated | Reference buffer with improved drift |
| US7750737B2 (en) * | 2007-09-05 | 2010-07-06 | Texas Instruments Incorporated | Common mode stabilization in a fully differential amplifier |
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| CN101533285B (en) * | 2009-03-31 | 2011-10-19 | 炬力集成电路设计有限公司 | A reference voltage buffer circuit |
| CN101969297B (en) * | 2010-09-30 | 2012-11-21 | 苏州思瑞浦微电子科技有限公司 | Continuous-time common-mode feedback circuit for fully-differential operational amplifier circuit |
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| CN202395750U (en) * | 2011-12-02 | 2012-08-22 | 上海贝岭股份有限公司 | Differential reference voltage buffer |
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Inventor after: Ding Xuexin Inventor after: Zhang Hui Inventor after: Li Dan Inventor after: Liu Yanhai Inventor after: Lv Haifeng Inventor before: Ding Xuexin Inventor before: Zhang Hui Inventor before: Li Dan Inventor before: Liu Yanhai Inventor before: Lv Haifeng |