CN106292818B - Fully differential generating circuit from reference voltage and Wireless Telecom Equipment suitable for pipeline ADC - Google Patents

Fully differential generating circuit from reference voltage and Wireless Telecom Equipment suitable for pipeline ADC Download PDF

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CN106292818B
CN106292818B CN201610710476.3A CN201610710476A CN106292818B CN 106292818 B CN106292818 B CN 106292818B CN 201610710476 A CN201610710476 A CN 201610710476A CN 106292818 B CN106292818 B CN 106292818B
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switching tube
switch
electrically connected
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resistor
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CN106292818A (en
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晋超超
刘马良
刘术彬
朱樟明
杨银堂
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Xidian University
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Xidian University
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters

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Abstract

The present invention relates to a kind of fully differential generating circuit from reference voltage and Wireless Telecom Equipment suitable for pipeline ADC.The fully differential generating circuit from reference voltage 10, including：Initial reference voltage input VREF, power end VDD, earth terminal GND, Full differential operational amplifier A1, the first level shifter V1, second electrical level shift unit V2, common mode feedback circuit CMFB, first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6 and first switch pipe M1, second switch pipe M2.The embodiment of the present invention can realize preferable PSRR, with good stability, and can be quickly established to stable state.The reference voltage of the high amplitude of oscillation is exported simultaneously.

Description

Fully-differential reference voltage generation circuit suitable for pipeline ADC (analog to digital converter) and wireless communication equipment
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a fully-differential reference voltage generation circuit suitable for a pipeline ADC (analog to digital converter) and wireless communication equipment.
Background
With the rapid development of video and wireless communication technologies, wireless communication devices have placed more stringent requirements on the performance of Analog-to-digital converters (ADCs). The ADC also needs to have good alternating current performance and intermediate frequency sampling capability under the condition of meeting the requirements of high speed and high precision. The ADC with the pipeline structure, namely the pipeline ADC can achieve good compromise in the aspects of sampling rate, conversion precision, power consumption and the like, so that the ADC is widely applied to the field of high speed and high precision.
In the pipelined ADC, the reference voltage generating circuit has two roles: (1) providing threshold voltages of comparators in each stage of pipeline structure; (2) a reference voltage is provided when a multiplication margin gain (MDAC) is subtracted. The reference voltage requires very large drive capability and is quickly set up to a steady state, thereby ensuring a quick set up of the MDAC. With the continuous improvement of the sampling rate and the precision of the pipeline ADC, the performance of the reference voltage has more obvious influence on the conversion performance of the ADC.
The conventional reference voltage generating circuit usually employs two single-ended operational amplifiers and a high-speed voltage buffer (buffer) to output the reference voltage. However, the output swing of the reference voltage is limited, and the reference voltage is easily affected by respective offset of the two single-ended operational amplifiers, so that the output reference voltage is skewed.
Therefore, there is a need for a new reference voltage generation circuit that has good stability and can quickly establish a stable state while achieving a high swing output of the reference voltage.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a fully differential reference voltage generating circuit and a wireless communication device suitable for a pipelined ADC, which can achieve a better Power Supply Rejection Ratio (PSRR), have good stability, and can be quickly set up to a stable state. And meanwhile, outputting a high-swing reference voltage.
One embodiment of the present invention provides a fully differential reference voltage generation circuit 10 suitable for a pipelined ADC, comprising: initial reference voltage input terminal VREFThe circuit comprises a power supply terminal VDD, a ground terminal GND, a fully differential operational amplifier A1, a first level shifter V1, a second level shifter V2, a common mode feedback circuit CMFB, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first switch tube M1 and a second switch tube M2; wherein,
the first switch tube M1, the fifth resistor R5, the sixth resistor R6 and the second switch tube M2 are sequentially connected in series between the power terminal VDD and the ground terminal GND;
the first resistor R1 and the second resistor R2 are sequentially connected in series between the ground terminal GND and a node formed by the first switch tube M1 and the fifth resistor R5 in series; the third resistor R3 and the fourth resistor R4 are sequentially connected in series with the initial reference voltage input end VREFThe node formed by connecting the sixth resistor R6 and the second switch tube M2 in series is arranged between the nodes;
a positive input terminal Vin + of the fully differential operational amplifier a1 is electrically connected to a node a formed by connecting the first resistor R1 and the second resistor R2 in series, a negative input terminal Vin-is electrically connected to a node B formed by connecting the third resistor R3 and the fourth resistor R4 in series, a negative output terminal Vout-and the first level shifter V1 are sequentially connected to the control terminal of the first switch tube M1 in series, and a positive output terminal Vout + and the second level shifter V2 are sequentially connected to the control terminal of the second switch tube M2 in series;
the input end of the common mode feedback circuit CMFB is electrically connected to the node C formed by the series connection of the fifth resistor R5 and the sixth resistor R6, and the output end thereof is electrically connected to the fully differential operational amplifier a 1.
In an embodiment of the present invention, the first switch transistor M1 is an NMOS transistor, and the second switch transistor M2 is a PMOS transistor.
In one embodiment of the invention, the source end of the NMOS tube is connected with the substrate end of the NMOS tube; and the source end of the PMOS tube is connected with the substrate end of the PMOS tube.
In one embodiment of the present invention, the present invention further includes a third capacitor C3 and a fourth capacitor C4; one end of the third capacitor C1 is electrically connected to the control terminal of the first switch transistor M1 and the other end is electrically connected to the ground terminal GND; one end of the fourth capacitor C4 is electrically connected to the control terminal of the second switch transistor M2 and the other end is electrically connected to the ground GND.
In one embodiment of the present invention, the fully differential operational amplifier a1 includes: a third switching tube M3, a fourth switching tube M4, a fifth switching tube M5, a sixth switching tube M6, a seventh switching tube M7, an eighth switching tube M8, a ninth switching tube M9, a tenth switching tube M10, an eleventh switching tube M11, a twelfth switching tube M12, a thirteenth switching tube M13, a fourteenth switching tube M14, a fifteenth switching tube M15, a sixteenth switching tube M16, a seventeenth switching tube M17 and an eighteenth switching tube M18; wherein,
the third switching tube M3, the fourth switching tube M4 and the eighth switching tube M8 are sequentially connected in series between the power supply end VDD and the ground end GND, a control end of the third switching tube M3 is electrically connected to a first bias voltage Vb1, a control end of the fourth switching tube M4 is electrically connected to the negative input end Vin-, and a control end of the eighth switching tube M8 is electrically connected to a node formed by connecting the fourth switching tube M4 and the eighth switching tube M8 in series;
the fifth switching tube M5 and the ninth switching tube M9 are sequentially connected in series between a node formed by connecting the third switching tube M3 and the fourth switching tube M4 in series and the ground terminal GND, the control end of the fifth switching tube M5 is electrically connected to the positive input terminal Vin +, and the control end of the ninth switching tube M9 is electrically connected to a node formed by connecting the fifth switching tube M5 and the ninth switching tube M9 in series;
the transmission end of the sixth switching tube M6 is electrically connected to the node Y formed by the fifth switching tube M5 and the ninth switching tube M9 connected in series and the ground GND respectively, and the control end of the sixth switching tube M6 is electrically connected to the control end of the eighth switching tube M8; the transmission end of the seventh switching tube M7 is electrically connected to the node X formed by the serial connection of the fourth switching tube M4 and the eighth switching tube M8 and the ground GND respectively, and the control end of the seventh switching tube M7 is electrically connected to the control end of the ninth switching tube M9;
the seventeenth switch tube M17, the fifteenth switch tube M15, the thirteenth switch M13, the eleventh switch M11 and the tenth switch tube M10 are sequentially connected in series between the power terminal VDD and the ground terminal GND, the control end of the seventeenth switch tube M17 is electrically connected to the second bias voltage Vb2, the control end of the fifteenth switch tube M15 is electrically connected to the third bias voltage Vb3, the control end of the thirteenth switching tube M13 is electrically connected to a fourth bias voltage Vb4, the control end of the eleventh switching tube M11 is electrically connected to a node X formed by the fourth switching tube M4 and the eighth switching tube M8 connected in series, the control end of the tenth switching tube M10 is electrically connected to the input end of the common mode feedback circuit CMFB, the negative output end Vout-is electrically connected to a node formed by the fifteenth switch tube M15 and the thirteenth switch M13 connected in series;
the eighteenth switching tube M18, the sixteenth switching tube M16, the fourteenth switching tube M14 and the twelfth switching tube M12 are sequentially connected in series between the power source terminal VDD and a node formed by connecting the eleventh switching tube M11 and the tenth switching tube M10 in series, the control terminal of the eighteenth switching tube M18 is electrically connected to the second bias voltage Vb2, the control terminal of the sixteenth switching tube M16 is electrically connected to the third bias voltage Vb3, the control terminal of the fourteenth switching tube M14 is electrically connected to the fourth bias voltage Vb4, the twelfth switching tube M12 is electrically connected to a node Y formed by connecting the fifth switching tube M5 and the ninth switching tube M9 in series, and the positive output terminal Vout + is electrically connected to a node formed by connecting the sixteenth switching tube M16 and the fourteenth switching tube M14 in series.
In an embodiment of the present invention, the third switching tube M3, the fourth switching tube M4, the fifth switching tube M5, the fifteenth switching tube M15, the sixteenth switching tube M16, the seventeenth switching tube M17, and the eighteenth switching tube M18 are PMOS tubes, and the sixth switching tube M6, the seventh switching tube M7, the eighth switching tube M8, the ninth switching tube M9, the tenth switching tube M10, the eleventh switching tube M11, the twelfth switching tube M12, the thirteenth switching tube M13, and the fourteenth switching tube M14 are NMOS tubes.
In one embodiment of the present invention, the first level shifter V1 includes: a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a first capacitor C1, a fifth capacitor C5 and a first direct current power supply Vbp 1; wherein the first switch K1 and the second switch K2 are sequentially connected in series between the first direct current power supply Vbp1 and the negative output terminal Vout-of the fully differential operational amplifier a1, and the third switch K3 and the fourth switch K4 are sequentially connected in series between the power supply terminal VDD and the control terminal of the first switch tube M1; one end of the first capacitor C1 is electrically connected to the negative output terminal Vout-of the fully differential operational amplifier a1 and the other end is electrically connected to the control terminal of the first switch transistor M1, one end of the fifth capacitor C5 is electrically connected to a node formed by the first switch K1 and the second switch K2 connected in series and the other end is electrically connected to a node formed by the third switch K3 and the fourth switch K4 connected in series.
In one embodiment of the present invention, the second level shifter V2 includes: a fifth switch K5, a sixth switch K6, a seventh switch K7, an eighth switch K8, a second capacitor C2, a sixth capacitor C6, and a second dc power supply Vbn 1; the fifth switch K5 and the sixth switch K6 are sequentially connected in series between the second dc power supply Vbn1 and the positive output terminal Vout + of the fully differential operational amplifier a1, and the seventh switch K7 and the eighth switch K8 are sequentially connected in series between the ground terminal GND and the control terminal of the second switch tube M2; one end of the second capacitor C2 is electrically connected to the positive output terminal Vout + of the fully differential operational amplifier a1 and the other end is electrically connected to the control terminal of the second switch transistor M2, one end of the sixth capacitor C6 is electrically connected to a node formed by the series connection of the fifth switch K5 and the sixth switch K6 and the other end is electrically connected to a node formed by the series connection of the seventh switch K7 and the eighth switch K8.
In one embodiment of the present invention, further comprising: a nineteenth switching tube M19, a twentieth switching tube M20, a seventh resistor R7 and an eighth resistor R8; the nineteenth switch tube M19, the seventh resistor R7, the eighth resistor R8 and the twentieth switch tube M20 are sequentially connected in series between the power supply terminal VDD and the ground terminal GND, the control terminal of the nineteenth switch tube M19 is electrically connected to the control terminal of the first switch tube M1, the control terminal of the twentieth switch tube M20 is electrically connected to the control terminal of the second switch tube M2, and a node formed by connecting the nineteenth switch tube M19 and the seventh resistor R7 in series outputs a reference voltage high level HVREFA node output reference voltage low level LV formed by connecting the eighth resistor R8 and the twentieth switching tube M20 in seriesREF。
Another embodiment of the present invention provides a wireless communication device comprising an analog-to-digital converter, wherein the analog-to-digital converter comprises the fully-differential reference voltage generating circuit 10 according to any of the above embodiments.
Compared with the prior art, the invention has the beneficial effects that:
(1) the output buffer of the fully differential reference voltage generation circuit is realized by only a source follower consisting of transistors M1 and M2, has simple circuit structure and can be used as a reference voltage HVREFAnd LVREFA large drive current is provided to achieve faster reference voltage settling.
(2) The fully differential operational amplifier A1 in the fully differential reference voltage generation circuit of the present invention forms a positive feedback loop by using the transistors M6-M9, thereby obtaining a very large DC open loop voltage gain, providing a sufficiently large loop gain available for the feedback loop of the fully differential reference voltage generation circuit.
(3) The loop gain of the fully differential reference voltage generation circuit is a very low value due to the attenuation of the series capacitance and the feedback factor. The fully differential reference voltage generating circuit has good stability and can be quickly established to a stable state, so that the quick establishment of MDAC is ensured.
(4) The reference voltage generating circuit adopts a fully differential structure, can effectively resist the influence of common-mode noise, and can output high-swing reference voltage.
Drawings
Fig. 1 is a schematic circuit diagram of a fully differential reference voltage generation circuit suitable for a pipelined ADC according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of another fully-differential reference voltage generation circuit suitable for a pipelined ADC according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a fully differential operational amplifier according to an embodiment of the present invention;
fig. 4 is a schematic circuit diagram of a first level shifter according to an embodiment of the present invention;
fig. 5 is a schematic circuit diagram of a second level shifter according to an embodiment of the present invention;
fig. 6 is a schematic circuit diagram of a fully differential reference voltage generating circuit suitable for a pipelined ADC according to an embodiment of the present invention;
fig. 7 is a schematic circuit diagram of a level shifter according to an embodiment of the present invention;
fig. 8 is a schematic diagram of an ac equivalent circuit of a fully differential reference voltage generating circuit suitable for a pipeline ADC according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1 to 6, fig. 1 is a schematic circuit structure diagram of a fully differential reference voltage generating circuit suitable for a pipeline ADC according to an embodiment of the present invention, fig. 2 is a schematic circuit structure diagram of another fully differential reference voltage generating circuit suitable for a pipeline ADC according to an embodiment of the present invention, fig. 3 is a schematic circuit structure diagram of a fully differential operational amplifier according to an embodiment of the present invention, fig. 4 is a schematic circuit structure diagram of a first level shifter according to an embodiment of the present invention, fig. 5 is a schematic circuit structure diagram of a second level shifter according to an embodiment of the present invention, and fig. 6 is a schematic circuit structure diagram of another fully differential reference voltage generating circuit suitable for a pipeline ADC according to an embodiment of the present invention.
Specifically, referring to fig. 1, the fully differential reference voltage generating circuit 10 includes: initial reference voltage input terminal VREFThe circuit comprises a power supply terminal VDD, a ground terminal GND, a fully differential operational amplifier A1, a first level shifter V1, a second level shifter V2, a common mode feedback circuit CMFB, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first switch tube M1 and a second switch tube M2; the first switch tube M1, the fifth resistor R5, the sixth resistor R6 and the second switch tube M2 are sequentially connected in series between the power supply terminal VDD and the ground terminal GND; the first resistor R1 and the second resistor R2 are sequentially connected in series between the ground terminal GND and a node formed by the first switch tube M1 and the fifth resistor R5 in series; the third resistor R3 and the fourth resistor R4 are sequentially connected in series to the initial reference voltageInput terminal VREFThe node formed by connecting the sixth resistor R6 and the second switch tube M2 in series is arranged between the nodes; a positive input terminal Vin + of the fully differential operational amplifier a1 is electrically connected to a node a formed by connecting the first resistor R1 and the second resistor R2 in series, a negative input terminal Vin-is electrically connected to a node B formed by connecting the third resistor R3 and the fourth resistor R4 in series, a negative output terminal Vout-and the first level shifter V1 are sequentially connected to the control terminal of the first switch tube M1 in series, and a positive output terminal Vout + and the second level shifter V2 are sequentially connected to the control terminal of the second switch tube M2 in series; the input end of the common mode feedback circuit CMFB is electrically connected to the node C formed by the series connection of the fifth resistor R5 and the sixth resistor R6, and the output end thereof is electrically connected to the fully differential operational amplifier a 1.
Optionally, the first switch transistor M1 is an NMOS transistor, and the second switch transistor M2 is a PMOS transistor. Further, the source end of the NMOS tube is connected with the substrate end of the NMOS tube; and the source end of the PMOS tube is connected with the substrate end of the PMOS tube.
Preferably, referring to fig. 2, the fully differential reference voltage generating circuit 10 further includes a third capacitor C3 and a fourth capacitor C4; one end of the third capacitor C1 is electrically connected to the control terminal of the first switch transistor M1 and the other end is electrically connected to the ground terminal GND; one end of the fourth capacitor C4 is electrically connected to the control terminal of the second switch transistor M2 and the other end is electrically connected to the ground GND.
Alternatively, referring to fig. 3, the fully differential operational amplifier a1 includes: a third switching tube M3, a fourth switching tube M4, a fifth switching tube M5, a sixth switching tube M6, a seventh switching tube M7, an eighth switching tube M8, a ninth switching tube M9, a tenth switching tube M10, an eleventh switching tube M11, a twelfth switching tube M12, a thirteenth switching tube M13, a fourteenth switching tube M14, a fifteenth switching tube M15, a sixteenth switching tube M16, a seventeenth switching tube M17 and an eighteenth switching tube M18; wherein,
the third switching tube M3, the fourth switching tube M4 and the eighth switching tube M8 are sequentially connected in series between the power supply end VDD and the ground end GND, a control end of the third switching tube M3 is electrically connected to a first bias voltage Vb1, a control end of the fourth switching tube M4 is electrically connected to the negative input end Vin-, and a control end of the eighth switching tube M8 is electrically connected to a node formed by connecting the fourth switching tube M4 and the eighth switching tube M8 in series;
the fifth switching tube M5 and the ninth switching tube M9 are sequentially connected in series between a node formed by connecting the third switching tube M3 and the fourth switching tube M4 in series and the ground terminal GND, the control end of the fifth switching tube M5 is electrically connected to the positive input terminal Vin +, and the control end of the ninth switching tube M9 is electrically connected to a node formed by connecting the fifth switching tube M5 and the ninth switching tube M9 in series;
the transmission end of the sixth switching tube M6 is electrically connected to the node Y formed by the fifth switching tube M5 and the ninth switching tube M9 connected in series and the ground GND respectively, and the control end of the sixth switching tube M6 is electrically connected to the control end of the eighth switching tube M8; the transmission end of the seventh switching tube M7 is electrically connected to the node X formed by the serial connection of the fourth switching tube M4 and the eighth switching tube M8 and the ground GND respectively, and the control end of the seventh switching tube M7 is electrically connected to the control end of the ninth switching tube M9;
the seventeenth switch tube M17, the fifteenth switch tube M15, the thirteenth switch M13, the eleventh switch M11 and the tenth switch tube M10 are sequentially connected in series between the power terminal VDD and the ground terminal GND, the control end of the seventeenth switch tube M17 is electrically connected to the second bias voltage Vb2, the control end of the fifteenth switch tube M15 is electrically connected to the third bias voltage Vb3, the control end of the thirteenth switching tube M13 is electrically connected to a fourth bias voltage Vb4, the control end of the eleventh switching tube M11 is electrically connected to a node X formed by the fourth switching tube M4 and the eighth switching tube M8 connected in series, the control end of the tenth switching tube M10 is electrically connected to the input end of the common mode feedback circuit CMFB, the negative output end Vout-is electrically connected to a node formed by the fifteenth switch tube M15 and the thirteenth switch M13 connected in series;
the eighteenth switching tube M18, the sixteenth switching tube M16, the fourteenth switching tube M14 and the twelfth switching tube M12 are sequentially connected in series between the power source terminal VDD and a node formed by connecting the eleventh switching tube M11 and the tenth switching tube M10 in series, the control terminal of the eighteenth switching tube M18 is electrically connected to the second bias voltage Vb2, the control terminal of the sixteenth switching tube M16 is electrically connected to the third bias voltage Vb3, the control terminal of the fourteenth switching tube M14 is electrically connected to the fourth bias voltage Vb4, the twelfth switching tube M12 is electrically connected to a node Y formed by connecting the fifth switching tube M5 and the ninth switching tube M9 in series, and the positive output terminal Vout + is electrically connected to a node formed by connecting the sixteenth switching tube M16 and the fourteenth switching tube M14 in series.
Wherein the third switching tube M3, the fourth switching tube M4, the fifth switching tube M5, the fifteenth switching tube M15, the sixteenth switching tube M16, the seventeenth switching tube M17 and the eighteenth switching tube M18 are PMOS tubes, and the sixth switching tube M6, the seventh switching tube M7, the eighth switching tube M8, the ninth switching tube M9, the tenth switching tube M10, the eleventh switching tube M11, the twelfth switching tube M12, the thirteenth switching tube M13 and the fourteenth switching tube M14 are NMOS tubes.
Optionally, referring to fig. 4, the first level shifter V1 includes: a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a first capacitor C1, a fifth capacitor C5 and a first direct current power supply Vbp 1; wherein the first switch K1 and the second switch K2 are sequentially connected in series between the first direct current power supply Vbp1 and the negative output terminal Vout-of the fully differential operational amplifier a1, and the third switch K3 and the fourth switch K4 are sequentially connected in series between the power supply terminal VDD and the control terminal of the first switch tube M1; one end of the first capacitor C1 is electrically connected to the negative output terminal Vout-of the fully differential operational amplifier a1 and the other end is electrically connected to the control terminal of the first switch transistor M1, one end of the fifth capacitor C5 is electrically connected to a node formed by the first switch K1 and the second switch K2 connected in series and the other end is electrically connected to a node formed by the third switch K3 and the fourth switch K4 connected in series.
Optionally, referring to fig. 5, the second level shifter V2 includes: a fifth switch K5, a sixth switch K6, a seventh switch K7, an eighth switch K8, a second capacitor C2, a sixth capacitor C6, and a second dc power supply Vbn 1; the fifth switch K5 and the sixth switch K6 are sequentially connected in series between the second dc power supply Vbn1 and the positive output terminal Vout + of the fully differential operational amplifier a1, and the seventh switch K7 and the eighth switch K8 are sequentially connected in series between the ground terminal GND and the control terminal of the second switch tube M2; one end of the second capacitor C2 is electrically connected to the positive output terminal Vout + of the fully differential operational amplifier a1 and the other end is electrically connected to the control terminal of the second switch transistor M2, one end of the sixth capacitor C6 is electrically connected to a node formed by the series connection of the fifth switch K5 and the sixth switch K6 and the other end is electrically connected to a node formed by the series connection of the seventh switch K7 and the eighth switch K8.
Optionally, referring to fig. 6, the fully differential reference voltage generating circuit 10 further includes: a nineteenth switching tube M19, a twentieth switching tube M20, a seventh resistor R7 and an eighth resistor R8; the nineteenth switch tube M19, the seventh resistor R7, the eighth resistor R8 and the twentieth switch tube M20 are sequentially connected in series between the power supply terminal VDD and the ground terminal GND, the control terminal of the nineteenth switch tube M19 is electrically connected to the control terminal of the first switch tube M1, the control terminal of the twentieth switch tube M20 is electrically connected to the control terminal of the second switch tube M2, and a node formed by connecting the nineteenth switch tube M19 and the seventh resistor R7 in series outputs a reference voltage high level HVREFA node output reference voltage low level LV formed by connecting the eighth resistor R8 and the twentieth switching tube M20 in seriesREF。
In this embodiment, the output buffer of the fully differential reference voltage generation circuit is implemented by the source follower formed by the transistors M1 and M2, and the circuit has a simple structure and can be the reference voltage HVREFAnd LVREFA large driving current is provided to realize faster reference voltage establishment; the fully differential operational amplifier A1 forms a positive feedback loop by using the transistors M6-M9, thereby obtaining a great DC open loop voltage gain, and providing a sufficiently large loop gain for the feedback loop of the fully differential reference voltage generation circuit; the loop gain of the fully differential reference voltage generation circuit is a very low value due to the attenuation of the series capacitance and the feedback factor. Therefore, the fully differential reference voltage generation circuit has good stability and can be quickly established to a stable state, so that the quick establishment of the MDAC is ensured.
Example two
Referring to fig. 1 to fig. 6 again, and fig. 7 to fig. 8 at the same time, fig. 7 is a schematic circuit diagram of a level shifter according to an embodiment of the present invention; fig. 8 is a schematic circuit diagram of a fully differential reference voltage generation circuit suitable for a pipeline ADC according to an embodiment of the present invention. The present embodiment describes the fully-differential reference voltage generating circuit 10 of the present invention in detail on the basis of the above-described embodiments. The method comprises the following specific steps:
referring to fig. 1, a fully differential reference voltage generating circuit 10 according to an embodiment of the present invention is a closed-loop feedback loop. The closed loop feedback loop is mainly composed of a fully differential operational amplifier A1, 2 level shifters and 2 output buffers. Wherein, the source follower formed by the first transistor M1 and the source follower formed by the second transistor M2 are output buffers. The first transistor M1 is an NMOS transistor, and the second transistor M2 is a PMOS transistor.
The specific circuit connection relationship is as follows:
the positive input terminal Vin + of the fully differential operational amplifier a1 is connected to one end of a first resistor R1, and the other end of the first resistor R1 is grounded. The negative input terminal Vin-of the fully differential operational amplifier A1 is connected to one end of a third resistor R3, and the other end of the third resistor R3 is connected to the initial referenceReference voltage VREF(VREFGenerated by a bandgap reference and reference voltage generating circuit).
The negative output terminal Vout-of the fully differential operational amplifier A1 is connected to one terminal of the first level shifter V1, and the other terminal of the first level shifter V1 is connected to the gate of the first transistor M1. The drain electrode of the first transistor M1 is connected with a power supply voltage; the source and the substrate are connected together to output a reference voltage high level HVREF。
The positive output terminal Vout + of the fully differential operational amplifier a1 is connected to one end of the second level shifter V2, and the other end of the second level shifter V2 is connected to the gate of the second transistor M2. The drain of the second transistor M2 is connected with a power supply voltage; the source is connected to the substrate, and the output reference voltage is low level LVREF。
The source terminals and the substrate of the first transistor M1 and the second transistor M2 are connected together, and nonlinearity caused by Vth is reduced.
The second resistor R2 has one end connected to the positive input terminal vout + of the fully differential operational amplifier a1 and the other end connected to the source of the first transistor M1. One end of the fourth resistor R4 is connected to the negative input terminal Vout "of the fully differential operational amplifier a1, and the other end is connected to the source of the second transistor M2.
One end of the fifth resistor R5 is connected to the source of the first transistor M1, the other end is connected to the sixth resistor R6, and the other end of the sixth resistor R6 is connected to the source of the second transistor M2.
The node C at which the fifth resistor R5 and the sixth resistor R6 are connected together is connected to the input of a common mode feedback Circuit (CMFB) of the fully differential operational amplifier. The output of the common mode feedback Circuit (CMFB) is connected to the gate of the tenth transistor M10 of the fully differential operational amplifier.
The common mode feedback Circuit (CMFB) maintains the common mode value of the output reference voltage at VDD/2.
One end of the third capacitor C3 is connected to the gate of the first transistor M1, and the other end is grounded; one end of the fourth capacitor C4 is connected to the gate of the second transistor M2, and the other end is grounded.
The third capacitor C3 and the fourth capacitor C4 are gate decoupling capacitors. The gate of the first transistor M1 is decoupled to ground by a decoupling capacitor C3 and the gate of the second transistor M2 is decoupled to ground by a decoupling capacitor C4. The structure that the grid electrode is decoupled to the ground through the decoupling capacitor has a good isolation effect, reduces the coupling effect from a power line to an output end, and improves the PSRR of the circuit.
Referring to fig. 1 again, the reference voltage HV of the ADC in this embodiment is high levelREFThe source follower output formed by the first transistor M1, the reference voltage being low by a level LVREFThe source follower output formed by the second transistor M2.
In order to meet the design accuracy requirement of MDAC, the output reference voltage needs to achieve a high output swing, the gate voltage of the first transistor M1 needs to be higher than VDD, and the gate voltage of the second transistor M2 needs to be lower than GND. In order to provide a reasonable dc operating point for the transistors as output buffers, level shifters V1 and V2 are introduced at the positive and negative outputs of the fully differential operational amplifier, respectively.
Referring to fig. 7, the level shifter V1 includes capacitors C1 and C5, wherein one end of the capacitor C5 is connected to or disconnected from the dc voltage Vbp1 through a switch K1, and is connected to or disconnected from one end of the capacitor C1 through a switch K2; the other end of the capacitor C5 is connected to or disconnected from the power supply voltage VDD through a switch K3, and is connected to or disconnected from the other end of the capacitor C1 through a switch K4. One end of the capacitor C1 is also connected to the negative output terminal Vout-of the fully differential operational amplifier, and the other end is also connected to the gate of the first transistor M1.
The level shifter V2 includes capacitors C2 and C6, one end of the capacitor C6 is connected to or disconnected from the dc voltage Vbn1 through a switch K5, and is connected to or disconnected from one end of the capacitor C2 through a switch K6; the other end of the capacitor C6 is connected to or disconnected from ground GND through a switch K7, and is connected to or disconnected from the other end of the capacitor C2 through a switch K8. One end of the capacitor C2 is also connected to the positive output terminal Vout + of the fully differential operational amplifier, and the other end is also connected to the gate of the second transistor M2.
Where Φ 1 and Φ 2 are two-phase non-overlapping clocks of the level shifter, and Vbp1 and Vbn1 are direct current voltages. Phi 1 controls the opening and closing of switches K1, K3, K5 and K7; Φ 2 controls the closing and opening of switches K2, K4, K6, K8.
The level shifter V1 makes the voltage Vout 1-C5 (VDD-Vbp1)/(C1+ C5) higher than the voltage Vout-, and the level shifter V2 makes the voltage Vout1+ C6(Vbn1-0)/(C2+ C6) lower than the voltage Vout +. By adjusting the magnitude of Vbp1 and Vbn1, the first transistor M1 and the second transistor M2, which are output buffers, can be biased at a suitable dc operating point, thereby providing an output current for the output reference voltage.
As described above, the circuit as the output terminal of this embodiment is implemented by only the source follower formed by the transistors M1 and M2, the circuit structure is simple, and it can provide a large driving current for the reference voltages HVREF and LVREF, so as to implement a faster reference voltage establishment. Furthermore, the source follower formed by transistors M1 and M2 has a high input impedance and a low output impedance, and can drive the switched capacitor network in the comparator and the capacitive load in the MDAC.
The structure of the fully differential operational amplifier a1 in the reference voltage generation circuit is described below:
the fully differential operational amplifier adopts a two-stage structure, the first stage of pre-amplification stage utilizes a positive feedback structure to improve the integral gain, and the second stage is an operational amplifier with a sleeve structure.
Referring again to fig. 3, a circuit diagram of the fully differential operational amplifier is shown, in which nodes Vin + and Vin-are respectively the positive and negative input terminals of the operational amplifier, nodes X and Y are respectively the positive and negative output terminals of the pre-amplifier stage, nodes Vout + and Vout-are respectively the positive and negative output terminals of the operational amplifier, and nodes VDD and GND are respectively connected to the power supply voltage and the ground voltage.
The operational amplifier of this embodiment includes: the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the transistors M3-M5, M15-M18 are PMOS transistors, the transistors M6-M14 are NMOS transistors, wherein,
the gate of the third transistor M3 is coupled to the input terminal Vb1 of the first bias voltage, the drain is coupled to the source of the fourth transistor M4 and the source of the fifth transistor M5, and the source of the third transistor M3 is grounded.
The gate of the fourth transistor M4 is coupled to the negative input terminal Vin-, and the drain is coupled to the gate of the sixth transistor M6, the gate of the eighth transistor M8, and the drain of the seventh transistor M7. A source of the fourth transistor M4 is connected to the drain of the third transistor M3 and to the source of the fifth transistor M5.
The gate of the fifth transistor M5 is connected to the positive input terminal Vin +, and the drain is connected to the gate of the seventh transistor M7, the gate of the ninth transistor M9 and the drain of the sixth transistor M6. A source of the fifth transistor M5 is connected to the drain of the third transistor M3 and to the source of the fourth transistor M4.
A gate of the sixth transistor M6 is connected to the drain of the fourth transistor M4, the gate of the eighth transistor M8, and the drain of the seventh transistor M7. The drain of the sixth transistor M6 is connected to the drain of the fifth transistor M5, the gate of the seventh transistor M7, and the gate of the ninth transistor M9. The source of the sixth transistor M6 is connected to ground.
A gate of the seventh transistor M7 is connected to the drain of the fifth transistor M5, the gate of the ninth transistor M9, and the drain of the sixth transistor M6. The drain of the seventh transistor M7 is connected to the drain of the fourth transistor M4, the gate of the sixth transistor M6, and the gate of the eighth transistor M8. The source of the seventh transistor M7 is connected to ground.
The gate of the eighth transistor M8 is connected to its own drain and to the gate of the sixth transistor M6 and to the gate of the seventh transistor M7. The source of the eighth transistor M8 is connected to ground.
The gate of the ninth transistor M9 is connected to its own drain and to the gate of the seventh transistor M7 and to the gate of the sixth transistor M6. The source of the ninth transistor M9 is grounded.
The tenth transistor M10 has a gate connected to the common mode feedback output terminal CMFB, a drain connected to the source of the eleventh transistor M11 and the source of the twelfth transistor M12, and a source connected to the ground of the tenth transistor M10.
A gate of the eleventh transistor M11 is coupled to the positive output terminal X of the pre-amplifying stage, a drain is coupled to the drain of the thirteenth transistor M13, and a source of the eleventh transistor M11 is coupled to the source of the twelfth transistor M12 and the drain of the tenth transistor M10.
A twelfth transistor M12 has a gate connected to the negative output terminal Y of the pre-amplifying stage, a drain connected to the drain of the fourteenth transistor M14, and a source of the twelfth transistor M12 connected to the source of the eleventh transistor M11 and the drain of the tenth transistor M10.
The thirteenth transistor M13 has a gate connected to the input terminal Vb4 of the fourth bias voltage, a drain connected to the drain of the fifteenth transistor M15, and a source connected to the drain of the seventeenth transistor M17.
The gate of the fourteenth transistor M14 is connected to the input terminal Vb4 of the fourth bias voltage, the drain is connected to the drain of the fourteenth transistor M14, and the source of the fourteenth transistor is connected to the drain of the sixteenth transistor M16.
The gate of the fifteenth transistor M15 is connected to the input terminal Vb3 of the third bias voltage, the drain is connected to the drain of the thirteenth transistor M13, and the source of the fifteenth transistor is connected to the drain of the seventeenth transistor M17.
The sixteenth transistor M16 has a gate connected to the input terminal Vb3 of the third bias voltage, a drain connected to the drain of the fourteenth transistor M14, and a source connected to the drain of the eighteenth transistor M18.
The gate of the seventeenth transistor M17 is connected to the input terminal Vb2 of the second bias voltage, the drain is connected to the source of the fifteenth transistor M15, and the source of the seventeenth transistor M17 is connected to the power supply.
The gate of the eighteenth transistor M18 is coupled to the input terminal Vb2 of the second bias voltage, the drain is coupled to the source of the sixteenth transistor M16, and the source of the eighteenth transistor M18 is coupled to the power supply.
Wherein the transistors M3-M9 constitute a pre-amplification stage of the fully differential operational amplifier, and the transistors M10-M18 constitute a second stage sleeve structure of the fully differential operational amplifier.
The pre-amplification stage circuit of the fully differential operational amplifier A1 of the invention has two feedback paths, the first is the series current feedback through the common source node of the fourth transistor M4 and the fifth transistor M5, and the feedback path is negative feedback; the second is a parallel voltage feedback connecting the gates and drains of the sixth transistor M6 and the seventh transistor M7, and this feedback path is a positive feedback.
When the positive feedback coefficient is larger than the negative feedback coefficient, the whole pre-amplification stage shows positive feedback. When the positive feedback coefficient is smaller than the negative feedback coefficient, the whole pre-amplifier stage shows negative feedback.
The output impedance at the positive output node X of the pre-amplifier stage is:
likewise, the output impedance at the negative output node Y is:
wherein, gm6, gm7, gm8 and gm9 are transconductance of transistors M6, M7, M8 and M9, respectively.
The load transistors M8 and M9 of the pre-amplifier stage in this embodiment are equal in size, the transistors M6 and M7 are equal in size, and the sizes of M8 and M9 are slightly larger than the sizes of M6 and M7. Therefore, M8 has a transconductance slightly larger than M6, and M9 has a transconductance slightly larger than M7. The output impedance of the pre-amplifier tends to a large value, and the feedback network of the pre-amplifier is represented by positive feedback, so that the maximum DC open loop gain is obtained.
The second stage of this embodiment is a telescopic cascode operational amplifier providing a gain of (gm ro)2Of the order of/2. The gain of the fully differential operational amplifier is further improved.
As described above, the fully differential operational amplifier a1 of the present invention forms a positive feedback loop by using the transistors M6-M9, thereby obtaining a very large DC open loop voltage gain, and providing a sufficiently large loop gain available for the feedback loop of the fully differential reference voltage generation circuit.
Referring to fig. 6 again, as a preferred embodiment, another reference voltage generating circuit is provided in the embodiment of the present invention. An open-loop branch 2 is added on the basis of the graph 1, and the open-loop branch 2 is duplicated according to the branch 1 in the aspect ratio relation of K: 1. The ratio of the current on the open-loop branch 2 to the current on the branch 1 is K: 1.
The nineteenth transistor M19 has a drain connected to the power supply VDD, and a gate connected to the gate of the first transistor M1. The source of the nineteenth transistor M19 is connected to the substrate and outputs a reference voltage high level HVREF。
The drain of the twentieth transistor M20 is grounded, and the gate is connected to the gate of the second transistor M2. The source of the twentieth transistor M20 is connected to the substrate and outputs the reference voltage LVREF.
One end of the seventh resistor R7 is connected to the source of the nineteenth transistor, and the other end is connected to one end of the eighth resistor R8. The other end of the eighth resistor R8 is connected to the source of the twentieth transistor M20.
As described above, the open-loop branch 2 at the output terminal of the reference voltage generation circuit as a preferred embodiment is implemented by a source follower. The source follower of the open-loop branch circuit 2 has good isolation effect, avoids the influence of voltage jitter and a closed-loop feedback loop, and enables the output reference voltage to be more stable. Meanwhile, the coupling effect from the power line to the output end can be reduced, and the PSRR of the circuit is improved.
HV is derived from the fully differential reference voltage generation circuit shown in FIG. 1REFAnd LVREFIs described in (1).
The resistance in the feedback loop satisfies the following relationship:
R1＝R2＝R3＝R4
R5＝R6
according to the virtual open circuit (imaginary cutoff) effect of the operational amplifier, the voltage equation of the column node at the node a corresponding to the positive input terminal of the fully differential operational amplifier a1 is listed as follows:
the equation for the column node voltage at node B corresponding to the negative input terminal of the fully differential operational amplifier A1 is listed as:
(VREF-Vin-)/R3＝(Vin--LVREF)/R4
according to the virtual short effect (Intrinsic virtual short) of the operational amplifier, it can be obtained:
Vin+＝Vin-
from the symmetry of the fully differential reference voltage generation circuit, the voltage at node C can be derived to satisfy:
Vcom＝(HVREF+LVREF)/2
where Vcom is the middle of the high and low reference voltages, and the output common mode voltage of the fully differential operational amplifier A1.
The high level HV of the output reference voltage can be obtained by the above formulaREFAnd a reference voltage low level LVREFExpression (c):
HVREF＝Vcom+VREF/2
LVREF＝Vcom-VREF/2
VREF＝HVREF-LVREF
from the expression, the output reference voltage HVREFAnd LVREFIs the operational amplifier output common mode voltage Vcom and the initial reference voltage VREFAs a function of (c). Wherein the common mode feedback Circuit (CMFB) maintains the middle value Vcom of the output reference voltage at VDD/2, and the initial reference voltage VREFGenerated by a bandgap reference and reference voltage generating circuit.
As described above, the fully differential reference voltage generation circuit of the present invention can output accurate reference voltage with high level HVREFAnd a reference voltage low level LVREF。
Next, the stability of the fully differential reference voltage generating circuit is analyzed, and fig. 8 is an ac equivalent circuit diagram of the fully differential reference voltage generating circuit, in which the influence of the level shifter is not considered.
According to fig. 8, the loop gain of the reference voltage generation circuit is listed:
wherein, gA1RoA1The gain of the fully differential operational amplifier a1 is shown, the term C3/(C3+ C1) is the attenuation value of the gain introduced by the operational amplifier a1 through the series capacitors C1 and C3, and the output gain of the whole circuit is attenuated to the original value of C3/(C1+ C3). 1/(1+ 1/(g)M2(R5//RdsM2) ) is the transfer function of the source follower, there will be some attenuation of the gain. R3/(R3+ R4) represents the voltage at which the output voltage is fed back to the input of the fully differential operational amplifier, i.e., the feedback coefficient.
From the expression, the loop gain of the fully differential reference voltage generation circuit is a very low value due to the attenuation of the series capacitance and the feedback factor.
In view of the above, the fully differential reference voltage generation circuit of the present invention has good stability and can be rapidly set up to a stable state, thereby ensuring rapid set-up of MDACs.
In addition, the reference voltage generating circuit adopts a fully differential structure, can effectively resist the influence of common-mode noise, and can output high-swing reference voltage.
EXAMPLE III
The present invention also provides a wireless communication device comprising an analog-to-digital converter, wherein the analog-to-digital converter comprises the fully-differential reference voltage generating circuit 10 according to any of the above embodiments.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1. A fully differential reference voltage generation circuit (10) adapted for a pipelined ADC, comprising: initial reference voltage input terminal (V)REF) The circuit comprises a power supply end (VDD), a ground end (GND), a fully differential operational amplifier (A1), a first level shifter (V1), a second level shifter (V2), a common mode feedback Circuit (CMFB), a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5), a sixth resistor (R6), a first switch tube (M1) and a second switch tube (M2); wherein the first switch tube (M1), the fifth resistor (R5), the sixth resistor (R6) and the resistorThe second switch tube (M2) is connected in series between the power supply end (VDD) and the ground end (GND) in sequence;
the first resistor (R1) and the second resistor (R2) are sequentially connected in series between the ground terminal (GND) and a node formed by connecting the first switch tube (M1) and the fifth resistor (R5) in series; the third resistor (R3) and the fourth resistor (R4) are sequentially connected in series to the initial reference voltage input terminal (V)REF) A node formed by connecting the sixth resistor (R6) and the second switch tube (M2) in series;
a positive input end (Vin +) of the fully differential operational amplifier (a1) is electrically connected to a node (a) formed by connecting the first resistor (R1) and the second resistor (R2) in series, a negative input end (Vin-) thereof is electrically connected to a node (B) formed by connecting the third resistor (R3) and the fourth resistor (R4) in series, a negative output end (Vout-) thereof and the first level shifter (V1) are sequentially connected to a control end of the first switch tube (M1) in series, and a positive output end (Vout +) thereof and the second level shifter (V2) are sequentially connected to a control end of the second switch tube (M2) in series;
the input end of the common mode feedback Circuit (CMFB) is electrically connected to a node (C) formed by the fifth resistor (R5) and the sixth resistor (R6) in series, and the output end of the common mode feedback circuit is electrically connected to the fully differential operational amplifier (A1).
2. The circuit (10) of claim 1, wherein the first switch transistor (M1) is an NMOS transistor and the second switch transistor (M2) is a PMOS transistor.
3. The circuit (10) of claim 2, wherein a source terminal of the NMOS transistor is connected to a substrate terminal of the NMOS transistor; and the source end of the PMOS tube is connected with the substrate end of the PMOS tube.
4. The circuit (10) of claim 1, further comprising a third capacitor (C3) and a fourth capacitor (C4); one end of the third capacitor (C3) is electrically connected to the control end of the first switch tube (M1) and the other end is electrically connected to the Ground (GND); one end of the fourth capacitor (C4) is electrically connected to the control end of the second switch tube (M2) and the other end is electrically connected to the Ground (GND).
5. The circuit (10) of claim 1, wherein the fully differential operational amplifier (a1) comprises: a third switching tube (M3), a fourth switching tube (M4), a fifth switching tube (M5), a sixth switching tube (M6), a seventh switching tube (M7), an eighth switching tube (M8), a ninth switching tube (M9), a tenth switching tube (M10), an eleventh switching tube (M11), a twelfth switching tube (M12), a thirteenth switching tube (M13), a fourteenth switching tube (M14), a fifteenth switching tube (M15), a sixteenth switching tube (M16), a seventeenth switching tube (M17) and an eighteenth switching tube (M18); wherein,
the third switching tube (M3), the fourth switching tube (M4) and the eighth switching tube (M8) are sequentially connected in series between the power supply end (VDD) and the ground end (GND), the control end of the third switching tube (M3) is electrically connected to a first bias voltage (Vb1), the control end of the fourth switching tube (M4) is electrically connected to the negative input end (Vin-), and the control end of the eighth switching tube (M8) is electrically connected to a node formed by connecting the fourth switching tube (M4) and the eighth switching tube (M8) in series;
the fifth switching tube (M5) and the ninth switching tube (M9) are sequentially connected in series between a node formed by connecting the third switching tube (M3) and the fourth switching tube (M4) in series and the ground terminal (GND), a control end of the fifth switching tube (M5) is electrically connected to the positive input end (Vin +), and a control end of the ninth switching tube (M9) is electrically connected to a node formed by connecting the fifth switching tube (M5) and the ninth switching tube (M9) in series;
the transmission end of the sixth switching tube (M6) is electrically connected to a node (Y) formed by the fifth switching tube (M5) and the ninth switching tube (M9) connected in series and a ground end (GND) respectively, and the control end of the sixth switching tube is electrically connected to the control end of the eighth switching tube (M8); the transmission end of the seventh switching tube (M7) is respectively electrically connected to a node (X) formed by the fourth switching tube (M4) and the eighth switching tube (M8) connected in series and a ground end (GND), and the control end of the seventh switching tube is electrically connected to the control end of the ninth switching tube (M9);
the seventeenth switching tube (M17), the fifteenth switching tube (M15), the thirteenth switching tube (M13), the eleventh switching tube (M11) and the tenth switching tube (M10) are connected in series in sequence between the power supply terminal (VDD) and the ground terminal (GND), the control terminal of the seventeenth switching tube (M17) is electrically connected to a second bias voltage (Vb2), the control terminal of the fifteenth switching tube (M15) is electrically connected to a third bias voltage (3), the control terminal of the thirteenth switching tube (M13) is electrically connected to a fourth bias voltage (Vb4), the control terminal of the eleventh switching tube (M11) is electrically connected to the fourth switching tube (M4) and a node (X) formed by connecting the eighth switching tube (M8) in series, the control terminal of the tenth switching tube (M10) is electrically connected to the input terminal of the common mode feedback circuit (fb), and the negative switching tube (cmm 35) is electrically connected to the thirteenth and the fifteenth switching tube (15) and the negative switching tube (cm3635 —) (M13) nodes formed in series;
the eighteenth switching tube (M18), the sixteenth switching tube (M16), the fourteenth switching tube (M14) and the twelfth switching tube (M12) are sequentially connected in series between the power supply end (VDD) and a node formed by connecting the eleventh switching tube (M11) and the tenth switching tube (M10) in series, the control end of the eighteenth switching tube (M18) is electrically connected with the second bias voltage (Vb2), the control end of the sixteenth switching tube (M16) is electrically connected with the third bias voltage (Vb3), the control end of the fourteenth switching tube (M14) is electrically connected with the fourth bias voltage (Vb4), the twelfth switching tube (M12) is electrically connected to the node (Y) formed by the fifth switching tube (M5) and the ninth switching tube (M9) in series, the positive output terminal (Vout +) is electrically connected to a node formed by the sixteenth switching tube (M16) and the fourteenth switching tube (M14) connected in series.
6. The circuit (10) according to claim 5, wherein the third switching tube (M3), the fourth switching tube (M4), the fifth switching tube (M5), the fifteenth switching tube (M15), the sixteenth switching tube (M16), the seventeenth switching tube (M17), and the eighteenth switching tube (M18) are PMOS tubes, and the sixth switching tube (M6), the seventh switching tube (M7), the eighth switching tube (M8), the ninth switching tube (M9), the tenth switching tube (M10), the eleventh switching tube (M11), the twelfth switching tube (M12), the thirteenth switching tube (M13), and the fourteenth switching tube (M14) are NMOS tubes.
7. The circuit (10) of claim 1, wherein the first level shifter (V1) comprises: a first switch (K1), a second switch (K2), a third switch (K3), a fourth switch (K4), a first capacitor (C1), a fifth capacitor (C5) and a first direct current power supply (Vbp 1); wherein the first switch (K1) and the second switch (K2) are sequentially connected in series between the first DC power supply (Vbp1) and the negative output terminal (Vout-) of the fully differential operational amplifier (A1), and the third switch (K3) and the fourth switch (K4) are sequentially connected in series between the power supply terminal (VDD) and the control terminal of the first switch tube (M1); one end of the first capacitor (C1) is electrically connected to the negative output end (Vout-) of the fully differential operational amplifier (A1) and the other end is electrically connected to the control end of the first switch tube (M1), one end of the fifth capacitor (C5) is electrically connected to a node formed by the first switch (K1) and the second switch (K2) which are connected in series, and the other end is electrically connected to a node formed by the third switch (K3) and the fourth switch (K4) which are connected in series.
8. The circuit (10) of claim 1, wherein the second level shifter (V2) comprises: a fifth switch (K5), a sixth switch (K6), a seventh switch (K7), an eighth switch (K8), a second capacitor (C2), a sixth capacitor (C6), and a second dc power supply (Vbn 1); wherein the fifth switch (K5) and the sixth switch (K6) are sequentially connected in series between the second dc power supply (Vbn1) and the positive output terminal (Vout +) of the fully differential operational amplifier (a1), and the seventh switch (K7) and the eighth switch (K8) are sequentially connected in series between the ground terminal (GND) and the control terminal of the second switch tube (M2); one end of the second capacitor (C2) is electrically connected to the positive output end (Vout +) of the fully differential operational amplifier (a1) and the other end is electrically connected to the control end of the second switch tube (M2), one end of the sixth capacitor (C6) is electrically connected to a node formed by the fifth switch (K5) and the sixth switch (K6) connected in series, and the other end is electrically connected to a node formed by the seventh switch (K7) and the eighth switch (K8) connected in series.
9. The circuit (10) of claim 1, further comprising: a nineteenth switching tube (M19), a twentieth switching tube (M20), a seventh resistor (R7) and an eighth resistor (R8); the nineteenth switching tube (M19), the seventh resistor (R7), the eighth resistor (R8) and the twentieth switching tube (M20) are sequentially connected in series between the power supply terminal (VDD) and the ground terminal (GND), the control terminal of the nineteenth switching tube (M19) is electrically connected to the control terminal of the first switching tube (M1), the control terminal of the twentieth switching tube (M20) is electrically connected to the control terminal of the second switching tube (M2), and the node formed by the nineteenth switching tube (M19) and the seventh resistor (R7) in series is connected to output a reference voltage high level (HV)REF) A node output reference voltage low Level (LV) formed by connecting the eighth resistor (R8) and the twentieth switching tube (M20) in seriesREF)。
10. A wireless communication device comprising an analog-to-digital converter, characterized in that the analog-to-digital converter comprises a fully differential reference voltage generating circuit (10) according to any of claims 1 to 9.
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