CN104702268A - Voltage buffer circuit and circuit including voltage buffer circuit to be used for driving loads to be switched along with time sequence - Google Patents
Voltage buffer circuit and circuit including voltage buffer circuit to be used for driving loads to be switched along with time sequence Download PDFInfo
- Publication number
- CN104702268A CN104702268A CN201510059257.9A CN201510059257A CN104702268A CN 104702268 A CN104702268 A CN 104702268A CN 201510059257 A CN201510059257 A CN 201510059257A CN 104702268 A CN104702268 A CN 104702268A
- Authority
- CN
- China
- Prior art keywords
- pmos
- nmos tube
- voltage
- grid
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electronic Switches (AREA)
Abstract
The invention provides a voltage buffer circuit and a circuit including the voltage buffer circuit to be used for driving loads to be switched along with the time sequence. The voltage buffer circuit is used for driving loads and at least comprises a differential input stage, an output stage and a bias module. The voltage buffer circuit is capable of switching drive capacity provided for the loads rapidly, small in power consumption and fast in work speed; the high driving current can be provided when large loads are needed to be driven, the low driving current is provided when large loads are not needed to be driven, the bias module maintains a high current branch in the output stage at a cut-off critical point, and accordingly, the output stage static current is reduced greatly. Meanwhile, the large current branch in the output stage is not cut off completely, so that the large current branch can be connected rapidly when the high driving current is needed, and the circuit switching speed and the reference voltage stability are improved.
Description
Technical field
The present invention relates to buffer circuit technical field, the circuit that the driving load particularly relating to a kind of voltage buffer circuit and have it switches with sequential.
Background technology
In analog integrated circuit; the situation that the load that often can run into reference voltage driving can switch with sequential; such as at SARADC (Successive Approximation Register Analog-to-Digital Converter; successive approximation register pattern number converter) in; the common mode reference voltage of comparator input terminal needs under the cooperation of sequential, drive large sampling capacitance (i.e. load), therefore provides the performance of the circuit of common mode reference voltage to whole circuit to play a key effect.
In the sample phase of SAR adc circuit, the common mode reference voltage produced by reference input voltage needs in the timing requirements of setting, to reach stable by fast driving bulky capacitor array, therefore provides the circuit of common mode reference voltage to need to have good stability and larger driving force.At data processing stage, common mode reference voltage does not need to drive bulky capacitor array, therefore will take into account the power problems that large driving force causes when circuit design yet.Fig. 1 is that the simplest common mode reference voltage produces circuit, common mode reference voltage VCM is produced by the first divider resistance Rd1 and the second divider resistance Rd2 dividing potential drop by reference input voltage VREF, common mode reference voltage VCM, directly by electric resistance partial pressure structure, i.e. the first load switch KC1 and the second load switch KC2, controls to drive the first large sampling capacitance CS1 and the second sampling capacitance CS2.This circuit structure is simple, but realizes large driving force to improve circuit speed, and the value of the first divider resistance Rd1 and the second divider resistance Rd2 can not be too large.But so, the milliampere level quiescent current of this circuit is by power consumptions a large amount of for waste, and electric resistance partial pressure structure limits the speed of this circuit and the stability of common mode reference voltage to a certain extent.
Fig. 2 is by an operational amplifier BUFFER, is connected between common mode reference voltage and the load of driving as buffer.This circuit can the large driving force of simple realization, and the output load of simultaneous buffering device and input common mode reference voltage are isolated, and ensure that the stability of reference voltage.But in order to realize large driving force, the quiescent current of common operational amplifier output stage is also comparatively large, does not need to drive in the time of heavy load at circuit, large Static Electro fails to be convened for lack of a quorum waste power consumption.
Therefore, need a kind of voltage buffer circuit now, can realize providing large driving force under heavy load, under little load, reduce quiescent dissipation, and the speed of circuit and the stability of reference voltage can be improved on this basis.
Summary of the invention
The shortcoming of prior art in view of the above, the circuit that the driving load that the object of the present invention is to provide a kind of voltage buffer circuit and have it switches with sequential, during for solving generating circuit from reference voltage driving heavy load in prior art, cause the problem of quiescent current power wastage to obtain large driving force.
For achieving the above object and other relevant objects, the invention provides a kind of voltage buffer circuit, for driving load, wherein, described voltage buffer circuit at least comprises: differential input stage, output stage and biasing module;
The positive input of described differential input stage connects a reference voltage, and the negative input of described differential input stage connects the output of described output stage, for comparing the output voltage of described reference voltage and described output stage;
Described output stage comprises at least two-way small area analysis branch road and at least one road big current branch road that are connected in parallel, for the relatively rear output driving current of the output voltage at described reference voltage and described output stage, and when the load that described voltage buffer circuit drives needs to switch, provide suitable driving force; Wherein, when described voltage buffer circuit is switched to driving heavy load, described output stage exports large-drive-current; When described voltage buffer circuit is switched to the little load of driving, the big current branch road in described output stage disconnects, and described output stage exports little drive current;
Described biasing module connects described output stage, when disconnecting for the big current branch road in described output stage, described big current branch road is biased to the critical point of shutoff, to reduce the quiescent current of described voltage buffer circuit.
Preferably, described differential input stage at least comprises: the first NMOS tube, the second NMOS tube, the first PMOS, the second PMOS and the 5th NMOS tube;
Wherein, the source ground of described 5th NMOS tube, the grid of described 5th NMOS tube accesses a differential input stage offset voltage, and the drain electrode of described 5th NMOS tube is connected with the source electrode of described second NMOS tube with the source electrode of described first NMOS tube; The drain electrode of described first NMOS tube is connected with draining with the grid of described first PMOS; The drain electrode of described second NMOS tube is connected with draining with the grid of the second PMOS; The source electrode of described 3rd PMOS is connected with power supply with the source electrode of the second PMOS; The grid of described first NMOS tube is the negative input of described differential input stage, and the grid of described second NMOS tube is the positive input of described differential input stage.
Preferably, in described output stage, first via small area analysis branch road at least comprises: the 3rd PMOS and the 3rd NMOS tube; Second road small area analysis branch road at least comprises: the 4th PMOS and the 4th NMOS tube; Big current branch road at least comprises: the 5th PMOS, the 6th NMOS tube, the first switch, second switch, the 3rd switch and the 4th switch;
Wherein, the source electrode of described 3rd PMOS is connected with power supply, the grid of described 3rd PMOS is connected with the grid of described first PMOS, and the drain electrode of described 3rd PMOS is connected with the drain and gate of described 3rd NMOS tube, the source ground of described 3rd NMOS tube; The source electrode of described 4th PMOS is connected with power supply, and the grid of described 4th PMOS is connected with the grid of described second PMOS, and the drain electrode of described 4th PMOS is connected with the drain electrode of described 4th NMOS tube; The grid of described 4th NMOS tube is connected with the grid of described 3rd NMOS tube, the source ground of described 4th NMOS tube; The anode of described first switch is connected with the grid of described 4th PMOS, and the negative terminal of described first switch is connected with the anode of described 3rd switch with the grid of described 5th PMOS; The anode of described second switch is connected with the grid of described 4th NMOS tube, and the negative terminal of described second switch is connected with the anode of described 4th switch with the grid of described 6th NMOS tube; The source electrode of described 5th PMOS is connected with power supply, and the drain electrode of described 5th PMOS is connected with the drain electrode of described 6th NMOS tube with the drain electrode of described 4th PMOS, the source ground of described 6th NMOS tube.
Preferably, described biasing module at least comprises: for generation of the first biasing circuit of the first bias voltage; Described first biasing circuit at least comprises: the 6th PMOS, the 7th PMOS, the first resistance and the 7th NMOS tube, and wherein, described first bias voltage is less than or equal to the difference of the threshold voltage of supply voltage and described 6th PMOS;
Wherein, the source electrode of described 6th PMOS is connected with power supply, the grid of described 6th PMOS is connected with the positive pole of described first resistance with the drain electrode of described 7th PMOS, and the drain electrode of described 6th PMOS is connected with the negative terminal of the 3rd switch with the source electrode of described 7th PMOS; The grid of described 7th PMOS is connected with the drain electrode of the negative pole of described first resistance with described 7th NMOS tube; The grid access one first bias circuit Bias voltage of described 7th NMOS tube, the source ground of described 7th NMOS tube; Described first bias voltage is the voltage of drain electrode place of described 6th PMOS.
Preferably, described biasing module also comprises: for generation of the second biasing circuit of the second bias voltage; Described second biasing circuit at least comprises: the 8th PMOS, the 9th PMOS, the second resistance, the 8th NMOS tube and the 9th NMOS tube, and wherein, described second bias voltage is more than or equal to the threshold voltage sum of earth terminal and described 9th NMOS tube;
Wherein, the source electrode of described 8th PMOS is connected with power supply, and the grid of described 8th PMOS is connected with the grid of described 6th PMOS, and the drain electrode of described 8th PMOS is connected with the source electrode of described 9th PMOS; The grid of described 9th PMOS is connected with the grid of described 7th PMOS, and the drain electrode of described 9th PMOS is connected with the grid of the positive pole of described second resistance with described 8th NMOS tube; The drain electrode of described 8th NMOS tube is connected with the grid of the negative terminal of described second resistance with described 9th NMOS tube, the source electrode of described 8th NMOS tube is connected with the drain electrode of described 9th NMOS tube with the negative terminal of described 4th switch, the source ground of described 9th NMOS tube; Described second bias voltage is the voltage of drain electrode place of described 9th NMOS tube.
The present invention also provides a kind of circuit driving load to switch with sequential, and wherein, the circuit that described driving load switches with sequential at least comprises: voltage buffer circuit as above.
Preferably, described driving load is that common mode reference voltage produces circuit with the circuit that sequential switches, and it also comprises: for generation of the voltage structure of common mode reference voltage; Wherein, described voltage structure is using its common mode reference voltage produced as the reference voltage being connected to described voltage buffer circuit.
Preferably, described voltage structure at least comprises: the first divider resistance and the second divider resistance; Wherein, the positive pole of described first divider resistance accesses a reference input voltage, and the negative pole of described first divider resistance is connected with the positive pole of described second divider resistance, the minus earth of described second divider resistance; Described common mode reference voltage is the voltage at the negative pole place of described first divider resistance.
As mentioned above, the circuit that voltage buffer circuit of the present invention and the driving load with it switch with sequential, has following beneficial effect:
Voltage buffer circuit of the present invention, can switch the driving force being supplied to load fast, power consumption is lower, and operating rate is fast; Can drive during heavy load at needs and provide large-drive-current, provide little drive current when not needing driving heavy load, now the big current branch road in output stage is remained on the critical point of shutoff by biasing module, greatly reduces the quiescent current of output stage.Meanwhile, because the big current branch road in output stage does not turn off completely, when needs large-drive-current, can open fast, improve the switch speed of circuit and the stability of reference voltage.
The circuit that driving load of the present invention switches with sequential, especially the common mode reference voltage of SAR ADC produces circuit, also can be the circuit that the load of other drivings switches with sequential, include the voltage buffer circuit that the present invention is above-mentioned, can realize providing large driving force under heavy load, under little load, reduce quiescent dissipation, and the speed of circuit and the stability of reference voltage can be improved on this basis.
Accompanying drawing explanation
Fig. 1 is shown as the schematic diagram that the present invention's common mode reference voltage of the prior art produces circuit.
Fig. 2 is shown as the schematic diagram that the present invention's common mode reference voltage with operational amplifier of the prior art produces circuit.
Fig. 3 is shown as the structural schematic block diagram of the voltage buffer circuit of first embodiment of the invention.
Fig. 4 is shown as the exemplary circuit diagram of the voltage buffer circuit of first embodiment of the invention.
Fig. 5 is shown as the schematic diagram of the circuit that driving load that the present invention second failed in love switches with sequential.
Element numbers explanation
VREF reference input voltage
VCM common mode reference voltage
Rd1 first divider resistance
Rd2 second divider resistance
KC1 first load switch
KC2 second load switch
CS1 first sampling capacitance
CS2 second sampling capacitance
BUFFER operational amplifier
10 differential input stages
20 output stages
21 first via small area analysis branch roads
22 second road small area analysis branch roads
30 biasing module
31 first biasing circuits
32 second biasing circuits
The negative input of VIN differential input stage
The positive input of VIP differential input stage
The output (output voltage) of Vout output stage
GND earth terminal
MN1 ~ MN9 first NMOS tube ~ the 9th NMOS tube
MP1 ~ MP9 first PMOS ~ the 9th PMOS
K1 ~ K4 first switch ~ the 4th switch
VB1 differential input stage offset voltage
VB2 first bias circuit Bias voltage
Vbias1 first bias voltage
Vbias2 second bias voltage
R1 first resistance
R2 second resistance
I1 first current source
I2 second current source
Mc mos capacitance
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 3 and Fig. 4, first embodiment of the invention relates to a kind of voltage buffer circuit, for driving load.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
As shown in Figure 3, the voltage buffer circuit of the present embodiment at least comprises: differential input stage 10, output stage 20 and biasing module 30.
For differential input stage 10, it has positive input and negative input.The positive input of differential input stage 10 connects a reference voltage, and the negative input of differential input stage 10 connects the output of output stage 20.Differential input stage 10 is for comparing the output voltage of reference voltage and output stage 20.
For output stage 20, it comprises at least two-way small area analysis branch road and at least one road big current branch road that are connected in parallel.Shown output stage 20 for the relatively rear output driving current of the output voltage at reference voltage and output stage 20, and when the load that voltage buffer circuit drives needs to switch, provides suitable driving force.Wherein, voltage buffer circuit be switched to drive heavy load time, output stage 20 exports large-drive-current, and namely output stage 20 provides large driving force for heavy load; Voltage buffer circuit be switched to drive little load time, the big current branch road in output stage 20 disconnects, and output stage 20 exports little drive current, and namely output stage 20 provides little driving force for little load.
For biasing module 30, it connects output stage 20, when disconnecting for the big current branch road in output stage 20, big current branch road is biased to the critical point of shutoff, to reduce the quiescent current of voltage buffer circuit.
It should be noted that, differential input stage 10, the power end in output stage 20 and biasing module 30 all accesses same supply voltage.
Be illustrated in figure 4 the exemplary circuit diagram of the present embodiment, differential input stage 10, concrete components and parts included in output stage 20 and biasing module 30 are as follows.It is pointed out that Fig. 4 is a kind of exemplary circuit in practical application, other are all can realize above-mentioned differential input stage 10, and the circuit of the effect of output stage 20 and biasing module 30 and the components and parts comprised thereof, all within protection scope of the present invention.
Refer to Fig. 4, differential input stage 10 at least comprises: the first NMOS tube MN1, the second NMOS tube MN2, the first PMOS MP1, the second PMOS MP2 and the 5th NMOS tube MN5.Wherein, the source ground of the 5th NMOS tube MN5, the grid of the 5th NMOS tube MN5 accesses a differential input stage 10 bias voltage VB1, and the drain electrode of the 5th NMOS tube MN5 is connected with the source electrode of the second NMOS tube MN2 with the source electrode of the first NMOS tube MN1; The drain electrode of the first NMOS tube MN1 is connected with draining with the grid of the first PMOS MP1; The drain electrode of the second NMOS tube MN2 is connected with draining with the grid of the second PMOS MP2; The source electrode of the 3rd PMOS MP3 is connected with power supply with the source electrode of the second PMOS MP2; The grid of the first NMOS tube MN1 is the negative input VIN of differential input stage 10, and the grid of the second NMOS tube MN2 is the positive input VIP of differential input stage 10.
Please continue to refer to Fig. 4, in output stage 20, preferably, comprise the two-way small area analysis branch road and a road big current branch road that are connected in parallel, two-way small area analysis branch road is respectively first via small area analysis branch road 21 and the second road small area analysis branch road 22.
First via small area analysis branch road 21 at least comprises: the 3rd PMOS MP3 and the 3rd NMOS tube MN3.Second road small area analysis branch road 22 at least comprises: the 4th PMOS MP4 and the 4th NMOS tube MN4.Big current branch road at least comprises: the 5th PMOS MP5, the 6th NMOS tube MN6, the first K switch 1, second switch K2, the 3rd K switch 3 and the 4th K switch 4.
Wherein, the source electrode of the 3rd PMOS MP3 is connected with power supply, and the grid of the 3rd PMOS MP3 is connected with the grid of the first PMOS MP1, and the drain electrode of the 3rd PMOS MP3 is connected with the drain and gate of the 3rd NMOS tube MN3, the source ground of the 3rd NMOS tube MN3; The source electrode of the 4th PMOS MP4 is connected with power supply, and the grid of the 4th PMOS MP4 is connected with the grid of the second PMOS MP2, and the drain electrode of the 4th PMOS MP4 is connected with the drain electrode of the 4th NMOS tube MN4; The grid of the 4th NMOS tube MN4 is connected with the grid of the 3rd NMOS tube MN3, the source ground of the 4th NMOS tube MN4; The anode of the first K switch 1 is connected with the grid of the 4th PMOS MP4, and the negative terminal of the first K switch 1 is connected with the anode of the 3rd K switch 3 with the grid of the 5th PMOS MP5; The anode of second switch K2 is connected with the grid of the 4th NMOS tube MN4, and the negative terminal of second switch K2 is connected with the anode of the 4th K switch 4 with the grid of the 6th NMOS tube MN6; The source electrode of the 5th PMOS MP5 is connected with power supply, and the drain electrode of the 5th PMOS MP5 is connected with the drain electrode of the 6th NMOS tube MN6 with the drain electrode of the 4th PMOS MP4, the source ground of the 6th NMOS tube MN6.
Please continue to refer to Fig. 4, biasing module 30 at least comprises: for generation of first biasing circuit 31 of the first bias voltage Vbias1.First biasing circuit 31 at least comprises: the 6th PMOS MP6, the 7th PMOS MP7, the first resistance R1 and the 7th NMOS tube MN7, wherein, first bias voltage Vbias1 is less than or equal to the difference of the threshold voltage vt hp of supply voltage VDD and the 6th PMOS MP6, is also the value Vthp lower than the value of supply voltage VDD of the first bias voltage Vbias1.Wherein, the source electrode of the 6th PMOS MP6 is connected with power supply, the grid of the 6th PMOS MP6 is connected with the positive pole of the first resistance R1 with the drain electrode of the 7th PMOS MP7, and the drain electrode of the 6th PMOS MP6 is connected with the negative terminal of the 3rd K switch 3 with the source electrode of the 7th PMOS MP7; The grid of the 7th PMOS MP7 is connected with the drain electrode of the 7th NMOS tube MN7 with the negative pole of the first resistance R1; The grid access one first biasing circuit 31 bias voltage VB2 of the 7th NMOS tube MN7, the source ground of the 7th NMOS tube MN7; First bias voltage Vbias1 is the voltage of drain electrode place of the 6th PMOS MP6.
Please continue to refer to Fig. 4, biasing module 30 also comprises: for generation of second biasing circuit 32 of the second bias voltage Vbias2.Second biasing circuit 32 at least comprises: the 8th PMOS MP8, the 9th PMOS MP9, the second resistance R2, the 8th NMOS tube MN8 and the 9th NMOS tube MN9, wherein, second bias voltage Vbias2 is more than or equal to the threshold voltage vt hn sum of earth terminal GND and the 9th NMOS tube MN9, is also the magnitude of voltage height Vthn of value than earth terminal GND of the second bias voltage Vbias2.Wherein, the source electrode of the 8th PMOS MP8 is connected with power supply, and the grid of the 8th PMOS MP8 is connected with the grid of the 6th PMOS MP6, and the drain electrode of the 8th PMOS MP8 is connected with the source electrode of the 9th PMOS MP9; The grid of the 9th PMOS MP9 is connected with the grid of the 7th PMOS MP7, and the drain electrode of the 9th PMOS MP9 is connected with the grid of the 8th NMOS tube MN8 with the positive pole of the second resistance R2; The drain electrode of the 8th NMOS tube MN8 is connected with the grid of the 9th NMOS tube MN9 with the negative terminal of the second resistance R2, and the source electrode of the 8th NMOS tube MN8 is connected with the drain electrode of the 9th NMOS tube MN9 with the negative terminal of the 4th K switch 4, the source ground of the 9th NMOS tube MN9; Second bias voltage Vbias2 is the voltage of drain electrode place of the 9th NMOS tube MN9.
The common mode reference voltage that the voltage buffer circuit of the present embodiment can be applicable to SAR ADC produces in circuit, also can be applied in other circuit driving loads to switch with sequential.When needing to drive large load (load namely driven needs to switch to heavy load), all small area analysis branch roads in output stage 20 and big current branch road are all connected in parallel and conducting, output stage 20 is switched to big current pattern, current branch increases, large-drive-current can be exported to heavy load, thus large driving force is provided.When not needing to drive large load (load namely driven needs to switch to little load), big current branch road in output stage 20 and the second road small area analysis branch road 22 are disconnected, small area analysis branch circuit parallel connection is only had to connect and conducting in output stage 20, output stage 20 is switched to small area analysis pattern, current branch reduces, little drive current can be exported to little load, thus little driving force is provided.When the big current branch road in output stage 20 and the second road small area analysis branch road 22 being disconnected, this big current branch road is connected to biasing module 30, this biasing module 30 can provide independent bias to this big current branch road.This independent bias makes the gate-source voltage bias of the 6th NMOS tube MN6 in this big current branch road at the threshold voltage place being slightly less than the 6th NMOS tube MN6, makes the gate-source voltage bias of the 5th PMOS MP5 in this big current branch road at the threshold voltage place a little less than the 5th PMOS MP5 simultaneously.When not needing large drive current, biasing module 30 makes the big current branch road in output stage 20 be biased in the critical point of shutoff, substantially reduces the quiescent current of output stage 20.Meanwhile, because the big current branch road in output stage 20 does not turn off completely, when needing large drive current, can open fast, under the prerequisite not increasing quiescent dissipation, substantially increasing the switch speed of circuit, further increasing the operating rate of circuit.
Second embodiment of the invention relates to a kind of circuit driving load to switch with sequential, and the circuit that the driving load of the present embodiment switches with sequential produces circuit as embody rule using the common mode reference voltage of SAR ADC, refers to Fig. 5.
The circuit that the driving load of the present embodiment switches with sequential at least comprises: the voltage buffer circuit involved by first embodiment of the invention.
In addition, drive load to be that common mode reference voltage produces circuit with the circuit that sequential switches, it also comprises: for generation of the voltage structure of common mode reference voltage VCM; Wherein, voltage structure is using its common mode reference voltage produced as the reference voltage being connected to voltage buffer circuit.
Wherein, voltage structure at least comprises: the first divider resistance Rd1 and the second divider resistance Rd2; Wherein, the positive pole of the first divider resistance Rd1 accesses a reference input voltage VREF, and the negative pole of the first divider resistance Rd1 is connected with the positive pole of the second divider resistance Rd2, the minus earth of the second divider resistance Rd2; First divider resistance Rd1 and the second divider resistance Rd2 produces with reference to input voltage VREF dividing potential drop the voltage that common mode reference voltage VCM, common mode reference voltage VCM are the negative pole place of the first divider resistance Rd1.
Please continue to refer to Fig. 5, voltage buffer circuit can be used as an operational amplifier, its output is the output end vo ut of output stage 20, and its positive input is the positive input VIP of differential input stage 10, and its negative input is the negative input VIN of differential input stage 10.The output of voltage buffer circuit is connected with its negative input, the negative feedback structure of component unit gain, according to the gain of operational amplifier, the current potential clamping down on its output is equal with the reference voltage of its positive input input, thus realizes the function of buffer circuit.Load is made up of mos capacitance Mc, the first load switch KC1, the second load switch KC2, the first sampling capacitance CS1 and the second sampling capacitance CS2.Wherein the positive pole of mos capacitance Mc is connected with the output end vo ut of output stage in voltage buffer circuit 20, the minus earth of mos capacitance Mc; The anode of the first load switch KC1 is all connected with the output end vo ut of output stage in voltage buffer circuit 20 with the anode of the second load switch KC2, and the negative terminal of the first load switch KC1 is connected with the positive pole of the first sampling capacitance CS1; The negative terminal of the second load switch KC2 is connected with the positive pole of the second sampling capacitance CS2; The negative pole of the first sampling capacitance CS1 is connected with the input VIN1 of follow-up adc circuit, for follow-up adc circuit provides input voltage, the negative pole of the second sampling capacitance CS2 is connected with the reference voltage VREF1 of follow-up adc circuit, as the reference voltage input terminal of follow-up adc circuit.Mos capacitance Mc is used for the frequency compensation of voltage buffer circuit.
The operation principle that the present embodiment common mode reference voltage produces circuit is:
When voltage buffer circuit needs to drive the heavy load be made up of the first sampling capacitance CS1 and the second sampling capacitance CS2, first load switch KC1 and the second load switch KC2 conducting simultaneously, the first sampling capacitance CS1 and the second sampling capacitance CS2 is connected to the output of voltage buffer circuit.First K switch 1 and second switch K2 be conducting simultaneously also, and the 3rd K switch 3 and the 4th K switch 4 are ended simultaneously.Now big current branch road becomes the part in feedback loop, and place in normal operation, there is large drive current, two-way small area analysis branch road in output stage 20 and a road big current branch road can give the first sampling capacitance CS1 and the rapid discharge and recharge of the second sampling capacitance CS2, make the voltage between the first sampling capacitance CS1 and the second sampling capacitance CS2 two-plate reach common mode reference voltage VCM rapidly, substantially increase the operating rate of circuit.
When buffer circuit does not need driving first sampling capacitance CS1 and the second sampling capacitance CS2, the first load switch KC1 and the second load switch KC2 ends simultaneously, and the first sampling capacitance CS1 and the second sampling capacitance CS2 disconnects from the output of voltage buffer circuit.Simultaneously, first K switch 1 and second switch K2 end simultaneously, 3rd K switch 3 and the conducting simultaneously of the 4th K switch 4, big current in output stage 20 prop up route independently the first bias voltage Vbias1 and the second bias voltage Vbias2 be biased, be the first current source I1 in Fig. 5 and the second current source I2.The computing formula of the first bias voltage Vbias1 and the second bias voltage Vbias2 is as follows:
Vbias1＝VDD+V
GSMP6-I·R1-V
GSMP7；
Vbias2＝V
GSMN9+I·R2-V
GSMN8。
Wherein, I is the quiescent current flowing through two biasing circuits, V
gSMP6be the gate source voltage of the 6th PMOS MP6, V
gSMP7be the gate source voltage of the 7th PMOS MP7, V
gSMN8be the gate source voltage of the 8th NMOS tube MN8, V
gSMN9it is the gate source voltage of the 9th NMOS tube MN9.
Make to meet lower relation of plane by arranging rational metal-oxide-semiconductor breadth length ratio:
VDD+Vdsatp＞Vbias1≈VDD+Vthp；Vdsatn＜Vbias2≈Vthn；
I·R1＜Vthn；I·R2＜|Vthp|。
Wherein, Vdsatp is the quiescent voltage of the 6th PMOS MP6, and Vdsatn is the quiescent voltage of the 9th NMOS tube MN9, Vdsatp=V
gSMP6-Vthp, Vdsatn=V
gSMN9-Vthn.
Thus make the 6th PMOS MP6, the 7th PMOS MP7, the 8th NMOS tube MN8 and the 9th NMOS tube MN9 be operated in saturation region, make the 5th PMOS MP5 and the 6th NMOS tube MN6 be operated in sub-threshold region simultaneously, substantially reduce static working current, save power consumption; Can ensure that the 5th PMOS MP5 and the 6th NMOS tube MN6 does not turn off completely simultaneously, can open fast, further increase the operating rate of circuit, ensure that the stability of reference voltage.In addition, because the 5th PMOS MP5 of the big current branch road in output stage 20 and the 6th NMOS tube MN6 is operated in sub-threshold region, the quiescent current of this big current branch road is very little, driving force is very weak, output resistance is higher, does not affect the output of the current voltage buffer circuit be made up of the two-way small area analysis branch road in differential input stage 10 and output stage 20.
It is to be noted, although the present embodiment produces circuit as embody rule using the common mode reference voltage of SAR ADC, but this is a kind of circuit of the voltage buffer circuit practical application involved by first embodiment of the invention, other application of the voltage buffer circuit involved by first embodiment of the invention can not be limited, in other embodiments, other drive load also can adopt the voltage buffer circuit involved by first embodiment of the invention with the circuit that sequential switches.
In sum, the circuit that voltage buffer circuit of the present invention and the driving load with it switch with sequential, has following beneficial effect:
Voltage buffer circuit of the present invention, can switch the driving force being supplied to load fast, power consumption is lower, and operating rate is fast; Can drive during heavy load at needs and provide large-drive-current, provide little drive current when not needing driving heavy load, now the big current branch road in output stage is remained on the critical point of shutoff by biasing module, greatly reduces the quiescent current of output stage.Meanwhile, because the big current branch road in output stage does not turn off completely, when needs large-drive-current, can open fast, improve the switch speed of circuit and the stability of reference voltage.
The circuit that driving load of the present invention switches with sequential, especially the common mode reference voltage of SAR ADC produces circuit, also can be the circuit that the load of other drivings switches with sequential, include the voltage buffer circuit that the present invention is above-mentioned, can realize providing large driving force under heavy load, under little load, reduce quiescent dissipation, and the speed of circuit and the stability of reference voltage can be improved on this basis.
So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (8)
1. a voltage buffer circuit, for driving load, is characterized in that, described voltage buffer circuit at least comprises: differential input stage, output stage and biasing module;
The positive input of described differential input stage connects a reference voltage, and the negative input of described differential input stage connects the output of described output stage, for comparing the output voltage of described reference voltage and described output stage;
Described output stage comprises at least two-way small area analysis branch road and at least one road big current branch road that are connected in parallel, for the relatively rear output driving current of the output voltage at described reference voltage and described output stage, and when the load that described voltage buffer circuit drives needs to switch, provide suitable driving force; Wherein, when described voltage buffer circuit is switched to driving heavy load, described output stage exports large-drive-current; When described voltage buffer circuit is switched to the little load of driving, the big current branch road in described output stage disconnects, and described output stage exports little drive current;
Described biasing module connects described output stage, when disconnecting for the big current branch road in described output stage, described big current branch road is biased to the critical point of shutoff, to reduce the quiescent current of described voltage buffer circuit.
2. voltage buffer circuit according to claim 1, it is characterized in that, described differential input stage at least comprises: the first NMOS tube (MN1), the second NMOS tube (MN2), the first PMOS (MP1), the second PMOS (MP2) and the 5th NMOS tube (MN5);
Wherein, the source ground of described 5th NMOS tube (MN5), the grid of described 5th NMOS tube (MN5) accesses a differential input stage offset voltage (VB1), and the drain electrode of described 5th NMOS tube (MN5) is connected with the source electrode of described second NMOS tube (MN2) with the source electrode of described first NMOS tube (MN1); The drain electrode of described first NMOS tube (MN1) is connected with draining with the grid of described first PMOS (MP1); The drain electrode of described second NMOS tube (MN2) is connected with draining with the grid of the second PMOS (MP2); The source electrode of described 3rd PMOS (MP3) is connected with power supply with the source electrode of the second PMOS (MP2); The grid of described first NMOS tube (MN1) is the negative input (VIN) of described differential input stage, and the grid of described second NMOS tube (MN2) is the positive input (VIP) of described differential input stage.
3. voltage buffer circuit according to claim 2, is characterized in that, in described output stage, first via small area analysis branch road at least comprises: the 3rd PMOS (MP3) and the 3rd NMOS tube (MN3); Second road small area analysis branch road at least comprises: the 4th PMOS (MP4) and the 4th NMOS tube (MN4); Big current branch road at least comprises: the 5th PMOS (MP5), the 6th NMOS tube (MN6), the first switch (K1), second switch (K2), the 3rd switch (K3) and the 4th switch (K4);
Wherein, the source electrode of described 3rd PMOS (MP3) is connected with power supply, the grid of described 3rd PMOS (MP3) is connected with the grid of described first PMOS (MP1), the drain electrode of described 3rd PMOS (MP3) is connected with the drain and gate of described 3rd NMOS tube (MN3), the source ground of described 3rd NMOS tube (MN3); The source electrode of described 4th PMOS (MP4) is connected with power supply, the grid of described 4th PMOS (MP4) is connected with the grid of described second PMOS (MP2), and the drain electrode of described 4th PMOS (MP4) is connected with the drain electrode of described 4th NMOS tube (MN4); The grid of described 4th NMOS tube (MN4) is connected with the grid of described 3rd NMOS tube (MN3), the source ground of described 4th NMOS tube (MN4); The anode of described first switch (K1) is connected with the grid of described 4th PMOS (MP4), and the negative terminal of described first switch (K1) is connected with the anode of described 3rd switch (K3) with the grid of described 5th PMOS (MP5); The anode of described second switch (K2) is connected with the grid of described 4th NMOS tube (MN4), and the negative terminal of described second switch (K2) is connected with the anode of described 4th switch (K4) with the grid of described 6th NMOS tube (MN6); The source electrode of described 5th PMOS (MP5) is connected with power supply, the drain electrode of described 5th PMOS (MP5) is connected with the drain electrode of described 6th NMOS tube (MN6) with the drain electrode of described 4th PMOS (MP4), the source ground of described 6th NMOS tube (MN6).
4. voltage buffer circuit according to claim 3, is characterized in that, described biasing module at least comprises: for generation of the first biasing circuit of the first bias voltage (Vbias1); Described first biasing circuit at least comprises: the 6th PMOS (MP6), the 7th PMOS (MP7), the first resistance (R1) and the 7th NMOS tube (MN7), wherein, described first bias voltage (Vbias1) is less than or equal to the difference of the threshold voltage of supply voltage (VDD) and described 6th PMOS (MP6);
Wherein, the source electrode of described 6th PMOS (MP6) is connected with power supply, the grid of described 6th PMOS (MP6) is connected with the positive pole of described first resistance (R1) with the drain electrode of described 7th PMOS (MP7), and the drain electrode of described 6th PMOS (MP6) is connected with the negative terminal of the 3rd switch (K3) with the source electrode of described 7th PMOS (MP7); The grid of described 7th PMOS (MP7) is connected with the drain electrode of the negative pole of described first resistance (R1) with described 7th NMOS tube (MN7); The grid access one first bias circuit Bias voltage (VB2) of described 7th NMOS tube (MN7), the source ground of described 7th NMOS tube (MN7); Described first bias voltage (Vbias1) is the voltage of drain electrode place of described 6th PMOS (MP6).
5. voltage buffer circuit according to claim 4, is characterized in that, described biasing module also comprises: for generation of the second biasing circuit of the second bias voltage (Vbias2); Described second biasing circuit at least comprises: the 8th PMOS (MP8), the 9th PMOS (MP9), the second resistance (R2), the 8th NMOS tube (MN8) and the 9th NMOS tube (MN9), wherein, described second bias voltage (Vbias2) is more than or equal to the threshold voltage sum of earth terminal (GND) and described 9th NMOS tube (MN9);
Wherein, the source electrode of described 8th PMOS (MP8) is connected with power supply, the grid of described 8th PMOS (MP8) is connected with the grid of described 6th PMOS (MP6), and the drain electrode of described 8th PMOS (MP8) is connected with the source electrode of described 9th PMOS (MP9); The grid of described 9th PMOS (MP9) is connected with the grid of described 7th PMOS (MP7), and the drain electrode of described 9th PMOS (MP9) is connected with the grid of the positive pole of described second resistance (R2) with described 8th NMOS tube (MN8); The drain electrode of described 8th NMOS tube (MN8) is connected with the grid of the negative terminal of described second resistance (R2) with described 9th NMOS tube (MN9), the source electrode of described 8th NMOS tube (MN8) is connected with the drain electrode of described 9th NMOS tube (MN9) with the negative terminal of described 4th switch (K4), the source ground of described 9th NMOS tube (MN9); Described second bias voltage (Vbias2) is the voltage of drain electrode place of described 9th NMOS tube (MN9).
6. the circuit driving load to switch with sequential, is characterized in that, the circuit that described driving load switches with sequential at least comprises: the voltage buffer circuit as described in any one of claim 1-5.
7. the circuit that switches with sequential of driving load according to claim 6, is characterized in that, described driving load is that common mode reference voltage produces circuit with the circuit that sequential switches, and it also comprises: for generation of the voltage structure of common mode reference voltage; Wherein, described voltage structure is using its common mode reference voltage produced as the reference voltage being connected to described voltage buffer circuit.
8. the circuit that switches with sequential of driving load according to claim 7, it is characterized in that, described voltage structure at least comprises: the first divider resistance (Rd1) and the second divider resistance (Rd2); Wherein, the positive pole of described first divider resistance (Rd1) accesses a reference input voltage (VREF), the negative pole of described first divider resistance (Rd1) is connected with the positive pole of described second divider resistance (Rd2), the minus earth of described second divider resistance (Rd2); Described common mode reference voltage is the voltage at the negative pole place of described first divider resistance (Rd1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510059257.9A CN104702268B (en) | 2015-02-04 | 2015-02-04 | The circuit that voltage buffer circuit and driving load with it switch with sequential |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510059257.9A CN104702268B (en) | 2015-02-04 | 2015-02-04 | The circuit that voltage buffer circuit and driving load with it switch with sequential |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104702268A true CN104702268A (en) | 2015-06-10 |
| CN104702268B CN104702268B (en) | 2017-08-08 |
Family
ID=53349085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510059257.9A Active CN104702268B (en) | 2015-02-04 | 2015-02-04 | The circuit that voltage buffer circuit and driving load with it switch with sequential |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104702268B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106325351A (en) * | 2016-10-14 | 2017-01-11 | 广州昌钰行信息科技有限公司 | Two-channel voltage buffer circuit |
| CN110763922A (en) * | 2019-11-01 | 2020-02-07 | 龙迅半导体（合肥）股份有限公司 | Differential reference voltage generation circuit, peak signal detection circuit, and electronic device |
| CN115167595A (en) * | 2022-07-12 | 2022-10-11 | 荣湃半导体（上海）有限公司 | Voltage buffer with low power consumption and high power supply ripple rejection ratio |
Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6259316B1 (en) * | 1998-05-29 | 2001-07-10 | Texas Instruments Incorporated | Low voltage buffer amplifier for high speed sample and hold applications |
| US20040039953A1 (en) * | 2002-06-10 | 2004-02-26 | Stmicroelectronics S.R.I. | Digital system with an output buffer with a switching current settable to load-independent constant values |
| CN1757157A (en) * | 2003-01-30 | 2006-04-05 | 桑迪士克股份有限公司 | Voltage buffer for capacitive loads |
| US7173489B1 (en) * | 2003-08-25 | 2007-02-06 | Marvell Semiconductor, Inc. | Programmable gain voltage buffer |
| CN101102095A (en) * | 2006-07-07 | 2008-01-09 | 雅马哈株式会社 | Offset voltage correction circuit and class d amplifier |
| CN101159432A (en) * | 2007-11-13 | 2008-04-09 | 东南大学 | CMOS type difference interface circuit |
| US7382308B1 (en) * | 2007-02-16 | 2008-06-03 | Iwatt Inc. | Reference buffer using current mirrors and source followers to generate reference voltages |
| CN101615049A (en) * | 2008-06-24 | 2009-12-30 | 联发科技股份有限公司 | Reference buffer circuit |
| US7821305B1 (en) * | 2008-04-03 | 2010-10-26 | Atheros Communications, Inc. | Dual voltage buffer with current reuse |
| CN102279610A (en) * | 2011-04-13 | 2011-12-14 | 清华大学 | Sub-threshold reference voltage source with extremely low power consumption and wide temperature range |
| CN102355261A (en) * | 2011-08-05 | 2012-02-15 | 清华大学 | Voltage buffer applied to high-speed analogue-to-digital converter |
| CN202395750U (en) * | 2011-12-02 | 2012-08-22 | 上海贝岭股份有限公司 | Differential reference voltage buffer |
| CN103365328A (en) * | 2012-04-09 | 2013-10-23 | 联咏科技股份有限公司 | Voltage buffer |
| CN103780212A (en) * | 2012-10-25 | 2014-05-07 | 华为技术有限公司 | Operational amplifiers, level switching circuit and programmable gain amplifier |
| CN104090626A (en) * | 2014-07-03 | 2014-10-08 | 电子科技大学 | High-precision multiple-output voltage buffer |
-
2015
- 2015-02-04 CN CN201510059257.9A patent/CN104702268B/en active Active
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6259316B1 (en) * | 1998-05-29 | 2001-07-10 | Texas Instruments Incorporated | Low voltage buffer amplifier for high speed sample and hold applications |
| US20040039953A1 (en) * | 2002-06-10 | 2004-02-26 | Stmicroelectronics S.R.I. | Digital system with an output buffer with a switching current settable to load-independent constant values |
| CN1757157A (en) * | 2003-01-30 | 2006-04-05 | 桑迪士克股份有限公司 | Voltage buffer for capacitive loads |
| US7173489B1 (en) * | 2003-08-25 | 2007-02-06 | Marvell Semiconductor, Inc. | Programmable gain voltage buffer |
| CN101102095A (en) * | 2006-07-07 | 2008-01-09 | 雅马哈株式会社 | Offset voltage correction circuit and class d amplifier |
| US7382308B1 (en) * | 2007-02-16 | 2008-06-03 | Iwatt Inc. | Reference buffer using current mirrors and source followers to generate reference voltages |
| CN101159432A (en) * | 2007-11-13 | 2008-04-09 | 东南大学 | CMOS type difference interface circuit |
| US7821305B1 (en) * | 2008-04-03 | 2010-10-26 | Atheros Communications, Inc. | Dual voltage buffer with current reuse |
| CN101615049A (en) * | 2008-06-24 | 2009-12-30 | 联发科技股份有限公司 | Reference buffer circuit |
| CN102279610A (en) * | 2011-04-13 | 2011-12-14 | 清华大学 | Sub-threshold reference voltage source with extremely low power consumption and wide temperature range |
| CN102355261A (en) * | 2011-08-05 | 2012-02-15 | 清华大学 | Voltage buffer applied to high-speed analogue-to-digital converter |
| CN202395750U (en) * | 2011-12-02 | 2012-08-22 | 上海贝岭股份有限公司 | Differential reference voltage buffer |
| CN103365328A (en) * | 2012-04-09 | 2013-10-23 | 联咏科技股份有限公司 | Voltage buffer |
| CN103780212A (en) * | 2012-10-25 | 2014-05-07 | 华为技术有限公司 | Operational amplifiers, level switching circuit and programmable gain amplifier |
| CN104090626A (en) * | 2014-07-03 | 2014-10-08 | 电子科技大学 | High-precision multiple-output voltage buffer |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106325351A (en) * | 2016-10-14 | 2017-01-11 | 广州昌钰行信息科技有限公司 | Two-channel voltage buffer circuit |
| CN110763922A (en) * | 2019-11-01 | 2020-02-07 | 龙迅半导体（合肥）股份有限公司 | Differential reference voltage generation circuit, peak signal detection circuit, and electronic device |
| CN110763922B (en) * | 2019-11-01 | 2021-12-31 | 龙迅半导体（合肥）股份有限公司 | Differential reference voltage generation circuit, peak signal detection circuit, and electronic device |
| CN115167595A (en) * | 2022-07-12 | 2022-10-11 | 荣湃半导体（上海）有限公司 | Voltage buffer with low power consumption and high power supply ripple rejection ratio |
| CN115167595B (en) * | 2022-07-12 | 2023-12-12 | 荣湃半导体（上海）有限公司 | Low-power consumption high-power supply ripple rejection ratio voltage buffer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104702268B (en) | 2017-08-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105187039B (en) | A kind of CMOS boot-strapped switch circuit | |
| CN110244095B (en) | High-speed current sampling circuit with ultralow power consumption | |
| Lee et al. | Design of low-power analog drivers based on slew-rate enhancement circuits for CMOS low-dropout regulators | |
| CN103956981B (en) | A kind of operation amplifier circuit eliminating DC offset voltage | |
| CN100452647C (en) | Voltage follower of small output resistance, large output amplitude | |
| CN104407662A (en) | Light-load transient enhanced circuit and low-voltage-difference linear voltage stabilizer integrated with circuit | |
| CN104639167A (en) | Comparator applied to low-power-consumption Pipeline ADCs (analog-to-digital converter) | |
| CN104702268A (en) | Voltage buffer circuit and circuit including voltage buffer circuit to be used for driving loads to be switched along with time sequence | |
| CN104881070A (en) | Ultra-low power consumption LDO circuit applied to MEMS | |
| CN110703010A (en) | Test circuit | |
| CN104779793A (en) | Breakover time generation circuit for BULK converter | |
| CN106487374B (en) | High-speed analog voltage signal buffer, chip and communication terminal | |
| CN104881071A (en) | Low-power reference voltage source | |
| CN106325346B (en) | Ldo circuit | |
| CN103529892A (en) | Class-AB output level biasing circuit | |
| CN212989976U (en) | LDO circuit, LDO and SOC system | |
| CN104300949A (en) | Low-voltage resetting circuit for radio frequency chip of internet of things | |
| CN103684420A (en) | Buffer for raising voltage driving capability | |
| CN205283503U (en) | Invariable mutual conductance rail -to -rail voltage comparater | |
| CN105162468A (en) | High-speed reference buffer circuit with voltage bootstrap | |
| CN106292832B (en) | A kind of compact CMOS mu balanced circuits of modified | |
| US20160056775A1 (en) | Signal output circuit | |
| CN204517773U (en) | A kind of single ended input hysteresis comparator circuit | |
| CN209265310U (en) | A kind of voltage buffer circuit | |
| CN113359928A (en) | Voltage generating circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: Zhangjiang Building 20A, 289 Chunxiao Road, China (Shanghai) Free Trade Pilot Area, Pudong New Area, Shanghai Co-patentee after: VeriSilicon Microelectronics (Beijing) Co., Ltd. Patentee after: Xinyuan Microelectronics (Shanghai) Co., Ltd. Co-patentee after: VERISILICON MICROELECTRONICS (CHENGDU) CO., LTD. Co-patentee after: Core holdings limited company Address before: 201203 Zhangjiang Building 20A, 560 Songtao Road, Zhangjiang High-tech Park, Pudong New Area, Shanghai Co-patentee before: VeriSilicon Microelectronics (Beijing) Co., Ltd. Patentee before: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Co-patentee before: VERISILICON MICROELECTRONICS (CHENGDU) CO., LTD. Co-patentee before: VeriSilicon Holdings Co., Ltd. |
|
| CP03 | Change of name, title or address |