CN1941205A - 擦除非易失性存储器单元的方法 - Google Patents
擦除非易失性存储器单元的方法 Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
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Abstract
一种方法包括确定一起擦除的行的分组，以在大量程序和擦除周期之后最小化与烘焙相关联的裕度损失。或者，所述方法包括确定一起擦除的行的分组，以最小化得到的擦除阈值电压分布的宽度，将所述分组一起擦除，当分组被擦除校验通过时，中止组的擦除并对之前未通过擦除校验的分组执行所述擦除步骤。
Description
技术领域
本发明通常涉及非易失性存储器单元阵列，尤其涉及他们的擦除。
背景技术
非易失性存储器单元阵列通常被设计用于经受100000次编程(programming)和擦除周期以及在每个单元中将存储的数据保留一段有效期，例如十年。存储器单元承受编程和擦除周期的次数的能力以及长时间保留数据的能力主要依赖于擦除操作。
在图1中示意性地说明了擦除过程，现在参考其。在擦除之前，被编程的单元可以具有高于程序校验(program verify，PV)电平的阈值电压的分布，由10标记。在擦除过程中，每次在一个脉冲内就立刻将整个阵列擦除。在第一个脉冲之后，程序分布10已经向较低的方向移动，变为分布12。在每个脉冲之后，“校验”阵列以确定是否全部单元已经被擦除为低于擦除校验(erase verify，EV)电平。重复该过程直到所有单元都被校验通过。在图1中，阵列需要3个产生分布12、14和16的脉冲，直到所有单元具有低于EV电平的阈值电压。最终的分布16还被称作“擦除分布”16。
然而，一些单元被快速的擦除(在图1中的2个脉冲内)，而其他单元需要更长时间来擦除(全部3个脉冲)，从而导致较宽的分布，由箭头18指示。经受额外的擦除脉冲的单元可能被过度擦除，这不是理想状态。
过度擦除可以有多种原因，其中包括在阵列中的单元的尺寸的不一致、阵列单元的程序分布的宽度、擦除算法、单元的电特性和物理特性等等。
过度擦除会影响产品可靠性和产品性能。其中的一个方面是“裕度损失”(margin loss)，在图2中显示，现在参考其。
阵列可以开始于高于程序校验(PV)电平的程序分布10和低于擦除校验(EV)电平的擦除分布16。读电平RD被定义在二个校验电平之间。如果单元具有高于读电平RD的阈值电压，则单元被定义为已编程的。否则，单元被定义为已擦除的。
裕度M也可以被定义，在这种情况下，只有其阈值电压在电平RD+M0以上时，单元才被认为是已编程的，只有在其阈值电压在电平RD-M1以下时，单元才被认为是已擦除的。
随着时间的流逝，二个分布都可以向较低的方向移动并展开，分别变成分布10’和16’。但是，分布10和16会移动到一定程度以致净裕度(net margin)NM不再保证正确的读操作，NM定义为最高擦除电平E1和最低程序电平P1之间的差。这在申请人于2004年12月9日提交的另一个待审未决申请USSN 11/007,332中有更详细的讨论，通过参考将其包含在此。
现在参考图3，图3说明了典型阵列在升高的温度(150℃)下经过100000次周期之后，净裕度NM随时间的变化。如在本技术领域中所知的，图3的例子是产品寿命的模型。净裕度NM可以从1200mV减少到300mV，改变了900mV。在100分钟处，较小的净裕度NM对于读操作可能是不够的。
附图说明
在本说明书的结论部分特别地指出并且清楚地声明了看作本发明的主题。然而，通过结合附图阅读以下的详细描述，可以更好地在组织和操作的方法，及其目的、特征和优点等方面了解本发明，其中：
图1示意性地说明在现有技术的擦除过程期间，阵列单元的阈值电压的分布；
图2示意性地说明在阵列操作期间的阈值电压的分布；
图3以图形的方式说明在升高的温度下，现有技术的阵列经过100000次周期之后的随时间变化的裕度损失；
图4A以图形的方式说明阵列的操作的不同模式的裕度损失；
图4B以图形的方式说明图4A中的操作模式的擦除分布；
图5示意性地说明根据本发明而构造和操作的非易失性存储器芯片的多个部分；
图6示意性地说明在图5的芯片的存储器阵列中的擦除分布。
应当了解，为了说明的简洁和清楚，附图中所示的元件不必按比例绘制。例如，为了清楚，一些元件的尺寸可以被相对于其他元件而夸大。此外，在适当的情况下，在各图中可以重复使用参考标记以指示对应的或类似的元件。
具体实施方式
在以下详细描述中，为了提供对本发明的透彻理解，描述了大量具体细节。但是，本领域的技术人员应该理解，即使没有这些具体细节，仍然可以实施本发明。在其他例子中，为了不使本发明变得模糊，没有详细描述已知的方法、过程和组件。
申请人已经意识到，在同一时间擦除更多位会增加过度擦除和其附带的裕度损失。在图4A和图4B中对其进行说明，现在参考图4A和图4B。二个图都比较了三种操作模式的数据，在“扇区模式”中，0.5M位被一起擦除，在“页模式”中，2K位被一起擦除，在“字节模式”中，八(8)位被一起擦除。
图4A与图3相似，并且显示了在扇区模式(曲线20)、页模式(曲线22)和字节模式(曲线24)中，随时间而变化的净裕度。可以看出净裕度变化在扇区模式(曲线20)中更加剧烈，并且在字节模式(曲线24)中最不剧烈。
在图4B中，比较了三个擦除分布30(扇区模式)、32(页模式)和34(字节模式)。如图所示，分布30比分布32更宽并且分布34最窄。分布的宽度显示随着一次被擦除的位的数量而减少。
图4A和图4B可以指示当更多位在同一时间被擦除时，在循环之后随着时间过去会增加过度擦除和裕度损失。
申请人已经意识到可以通过将擦除操作分割成不同的组来使擦除分布变窄。分割会使得每个擦除分组有更少位，其可以在擦除分组中提供改进的同质性(homogeneity)。由于与更少的将被一次擦除的单元相关联的改进的同质性，对于每个片断或每个分组的擦除分布可以有更小的展开，并且得到的阵列的擦除分布将会更窄。在这种方法中，可以部分克服导致较宽的擦除分布的原因，例如单元的不一致性、擦除算法和程序分布。
申请人还意识到可以使用一组行或字线WLs来决定擦除操作的终止。根据本发明的优先实施例，可以在某个时间同时向全部字线分组提供擦除脉冲。当一个分组被擦除校验过后，擦除操作可以为该擦除分组停止。其他擦除分组可以继续擦除操作直到他们通过擦除校验。
现在参考图5，图5说明了根据本发明构造和操作的存储器芯片40，其中多组行被一起擦除。存储器芯片40可以包括存储器阵列42，其由字线WL(i)(“行”)和位线BL(j)(“列”)构成。单元44可以是任何合适的非易失性存储器，例如单位或双位NROM(氮化物只读存储器)单元，可以在字线WL与位线BL的交叉点找到单元44。
根据本发明的优选实施例，存储器芯片40还可以包括X解码器46，其具有用于存储字线WL的分组的擦除标志寄存器48。应当知到寄存器48的物理位置可以在任何合适的位置而不是必须在如图指示的位置。
在常规操作期间，X解码器46可以解码输入地址以确定激活哪些字线WL(i)以访问所期望的单元。Y-解码器(未显示)可以选择合适的位线BL(j)以访问所期望的单元。
在擦除期间，X解码器46可以存储在擦除标志寄存器48中的信息按照字线WL(i)的分组来激活字线WL(i)。可以按照任何合适的方法对字线WL(i)进行分组，例如，M个连续的字线WL(i)，其中M可以大于等于1。通常M可以是4-16。
在另一个实施例中，可以以按照阵列的不一致性而排列的模型对字线WL(i)进行分组。例如，一些字线WL(i)可以更接近于到位线触点(即电流到达位线BL的点)的金属，其他可以更远。在具有128-512个字线的擦除扇区的阵列中，每16或32个字线WLs设置到位线接触点的金属。在本实施例中，可以按照字线WL(i)与到位线触点的金属的距离来对字线WL(i)进行分组。
在本发明中，可以向整个阵列提供第一擦除脉冲，在这之后可以一组接一组地对阵列进行擦除校验。当一组通过擦除校验时，可以为该组停止擦除操作(这可以通过改变该组的字线的标志来实现)。那些未通过擦除校验的组可以接收下一个擦除脉冲，直到没有未通过擦除校验的组。
因此，可以按照每个所选择的组的擦除的速度来分割擦除操作。那些在N个脉冲之后可以被擦除校验通过的字线分组可以与那些在N+m个脉冲之后被擦除校验通过的分组区分开，其中m大于等于1。
由于在本发明中，被一起擦除的单元的数量可以较小和/或分组可以更同质，所以对于大多数组，中止擦除的决定可以更早出现，从而导致更少的过度擦除单元。这可以导致更窄的擦除分布，如图6所示，现在简要参考其。
图6显示了标准扇区擦除操作的擦除分布50和本发明的擦除分布52。如图所示，扇区擦除分布50具有1000mV的宽度，而擦除分布52仅具有700mV的宽度。
虽然在此说明和描述了本发明的某些特征，但是本领域的普通技术人员可以想到许多变形、替换、改变和等价物。因此，应该理解所附加的权利要求用于包括所有符合本发明的精神的变形和改变。
Claims (21)
1.一种非易失性存储器芯片，包括：
非易失性存储器单元的存储器阵列，该阵列形成为行和列；
激活所述存储器阵列的行的X解码器；以及
擦除标志寄存器，用于识别将一起擦除的所述行的分组。
2.如权利要求1所述的芯片，其中，每个所述分组是M个连续行的集合。
3.如权利要求1所述的芯片，其中，每个所述分组是根据所述阵列中的不一致性而排列的N个行的集合。
4.如权利要求1所述的芯片，其中，每个所述分组是根据程序操作期间的阵列单元的编程电平和速度的不一致性而排列的A个行的集合。
5.如权利要求1所述的芯片，其中，每个所述分组是根据擦除操作期间的阵列单元的擦除速度的不一致性而排列的B个行的集合。
6.如权利要求1所述的芯片，其中，每个所述分组是根据行与该行的捷联位置(strapping location)的距离的不一致性而排列的C个行的集合。
7.如权利要求1所述的芯片，其中，每个所述分组是在之前的擦除操作期间，在相同数量的脉冲内被擦除的D个行的集合。
8.一种方法，包括：
确定将一起擦除的行的分组，以最小化得到的擦除阈值电压分布的宽度；
一起擦除所述分组；
当分组被擦除校验过时，停止所述分组的擦除；以及
对之前未被擦除校验过的分组执行所述擦除步骤。
9.如权利要求8所述的芯片，其中，每个所述分组是M个连续行的集合。
10.如权利要求8所述的芯片，其中，每个所述分组是根据阵列不一致性而排列的N个行的集合。
11.如权利要求8所述的芯片，其中，每个所述分组是根据程序操作期间的阵列单元的编程电平和速度的不一致性而排列的A个行的集合。
12.如权利要求8所述的芯片，其中，每个所述分组是根据擦除操作期间的阵列单元的擦除速度的不一致性而排列的B个行的集合。
13.如权利要求8所述的芯片，其中，每个所述分组是根据行与该行的捷联位置的距离而定义的C个行的集合。
14.如权利要求8所述的芯片，其中，每个所述分组是在之前的擦除操作期间，在相同数量的脉冲内被擦除的D个行的集合。
15.一种方法，包括：
确定将一起擦除的行的分组，以便在大量编程和擦除周期之后，最小化与烘焙(bake)相关联的裕度损失。
16.如权利要求15所述的芯片，其中，每个所述分组是M个连续行的集合。
17.如权利要求15所述的芯片，其中，每个所述分组是根据阵列不一致性而排列的N个行的集合。
18.如权利要求15所述的芯片，其中，每个所述分组是根据程序操作期间的阵列单元的编程电平和速度的不一致性而排列的A个行的集合。
19.如权利要求15所述的芯片，其中，每个所述分组是根据擦除操作期间的阵列单元的擦除速度的不一致性而排列的B个行的集合。
20.如权利要求15所述的芯片，其中，每个所述分组是根据行与该行的捷联位置的距离而定义的C个行的集合。
21.如权利要求15所述的芯片，其中，每个所述分组是在之前的擦除操作期间，在相同数量的脉冲内被擦除的D个行的集合。
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| US11/205,716 US7668017B2 (en) | 2005-08-17 | 2005-08-17 | Method of erasing non-volatile memory cells |
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| US (1) | US7668017B2 (zh) |
| EP (1) | EP1755127A3 (zh) |
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| CN102890617A (zh) * | 2011-07-18 | 2013-01-23 | 群联电子股份有限公司 | 存储器控制方法、存储器控制器与存储器储存装置 |
| CN103606383A (zh) * | 2013-11-11 | 2014-02-26 | 广东博观科技有限公司 | 一种自适应的芯片擦除字线分组的装置和方法 |
| CN103778083A (zh) * | 2012-10-18 | 2014-05-07 | 华邦电子股份有限公司 | 数据储存装置以及非挥发性存储器控制方法 |
| CN104575604A (zh) * | 2013-10-25 | 2015-04-29 | 华邦电子股份有限公司 | 快闪存储器的抹除方法 |
| CN111951861A (zh) * | 2019-05-14 | 2020-11-17 | 北京兆易创新科技股份有限公司 | 一种控制擦除性能的方法和装置 |
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| KR20100097407A (ko) * | 2009-02-26 | 2010-09-03 | 삼성전자주식회사 | 저항성 메모리 장치, 이를 포함하는 메모리 시스템 및 저항성 메모리 장치의 프로그램 방법 |
| KR20100107609A (ko) * | 2009-03-26 | 2010-10-06 | 삼성전자주식회사 | 저항성 메모리 장치, 이를 포함하는 메모리 시스템 및 저항성 메모리 장치의 기입 방법 |
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| US6912160B2 (en) | 2003-03-11 | 2005-06-28 | Fujitsu Limited | Nonvolatile semiconductor memory device |
| US6940759B2 (en) * | 2003-10-14 | 2005-09-06 | Atmel Corporation | Group erasing system for flash array with multiple sectors |
| US6937523B2 (en) | 2003-10-27 | 2005-08-30 | Tower Semiconductor Ltd. | Neighbor effect cancellation in memory array architecture |
| KR100562636B1 (ko) | 2003-12-30 | 2006-03-20 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 파워업 회로 |
| JP4427361B2 (ja) * | 2004-03-16 | 2010-03-03 | 株式会社東芝 | 不揮発性半導体メモリ |
| US7281193B2 (en) * | 2004-09-27 | 2007-10-09 | Mediatek Inc. | Method and apparatus for decoding multiword information |
| US7242618B2 (en) | 2004-12-09 | 2007-07-10 | Saifun Semiconductors Ltd. | Method for reading non-volatile memory cells |
| US7257025B2 (en) | 2004-12-09 | 2007-08-14 | Saifun Semiconductors Ltd | Method for reading non-volatile memory cells |
-
2005
- 2005-08-17 US US11/205,716 patent/US7668017B2/en active Active
-
2006
- 2006-08-15 EP EP06118949A patent/EP1755127A3/en not_active Withdrawn
- 2006-08-17 CN CNA2006101150463A patent/CN1941205A/zh active Pending
- 2006-08-17 JP JP2006222249A patent/JP2007052908A/ja active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102890617A (zh) * | 2011-07-18 | 2013-01-23 | 群联电子股份有限公司 | 存储器控制方法、存储器控制器与存储器储存装置 |
| CN102890617B (zh) * | 2011-07-18 | 2015-06-10 | 群联电子股份有限公司 | 存储器控制方法、存储器控制器与存储器储存装置 |
| CN103778083A (zh) * | 2012-10-18 | 2014-05-07 | 华邦电子股份有限公司 | 数据储存装置以及非挥发性存储器控制方法 |
| CN103778083B (zh) * | 2012-10-18 | 2017-03-01 | 华邦电子股份有限公司 | 数据储存装置以及非挥发性存储器控制方法 |
| CN104575604A (zh) * | 2013-10-25 | 2015-04-29 | 华邦电子股份有限公司 | 快闪存储器的抹除方法 |
| CN104575604B (zh) * | 2013-10-25 | 2018-01-19 | 华邦电子股份有限公司 | 快闪存储器的抹除方法 |
| CN103606383A (zh) * | 2013-11-11 | 2014-02-26 | 广东博观科技有限公司 | 一种自适应的芯片擦除字线分组的装置和方法 |
| CN111951861A (zh) * | 2019-05-14 | 2020-11-17 | 北京兆易创新科技股份有限公司 | 一种控制擦除性能的方法和装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| US7668017B2 (en) | 2010-02-23 |
| JP2007052908A (ja) | 2007-03-01 |
| EP1755127A2 (en) | 2007-02-21 |
| US20070041249A1 (en) | 2007-02-22 |
| EP1755127A3 (en) | 2007-05-30 |
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