CN1645604A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN1645604A
CN1645604A CNA200510004755XA CN200510004755A CN1645604A CN 1645604 A CN1645604 A CN 1645604A CN A200510004755X A CNA200510004755X A CN A200510004755XA CN 200510004755 A CN200510004755 A CN 200510004755A CN 1645604 A CN1645604 A CN 1645604A
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China
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projection
mentioned
welding disk
semiconductor device
pad
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CN100481424C (zh
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戒能宪幸
家合政敏
桑原公仁
大谷克实
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

本发明可增大焊盘部和外部端子的连接力,可靠地防止脱落,确保长期连接可靠性。本发明的半导体装置,在半导体元件1上形成使金属配线7a间绝缘的绝缘树脂层4,金属配线的端部与上述半导体元件上的电极2连接,金属配线的其他端部作为焊盘与外部端子9连接,除了上述焊盘的连接部分,被表层树脂层8被覆,其中,焊盘中至少一个焊盘部7b的上面设置突起10。从而,焊接连接时外部端子从周围捕捉焊盘部的突起,可可靠地连接外部端子和焊盘部。结果,可获得确保长期连接可靠性的半导体装置。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法,所述半导体装置是保护半导体的集成电路部且确保外部装置和半导体元件的电气连接的半导体装置,它将BGA和晶片级的芯片尺寸封装等在树脂基板上与外部端子焊接连接,具有长期的高焊接连接可靠性。
背景技术
近年,为了响应电子设备的处理能力提高及便携性提高,半导体装置等的电子部件要求高密度安装,从而,半导体装置的小型、薄型化、且同一装置尺寸中的多针化取得进展,开发了在区域上排列针的BGA和各种的CSP(芯片尺寸封装)。
特别地,在半导体的晶片上形成从半导体元件电极到外部端子为止进行连接的再配线,最终工序中分割的形态的WLCSP(晶片级CSP)作为实现与裸芯片同等的极小型封装的技术在近年备受注目(参照特开平11-54649号公报)。
以下,参照图面说明传统的称为WLCSP的半导体装置及其制造方法。
图20是称为WLCSP的半导体装置的部分开口透视图。图20中,1是半导体元件,2是半导体元件电极,3是钝化膜,4是绝缘树脂层,7a是金属配线,7b是金属焊盘,8是焊料保护膜,9是外部端子。
图21到图23是表示上述半导体装置的传统的制造方法的各工序的截面图。图21到图23中,与图20相同构成要素采用相同符号,其说明省略。
首先作为绝缘树脂层4,一般用感光性树脂在半导体元件1上涂敷。然后采用对准器或分节器等曝光,显影除去半导体元件电极2上及其他不要的感光性树脂后,硬化形成绝缘树脂层4(图21A)。
这里,半导体元件电极2通常采用Al-Si或Al-Si-Cu,因而作为形成绝缘树脂层4的材料即感光性树脂的显影液,采用显影时不溶解半导体元件电极2的弱碱性或有机显影液。
构图并层叠了绝缘树脂层4的半导体元件1上通过溅射法全面形成蒸镀金属层5(图21B)。此时作为蒸镀金属层5,首先形成金属阻挡层,在真空状态下形成延伸的电镀板层。另外,溅射之前,通过等离子处理使绝缘树脂层4的表面微细地粗化,提高绝缘树脂层4和金属阻挡层的粘合强度。等离子处理方法和反应气体若能够对半导体元件电极2和钝化膜3选择性地蚀刻绝缘树脂层4的树脂就可以,这里采用RIE(Reactive Ion Etching)处理法和O2气和N2气或O2气和CF4气的混合气体等。
金属阻挡层具有与绝缘树脂层4或半导体元件电极2、钝化膜3的强粘合强度,且对电镀板层的蚀刻液具有阻挡性的金属,例如采用Cr等。作为电镀板层必须是电解电镀中电阻率低的金属,一般采用Cu。金属阻挡层的厚度从对电镀板层的蚀刻液的阻挡性的观点看,采用0.1到0.2μm左右,电镀板层的厚度从电气电阻和析出应力和蚀刻的容易度的观点看,采用0.2到0.5μm左右。接着在电镀板层上涂敷感光性保护膜材料。然后通过干燥、曝光、显影感光性保护膜材料,形成电镀保护膜6a(图21C)。一般,由于后工序的电解Cu电镀厚度从5到11μm左右,因而电镀保护膜6a的厚度形成从8到15μm。然后,通过O2气的等离子处理除去电镀保护膜6a的显影残留。
接着,通过电解Cu电镀法,在电镀保护膜6a开口、板层露出的部分选择地形成厚膜金属层7(图22A)。厚膜金属层7的厚度从电气电阻和机械强度的观点看,形成5到11μm左右的厚度。
厚膜金属层7形成后剥离除去电镀保护膜6a,而且通过O2等离子的等离子处理除去电镀保护膜6a的剥离残留(图22B)。
接着,若用Cu蚀刻液全面Cu蚀刻板层和厚膜金属层7,则比厚膜金属层7层厚薄的板层的Cu被先行除去。此时板层的蚀刻液采用不溶金属阻挡层但可选择地蚀刻板层的溶液。接着通过全面蚀刻金属阻挡层,形成具有期望图案的金属配线7a及金属焊盘7b(图22C)。
接着在绝缘树脂层4、厚膜金属层7上涂敷感光性树脂,然后干燥、曝光,显影除去金属焊盘7b上及其他不需要的感光性树脂后,硬化形成焊料保护膜层8(图23A)。
然后在金属焊盘上印刷焊接剂,熔融形成外部端子9(图23B)。这里作为印刷熔融焊接剂的替代,也可以搭载熔融低融点金属球来形成外部端子9。另外,在印刷焊接剂之前,也可以在金属焊盘上进行Ni-Au电镀。
但是,根据上述传统的半导体装置的制造方法,为了提高与焊料保护膜的粘合性,构成配线及焊盘的Cu层中虽然进行微细粗化的表面处理,但是金属焊盘和外部端子之间的整体形状是平坦的。因而,半导体装置安装后的检查工序及安装工序,安装后与外部装置连接的状态中,外部端子若受到机械外力和热膨张差导致的热应力,则如图24所示可能从焊盘7b和外部端子9的连接界面开始产生裂纹13,另外外部端子也可能脱落。
一次负载中即使不产生裂纹和脱落,由于高温环境下在界面形成合金层,也会降低长期间的连接可靠性。因而,如图25A、B所示,有通过增加焊盘部7b和外部端子9的连接界面14的面积来增加焊盘部7b和外部端子9的连接界面14中产生的金属结合的连接力的方法,虽然在增加连接面的面积的同时提高连接强度,但是,由于热履历,在连接界面1.4中金属扩散导致脆合金层形成时,连接强度显著降低,因而没有根本解决连接界面中的裂纹和外部端子脱落。
近年,铅对环境的影响成为世界问题,从传统的包含铅的Pb-Sn共晶焊接向不包含铅的焊接(以下称为无铅焊接)的转换在包含电机、部件业界的各公司取得进展。无铅焊接与Pb-Sn共晶焊接相比,由于融点高,在反流工序的设定温度也变高,可容易地进行前述的金属扩散,事实上,连接界面中的裂纹和外部端子脱落的发生频度比传统高。
发明内容
本发明的目的是提供:可增大焊盘部和外部端子的连接力、可靠地防止脱落、确保长期连接可靠性的半导体装置及其制造方法。
为了达到上述目的,第1发明的半导体装置,在半导体元件上形成使金属配线间绝缘的绝缘树脂层,金属配线的端部与半导体元件上的电极连接,金属配线的其他端部作为焊盘与外部端子连接,除了焊盘的连接部分,被表层树脂层被覆,其中,焊盘中至少一个焊盘部的上面设置突起。
根据该构成,焊接连接时外部端子从周围捕捉焊盘部的突起,可可靠地连接外部端子和焊盘部。结果,可获得确保长期连接可靠性的半导体装置。
第2发明的半导体装置,是第1发明的半导体装置中,焊盘部的上面设置的突起的上部的至少一部分为比下部伸出的形状。
根据该构成,由于成为外部端子脱落方向的障碍,因而可增大焊盘部和外部端子的连接力,可靠地防止脱落。
第3发明的半导体装置,是第1发明的半导体装置中,焊盘部的上面设置的突起的侧壁的至少一部分是倒锥体形状。
根据该构成,由于成为外部端子脱落方向的障碍,因而可增大焊盘部和外部端子的连接力,可靠地防止脱落。
第4发明的半导体装置,是第2或3发明的半导体装置中,焊盘部的上面设置的突起的平面形状,在与接近焊盘部的半导体装置的外形缘部成直角方向上形成长度方向。
根据该构成,通过相对于机械外力附加方向使突起的平面形状的长度方向一致,可阻碍机械外力,因而可保持外部端子的连接。
第5发明的半导体装置,是第2或3发明的半导体装置中,焊盘部的上面设置的突起的平面形状,在从半导体装置的平面图上的中心呈放射状方向上形成长度方向。
根据该构成,通过相对于热应力附加方向使突起的平面形状的长度方向一致,可阻碍热应力,因而可保持外部端子的连接。
第6发明的半导体装置,是第2或3发明的半导体装置中,半导体装置的对角线上配置的焊盘中,至少一个焊盘部的上面设置的突起的平面形状,是在与接近焊盘部的半导体装置的2个外形缘部成直角方向上具有2个方向的长度方向的十字形或L字形。
根据该构成,通过相对于角部附近中机械外力附加的2方向使突起的平面形状的长度方向一致,可阻碍2方向的机械外力,因而可保持外部端子的连接。
第7发明的半导体装置,是第2或3发明的半导体装置中,从半导体装置的外形缘部的附近到内侧多列配置的焊盘中,在从外周开始的至少1列四周的焊盘部的上面设置突起,在从内侧开始的至少1列的焊盘部不设置突起。
根据该构成,相对于由半导体装置的平面图上离中心的距离越远越大的热膨张差引起的热应力来配置突起,可保持外部端子的连接。
第8发明的半导体装置,是第2或3发明的半导体装置中,通过在焊盘部的上面并列配置多个突起,在与接近焊盘部的半导体装置的外形缘部成直角方向上,形成突起的平面形状的长度方向。
第9发明的半导体装置,是第2或3发明的半导体装置中,通过在焊盘部的上面并列配置多个突起,在从半导体装置的平面图上的中心开始的放射状方向上,形成突起的平面形状的长度方向。
第10发明的半导体装置,是第2或3发明的半导体装置中,形成突起,使得焊盘部的上面设置的突起的平面形状中,在与接近焊盘部的半导体装置的外形缘部成直角方向上形成长度方向,且相对于长度方向的长度的宽度在中途发生变化。
第11发明的半导体装置,是第2或3发明的半导体装置中,形成突起,使得焊盘部的上面设置的突起的平面形状中,在半导体装置的平面图上的中心开始的放射状方向上形成长度方向,且相对于长度方向的长度的宽度在中途发生变化。
根据第8~11发明的构成,可增加阻碍外部端子脱落方向的面积,增大焊盘部和外部端子的连接力,防止脱落。
第12发明的半导体装置,是第2或3发明的半导体装置中,形成突起,使得焊盘部的上面设置的突起的平面形状是,在接近焊盘部的半导体装置的2个外形缘部成直角方向上具有2方向的长度方向的十字形,相对于长度方向的长度的宽度在中途发生变化。
根据该构成,通过相对于角部附近中机械外力附加的2方向使突起的平面形状的长度方向一致,可阻碍2方向的机械外力,且增加阻碍外部端子脱落方向的面积,增大焊盘部和外部端子的连接力,防止脱落。
第13发明的半导体装置,是第2或3发明的半导体装置中,形成突起,使得焊盘部的上面设置的突起的平面形状是具有多方向的长度方向的放射形,相对于长度方向的长度的宽度在中途发生变化。
根据该构成,突起的平面形状形成无方向性的构成。因而,可与半导体装置内的焊盘的位置关系无关地进行配置,且可增加阻碍外部端子脱落方向的面积,因而可增大焊盘部和外部端子的连接力,防止脱落。
第14发明的半导体装置,是第2或3发明的半导体装置中,形成突起,使得焊盘部的上面设置的突起的平面形状中对轮廓倒角形成角部的角度在120°以上,或者,通过向角部附加圆角,排除角部的边缘。
根据该构成,可缓和集中到外部端子的应力,防止外部端子的裂纹及脱落。
第15发明的半导体装置,是第2或3发明的半导体装置中,焊盘部的上面设置的突起的平面形状相对于焊盘部的外周轮廓或焊盘部上的保护膜开口的轮廓不伸出也不连接,而是相对于外周轮廓或焊盘部上的保护膜开口的轮廓在内侧形成突起。
根据该构成,突起被构成外部端子的材料包围,因而构成外部端子的材料可从四周捕捉突起,可防止以突起为起点的外部端子的变形和裂纹,防止外部端子的脱落。
第16发明的半导体装置的制造方法,在半导体元件上形成使金属配线间绝缘的绝缘树脂层,将金属配线的端部与半导体元件上的电极连接,金属配线的其他端部作为焊盘与外部端子连接,其中,焊盘中至少一个焊盘部上,形成具有侧壁为正锥体的开口部的电镀保护膜,通过电解电镀法在开口部形成侧壁为倒锥体形状的突起。
根据该构成,可在焊盘部的突起中采用倒锥体形状,阻碍外部端子脱落方向,因而可增大焊盘部和外部端子的连接力,可靠地防止脱落。
第17发明的半导体装置的制造方法,在半导体元件上形成使金属配线间绝缘的绝缘树脂层,将金属配线的端部与半导体元件上的电极连接,金属配线的其他端部作为焊盘与外部端子连接,其中,焊盘中至少一个焊盘部上,形成具有开口部的电镀保护膜,通过电解电镀法在开口部析出超过电镀保护膜的膜厚的金属,形成其上部的至少一部分比下部伸出的形状的突起。
根据该构成,可使焊盘部的突起中的上部为比下部伸出的形状,阻碍外部端子脱落方向,因而可增大焊盘部和外部端子的连接力,可靠地防止脱落。
第18发明的半导体装置的制造方法,在半导体元件上形成使金属配线间绝缘的绝缘树脂层,将金属配线的端部与半导体元件上的电极连接,金属配线的其他端部作为焊盘与外部端子连接,其中,形成树脂膜的工序中,在与焊盘部对应部分中至少一个部分的树脂上,形成侧壁为倒锥体形状的树脂突起,在形成金属配线的金属蒸镀及电镀工序中,通过在树脂突起形成焊盘部,在焊盘部内形成一部分突起。
根据该构成,沿树脂突起的形状通过电镀析出金属,使焊盘部上形成突起,可以可靠地连接外部端子和焊盘部。
附图说明
图1是本发明第1实施例的半导体装置的截面图。
图2是本发明第2实施例的半导体装置的截面图。
图3是本发明第3实施例中的外部端子搭载前的半导体装置的平面图。
图4是本发明第4实施例中的外部端子搭载前的半导体装置的平面图。
图5是本发明第5实施例中的半导体装置的截面图。
图6A~C是本发明第6实施例中的外部端子搭载前的焊盘上突起的平面图。
图7A、B是本发明第6实施例中的外部端子搭载前的半导体装置的角部部分的平面图。
图8是本发明第7实施例中的外部端子搭载前的焊盘上突起的平面图。
图9是本发明第8实施例中的外部端子搭载前的焊盘上突起的平面图。
图10是本发明第9的实施例中的外部端子搭载前的焊盘上突起的平面图。
图11是本发明第10实施例中的外部端子搭载前的焊盘上突起的平面图。
图12A~C是本发明的半导体装置的制造方法的实施例中的制造工序的截面图。
图13A~C是本发明的半导体装置的制造方法的实施例中的制造工序的截面图。
图14A~C是本发明的半导体装置的制造方法的实施例中的制造工序的截面图。
图15是本发明的半导体装置的制造方法的实施例中的制造工序的截面图。
图16是本发明的半导体装置的制造方法的实施例中的半导体装置的电镀保护膜形成后的状态的平面图。
图17A~C是本发明的半导体装置的制造方法的其他实施例中的制造工序的截面图。
图18是本发明的半导体装置的制造方法的实施例的变形例中的制造工序的截面图。
图19是本发明的半导体装置的制造方法的各实施例的变形例中的半导体装置的截面图。
图20是表示半导体装置的部分开口的透视图。
图21A~C是传统的半导体装置的制造工序的截面图。
图22A~C是传统的半导体装置的制造工序的截面图。
图23A、B是传统的半导体装置的制造工序的截面图。
图24A、B是传统的半导体装置的检查工序后的焊盘连接界面的裂纹的截面图。
图25A、B是传统的半导体装置的焊盘部连接面积增加方法的截面图。
具体实施方式
以下,作为本发明的实施例,以WLCSP为例参照图面进行说明。
本发明第1实施例根据图1进行说明。图1是本发明第1实施例的半导体装置的截面图。
图1中,与图20相同的构成要素采用相同符号,其说明省略。如图1所示,金属配线7a间绝缘的绝缘树脂层4在半导体元件1上形成,金属配线7a的端部与半导体元件1上的电极2连接,金属配线7a的其他端部作为焊盘与外部端子9连接,除了焊盘的连接部分,被表层树脂层8被覆。,焊盘中至少一个焊盘部7b的上面设有突起10。该场合,焊盘部7b上的突起上部10a形成比下部10b伸出的形状。
突起10是通过电镀析出Cu等的金属,电镀工序中,通过电镀析出金属,其厚度超过第2层电镀保护膜6b的膜厚(图18)。伸出在突起侧壁的大致四周形成时,伸出量为0.2μm以上,即使突起厚0.5μm左右也有效果。但是外部端子9的连接工序中,焊接剂不进入,产生空隙,反而降低连接可靠性,因而突起10的高度和伸出量的比率(纵横比)最好在1以下。
根据本实施例,焊盘部上突起的形成工序中,突起的一部分中,上部形成比下部伸出的形状,从而与外部端子焊接连接时,伸出的部分形成阻挡外部端子脱落的形状,因而可构造成防止外部端子的脱落。
本发明第2实施例根据图2说明。图2是本发明第2实施例的半导体装置的截面图。
图2中与图1相同构成要素采用相同符号,其说明省略。
如图2所示,焊盘部7b上的突起10的轮廓侧壁的一部分形成倒锥体(根切)形状。突起10侧壁的大致四周形成倒锥体形状的场合,突起的厚度为0.5~2μm,锥体的角度为15°~30°左右有效。
本发明第3实施例根据图3进行说明。图3是本发明第3实施例的半导体装置的外部端子搭载前的平面图。
图3中与图1相同构成要素采用相同符号,其说明省略。
如图3所示,最外周焊盘部7b上的突起10的平面形状相对于半导体装置邻接的外形缘部,在直角方向上形成长度方向。另外,4角部的焊盘部7b上设的突起10的平面形状是相对于半导体装置的2个邻接外形缘部成直角方向的具有2方向的长度方向的L字型。这是因为,最外周的外部端子经常在安装后的检查工序及安装工序等中从半导体装置侧面方向受到机械外力。从而,4角部的外部端子有必要对抗来自2方向的机械外力,角部焊盘上的突起10最好采用L字型、十字形的平面形状。
另外,也可以采用在从半导体装置的外形缘部的附近向内侧多列配置的焊盘中,从外周开始在至少1列四周的焊盘部的上面设置突起,从内侧开始在至少1列的焊盘部不设置突起的构成。
本发明第4实施例根据图4进行说明。图4是本发明第4实施例的半导体装置的外部端子搭载前的平面图。
图4中,与图1相同构成要素采用相同符号,其说明省略。
如图4所示,焊盘部7b上的突起10的平面形状以半导体装置的平面图上中心呈放射状方向上形成长度方向。这是因为,除最外周的一般的外部端子在安装基板后的检查工序及安装工序、与安装后的外部装置连接的状态下,外部端子被施加热膨张差导致的热应力,热膨张差在半导体装置的平面图上的中心为0,随着离中央的距离越远变得越大,发生应力的方向从半导体装置的中心呈放射状。从而,半导体装置中央部焊盘部7b上的突起10的效果减小,可以省略。
本发明第5实施例根据图5进行说明。图5是本发明第5实施例的半导体装置的截面图。
图5中与图1相同构成要素采用相同符号,其说明省略。
如图5所示,焊盘部7b的下部形成树脂突起12,沿上述树脂突起形状通过电镀析出金属,形成突起10。突起10的轮廓侧壁的一部分形成倒锥体(根切)形状。在突起10侧壁的大致四周形成倒锥体形状的场合,突起10的厚度为0.5~2μm,锥体的角度为15°~30°左右有效。通过形成树脂突起12,由于与实施例1、2同样地在焊盘部7b上形成金属突起10,因而效果也与实施例1、2相同。
图6~11表示焊盘上突起的其他实施例。作为实施例6,图6A~C所示的突起10是将图3所示椭圆状的突起在长度方向上分割成多个。在一个焊盘部7b的上面通过并列配置多个突起10,形成长度方向。该场合,突起10分割成2个,图6A中平面形状是圆形,B中相对部大致平行,C中相对部凹陷。从而,成为外部端子脱落方向的障碍的面积增加,焊盘部7b和外部端子的连接力增大,可防止脱落。
此时的半导体装置角部部分的焊盘上,如图7A、B所示,形成与一个椭圆状突起时的图3、4同样的配置。即,图7A中,4角部的焊盘部7b上设有的多个突起10配置成相对于半导体装置的2个邻接外形缘部呈直角方向的具有2方向的长度方向L字型。图7B中,焊盘部7b上的多个突起10配置成在从半导体装置的平面图上中心呈放射状方向上形成长度方向。
作为实施例7,图8所示的突起10的平面形状中,形成相对于长度方向的长度,宽度(宽度方向的长度)中途发生变化的突起10。从而,成为外部端子脱落方向的障碍的面积增加,焊盘部7b和外部端子的连接力增大,可防止脱落。
作为实施例8,图9所示的突起10的平面形状中,突起10是相对于接近焊盘部7b的半导体装置的2个外形缘部呈直角方向的具有2方向长度方向的十字形,相对于长度方向的长度,宽度(宽度方向的长度)中途发生变化。从而,角部附近中机械外力附加的2方向与突起10的平面形状的长度方向一致,对来自2方向的机械外力形成障碍,且外部端子脱落方向的障碍面积增加,焊盘部7b和外部端子的连接力增大,可防止脱落。
作为实施例9,图10所示的突起10是平面形状中具有多方向的长度方向的放射形,相对于长度方向的长度,宽度在中途发生变化地形成突起10。突起10的平面形状由于没有方向性,因而可以与半导体装置内的焊盘的位置关系无关地进行配置,且可增加外部端子脱落方向的障碍面积。因而,焊盘部7b和外部端子的连接力增大,可防止脱落。
作为实施例10,图11所示的突起10通过在平面形状中对轮廓倒角形成角部的角θ在120°以上,排除了突起10的平面形状中的角部的边缘,因而可缓和集中到外部端子的应力,可防止外部端子的裂纹及脱落。也可以在图3、4、6~10所示的角部附加圆角。
另外,上述各实施例中,焊盘部的上面设置的突起10的平面形状相对于焊盘部7b的外周轮廓或焊盘部7b上的保护膜开口的轮廓不伸出也不连接,而是相对于外周轮廓或焊盘部7b上的保护膜开口的轮廓在内侧形成突起10,以构成外部端子的材料包围突起10,因而,构成外部端子的材料从四周捕捉突起10,可防止以突起10为起点的外部端子的变形和裂纹,防止外部端子的脱落。
以下,更具体地进行说明。
图12~15是表示本发明的半导体装置的制造方法的实施例的工序的其他截面图。本实施例涉及实施例2的半导体装置的制造方法。如图12A所示,在构图并层叠了绝缘树脂层4的半导体元件1上的整个面,通过溅射法等的各向异性蒸镀工序形成蒸镀金属层5(图12B)。此时作为蒸镀金属层5,首先形成金属阻挡层,在真空状态下形成延伸的电镀板层。另外,在溅射之前,通过等离子处理使绝缘树脂层4的露出表面微细地粗化,提高绝缘树脂层4和金属阻挡层的粘合强度。
通过上述等离子处理,绝缘树脂层4的表面被部分灰化除去,半导体元件电极2表面附着的树脂残留也被除去。因而,等离子处理方法和反应气体若能够对半导体元件电极2和钝化膜3选择性地蚀刻绝缘树脂层4的树脂就可以,这里采用RIE(Reactive Ion Etching)处理法和O2气和N2气或O2气和CF4气的混合气体等。
金属阻挡层具有与绝缘树脂层4或半导体元件电极2、钝化膜3的强粘合强度,且对电镀板层的蚀刻液具有阻挡性的金属,例如采用Cr等。作为电镀板层必须是电解电镀中电阻率低的金属,一般采用Cu。金属阻挡层的厚度从对电镀板层的蚀刻液的阻挡性的观点看,采用0.1到0.2μm左右,电镀板层的厚度从电气电阻和析出应力和蚀刻的容易度的观点看,采用0.2到0.5μm左右用。接着在电镀板层上涂敷感光性保护膜材料。然后通过干燥、曝光、显影感光性保护膜材料,形成电镀保护膜6a(图12C)。然后,通过O2气的等离子处理除去电镀保护膜6a的显影残留。
接着,通过电解Cu电镀法,在电镀保护膜6a开口、板层露出的部分选择地形成厚膜金属层7(图13A)。上述厚膜金属层7构成金属配线7a及焊盘部7b。厚膜金属层7的厚度从电气电阻和机械强度及生产性的观点看,形成5到11μm左右的厚度。
接着,再次涂敷感光性保护膜材料。然后通过干燥、曝光、显影感光性保护膜材料形成电镀保护膜6b,使在至少一个金属焊盘部7b上的一部分中开口(图13B)。由于这里电镀保护膜开口部6c的侧壁形成正锥体,因而作为电镀保护膜6b,使用正片型的感光性树脂,适当设定干燥、曝光条件。电镀保护膜6b的开口构图如图16所示。为了仅仅在期望的保护膜开口部分透过光,以其他部分作为Ni电镀的曝光用掩模使电镀保护膜6b被开口。这里在最外周焊盘中,形成相对于半导体装置外形的边缘成直角的长度方向,最外周的角部的焊盘形成与邻接2个边缘成直角的L型,对来自半导体装置侧面方向的外力增加强度。从外周开始的第2、3列形成从半导体装置中心呈放射状的长度方向,以实现对热膨张差增加强度。中央部的焊盘为了获得强度平衡,电镀保护膜不开口,不设置突起。另外,形成突起各开口部为了使与外部端子连接时的应力避免集中,在本实施例中设置角部R以消除平面上的边缘。然后,通过O2气的等离子处理,除去电镀保护膜的显影残留。
接着通过电解Cu电镀法,在电镀保护膜6b开口、金属焊盘部7b露出的部分选择地形成金属层(图13C)。上述金属层构成焊盘部7b上的突起10。突起10的轮廓侧壁为了转写电镀保护膜6b的开口部侧壁的形状,形成倒锥体形状。突起10形成后剥离除去电镀保护膜6,而且通过O2等离子的等离子处理除去电镀保护膜6的剥离残留(图14A)。
接着,若用Cu蚀刻液全面Cu蚀刻板层和厚膜金属层7,则比厚膜金属层7层厚薄的板层的Cu被先行除去(图14B)。此时板层的蚀刻液采用不溶金属阻挡层但可选择地蚀刻板层的溶液。接着通过全面蚀刻金属阻挡层,形成具有期望图案的金属配线7a及金属焊盘7b。
接着在绝缘树脂层4、厚膜金属层7上涂敷感光性树脂,然后干燥、曝光,显影除去焊盘7b上及其他不需要的感光性树脂后,硬化形成焊料保护膜层8(图14C)。
然后在金属焊盘7b上印刷焊接剂,熔融形成外部端子9(图15)。这里作为印刷熔融焊接剂的替代,也可以搭载熔融低融点金属球来形成外部端子9。另外,形成突起的电镀工序中,也可通过电镀析出超过电镀保护膜的膜厚的金属,形成突起的上部比下部伸出的形状。为了说明该突起形成方法,电镀工序后的状态如图18A所示,保护膜剥离后的状态如图18B所示。该场合,电镀保护膜开口部6c的侧壁的锥体可以是正锥体也可以是倒锥体。
图17是表示本发明的半导体装置的制造方法的其他实施例的工序的其他截面图。本实施例涉及实施例5的半导体装置。如图17A所示,构图并层叠了绝缘树脂层4的半导体元件1上,在后续的工序中,在形成焊盘的部分中至少一个部分的树脂上进一步层叠形成树脂膜,形成树脂突起12(图17B)。此时树脂突起12的侧壁为了形成倒锥体,使用负片型的感光性树脂,适当设定干燥、曝光、显影、后硬化条件。接着通过无电解电镀形成金属层5(图17C)。金属层5构成电解电镀工序的板层。另外,在无电解电镀之前,通过等离子处理使绝缘树脂层4的露出表面微细地粗化,提高绝缘树脂层4和金属阻挡层的粘合强度。
通过上述等离子处理,绝缘树脂层4的表面被部分灰化除去,半导体元件电极2表面附着的树脂残留也被除去。因而,等离子处理方法和反应气体若能够对半导体元件电极2和钝化膜3选择性地蚀刻绝缘树脂层4的树脂就可以,这里采用RIE(Reactive Ion Etching)处理法和O2气和N2气或O2气和CF4气的混合气体等。
电镀保护膜形成工序以下与传统例相同,因而省略了制造工序,形成金属配线的金属蒸镀及电镀工序中,通过在树脂突起12形成焊盘部,在焊盘部内形成一部分突起。
另外,制造方法的各实施例都可以在焊料保护膜8形成后,通过电解电镀法或无电解电镀法在焊盘部7b的保护膜开口部析出镍镀层、金镀层等,形成表面处理层11(图19A、B)。
镍镀层用于防止焊接连接的外部端子的金属材料和构成焊盘的金属材料扩散形成脆合金层,金镀层用于防止焊盘表面氧化使得焊接连接时的粘合力降低。
根据相关构成,通过采用焊盘的突起部中上部比下部伸出的形状或倒锥体形状,可形成阻碍外部端子脱落方向的机械构造,因而可实现增加焊盘部和外部端子的连接力,可靠地防止连接界面的裂纹和外部端子的脱落,确保长期连接可靠性的半导体装置。
另外,虽然以WLCSP为例作为本实施例,但是取代晶片,通过在BGA等的基板上以规定的形状层叠形成绝缘树脂层、金属层、焊料保护膜,与WLCSP的场合完全一样地,可作成在焊盘形成有突起的BGA用基板。

Claims (18)

1.一种半导体装置,在半导体元件上形成使金属配线间绝缘的绝缘树脂层,上述金属配线的端部与上述半导体元件上的电极连接,上述金属配线的其他端部作为焊盘与外部端子连接,除了上述焊盘的连接部分,被表层树脂层被覆,其中,上述焊盘中至少一个焊盘部的上面设置突起。
2.权利要求1所述的半导体装置,其特征在于,
上述焊盘部的上面设置的突起的上部的至少一部分为比下部伸出的形状。
3.权利要求1所述的半导体装置,其特征在于,
上述焊盘部的上面设置的突起的侧壁的至少一部分是倒锥体形状。
4.权利要求2或3所述的半导体装置,其特征在于,
上述焊盘部的上面设置的突起的平面形状,在与接近上述焊盘部的半导体装置的外形缘部成直角方向上形成长度方向。
5.权利要求2或3所述的半导体装置,其特征在于,
上述焊盘部的上面设置的突起的平面形状,在从半导体装置的平面图上的中心呈放射状方向上形成长度方向。
6.权利要求2或3所述的半导体装置,其特征在于,
上述半导体装置的对角线上配置的焊盘中,至少一个焊盘部的上面设置的突起的平面形状,是在与接近上述焊盘部的半导体装置的2个外形缘部成直角方向上具有2个方向的长度方向的十字形或L字形。
7.权利要求2或3所述的半导体装置,其特征在于,
从上述半导体装置的外形缘部的附近到内侧多列配置的焊盘中,在从外周开始的至少1列四周的焊盘部的上面设置突起,在从内侧开始的至少1列的焊盘部不设置突起。
8.权利要求2或3所述的半导体装置,其特征在于,
通过在上述焊盘部的上面并列配置多个突起,在与接近上述焊盘部的半导体装置的外形缘部成直角方向上,形成突起的平面形状的长度方向。
9.权利要求2或3所述的半导体装置,其特征在于,
通过在上述焊盘部的上面并列配置多个突起,在从半导体装置的平面图上的中心开始的放射状方向上,形成突起的平面形状的长度方向。
10.权利要求2或3所述的半导体装置,其特征在于,
形成突起,使得上述焊盘部的上面设置的突起的平面形状中,在与接近上述焊盘部的半导体装置的外形缘部成直角方向上形成长度方向,且相对于长度方向的长度的宽度在中途发生变化。
11.权利要求2或3所述的半导体装置,其特征在于,
形成突起,使得上述焊盘部的上面设置的突起的平面形状中,在半导体装置的平面图上的中心开始的放射状方向上形成长度方向,且相对于长度方向的长度的宽度在中途发生变化。
12.权利要求2或3所述的半导体装置,其特征在于,
形成突起,使得上述焊盘部的上面设置的突起的平面形状是,在接近上述焊盘部的半导体装置的2个外形缘部成直角方向上具有2方向的长度方向的十字形,相对于长度方向的长度的宽度在中途发生变化。
13.权利要求2或3所述的半导体装置,其特征在于,
形成突起,使得上述焊盘部的上面设置的突起的平面形状是具有多方向的长度方向的放射形,相对于长度方向的长度的宽度在中途发生变化。
14.权利要求2或3所述的半导体装置,其特征在于,
形成突起,使得上述焊盘部的上面设置的突起的平面形状中对轮廓倒角形成角部的角度在120°以上,或者,通过向角部附加圆角,排除角部的边缘。
15.权利要求2或3所述的半导体装置,其特征在于,
上述焊盘部的上面设置的突起的平面形状相对于上述焊盘部的外周轮廓或上述焊盘部上的保护膜开口的轮廓不伸出也不连接,而是相对于外周轮廓或上述焊盘部上的保护膜开口的轮廓在内侧形成突起。
16.一种半导体装置的制造方法,在半导体元件上形成使金属配线间绝缘的绝缘树脂层,将上述金属配线的端部与上述半导体元件上的电极连接,上述金属配线的其他端部作为焊盘与外部端子连接,其中,上述焊盘中至少一个焊盘部上,形成具有侧壁为正锥体的开口部的电镀保护膜,通过电解电镀法在上述开口部形成侧壁为倒锥体形状的突起。
17.一种半导体装置的制造方法,在半导体元件上形成使金属配线间绝缘的绝缘树脂层,将上述金属配线的端部与上述半导体元件上的电极连接,上述金属配线的其他端部作为焊盘与外部端子连接,其中,上述焊盘中至少一个焊盘部上,形成具有开口部的电镀保护膜,通过电解电镀法在上述开口部析出超过上述电镀保护膜的膜厚的金属,形成其上部的至少一部分比下部伸出的形状的突起。
18.一种半导体装置的制造方法,在半导体元件上形成使金属配线间绝缘的绝缘树脂层,将上述金属配线的端部与上述半导体元件上的电极连接,上述金属配线的其他端部作为焊盘与外部端子连接,其中,形成上述树脂膜的工序中,在与上述焊盘部对应部分中至少一个部分的树脂上,形成侧壁为倒锥体形状的树脂突起,在形成上述金属配线的金属蒸镀及电镀工序中,通过在上述树脂突起形成上述焊盘部,在焊盘部内形成一部分突起。
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US8574959B2 (en) 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
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US8129841B2 (en) 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
US8216930B2 (en) 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
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US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
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JP4287421B2 (ja) * 2005-10-13 2009-07-01 株式会社ルネサステクノロジ 半導体装置の製造方法
JP4305667B2 (ja) 2005-11-07 2009-07-29 セイコーエプソン株式会社 半導体装置
JP5502257B2 (ja) * 2006-08-29 2014-05-28 セイコーインスツル株式会社 半導体装置
JP2009246166A (ja) * 2008-03-31 2009-10-22 Fujitsu Ltd 電子部品パッケージおよび基板ユニット並びにプリント配線板およびその製造方法
KR100979497B1 (ko) * 2008-06-17 2010-09-01 삼성전기주식회사 웨이퍼 레벨 패키지 및 그 제조방법
CN100595897C (zh) * 2008-08-20 2010-03-24 晶方半导体科技(苏州)有限公司 晶圆级封装对象及其形成的方法
US20100237500A1 (en) * 2009-03-20 2010-09-23 Stats Chippac, Ltd. Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site
KR101141209B1 (ko) * 2010-02-01 2012-05-04 삼성전기주식회사 단층 인쇄회로기판 및 그 제조방법
JP5655443B2 (ja) * 2010-09-06 2015-01-21 住友電気工業株式会社 無機化合物膜のエッチング方法および半導体光素子の製造方法
JP6081044B2 (ja) 2010-09-16 2017-02-15 富士通株式会社 パッケージ基板ユニットの製造方法
US8304867B2 (en) * 2010-11-01 2012-11-06 Texas Instruments Incorporated Crack arrest vias for IC devices
US9184144B2 (en) 2011-07-21 2015-11-10 Qualcomm Incorporated Interconnect pillars with directed compliance geometry
KR101939240B1 (ko) * 2011-11-25 2019-01-17 삼성전자 주식회사 반도체 패키지
US8847391B2 (en) 2012-07-09 2014-09-30 Qualcomm Incorporated Non-circular under bump metallization (UBM) structure, orientation of non-circular UBM structure and trace orientation to inhibit peeling and/or cracking
US9761549B2 (en) * 2012-11-08 2017-09-12 Tongfu Microelectronics Co., Ltd. Semiconductor device and fabrication method
US9368461B2 (en) * 2014-05-16 2016-06-14 Intel Corporation Contact pads for integrated circuit packages
KR102323250B1 (ko) * 2015-05-27 2021-11-09 삼성전자주식회사 반도체 발광소자 제조방법
CN108346618B (zh) * 2017-01-25 2021-09-21 中芯国际集成电路制造(上海)有限公司 半导体器件及其制作方法、电子装置
JP2020150172A (ja) 2019-03-14 2020-09-17 キオクシア株式会社 半導体装置
US11705378B2 (en) * 2020-07-20 2023-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
CN113113374A (zh) * 2021-04-08 2021-07-13 重庆群崴电子材料有限公司 一种封装用圆球及其封装结构

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3378334B2 (ja) 1994-01-26 2003-02-17 株式会社東芝 半導体装置実装構造体
JPH10209591A (ja) 1997-01-20 1998-08-07 Ngk Spark Plug Co Ltd 配線基板
JP3335575B2 (ja) 1997-06-06 2002-10-21 松下電器産業株式会社 半導体装置およびその製造方法
JP3416040B2 (ja) 1997-11-11 2003-06-16 富士通株式会社 半導体装置
JP3753218B2 (ja) * 1998-03-23 2006-03-08 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
US6181010B1 (en) * 1998-03-27 2001-01-30 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board and electronic instrument
JPH11297873A (ja) 1998-04-13 1999-10-29 Seiko Epson Corp 半導体装置およびその製造方法
JPH11354563A (ja) 1998-06-11 1999-12-24 Citizen Watch Co Ltd 半導体配線の構造
KR100298827B1 (ko) * 1999-07-09 2001-11-01 윤종용 재배선 기판을 사용한 웨이퍼 레벨 칩 스케일 패키지 제조방법
JP3386029B2 (ja) * 2000-02-09 2003-03-10 日本電気株式会社 フリップチップ型半導体装置及びその製造方法
JP3629178B2 (ja) * 2000-02-21 2005-03-16 Necエレクトロニクス株式会社 フリップチップ型半導体装置及びその製造方法
JP4313520B2 (ja) 2001-03-19 2009-08-12 株式会社フジクラ 半導体パッケージ
JP2003332360A (ja) * 2002-05-17 2003-11-21 Denso Corp 半導体装置

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7791186B2 (en) 2005-10-12 2010-09-07 Nec Corporation Wiring board, semiconductor device in which wiring board is used, and method for manufacturing the same
US7880295B2 (en) 2005-10-12 2011-02-01 Nec Corporation Wiring board, semiconductor device in which wiring board is used, and method for manufacturing the same
CN101533824B (zh) * 2005-10-12 2012-11-21 日本电气株式会社 配线板、半导体器件及制造配线板和半导体器件的方法
CN102484101A (zh) * 2009-08-13 2012-05-30 SKLink株式会社 电路基板及其制造方法
CN102244041A (zh) * 2010-03-24 2011-11-16 瑞萨电子株式会社 半导体器件
CN102244041B (zh) * 2010-03-24 2015-05-06 瑞萨电子株式会社 半导体器件
CN102157477A (zh) * 2011-03-23 2011-08-17 南通富士通微电子股份有限公司 半导体装置的制造方法
CN102157477B (zh) * 2011-03-23 2012-10-03 南通富士通微电子股份有限公司 半导体装置的制造方法
CN103378040A (zh) * 2012-04-11 2013-10-30 台湾积体电路制造股份有限公司 半导体器件封装件及半导体器件封装方法
CN103378040B (zh) * 2012-04-11 2016-08-03 台湾积体电路制造股份有限公司 半导体器件封装件及半导体器件封装方法
CN104576576A (zh) * 2013-10-25 2015-04-29 日月光半导体制造股份有限公司 半导体封装件及其制造方法
CN104392978A (zh) * 2014-11-04 2015-03-04 上海兆芯集成电路有限公司 线路基板和半导体封装结构
US9601425B2 (en) 2014-11-04 2017-03-21 Via Alliance Semiconductor Co., Ltd. Circuit substrate and semiconductor package structure
CN104392978B (zh) * 2014-11-04 2017-04-12 上海兆芯集成电路有限公司 线路基板和半导体封装结构
US10204852B2 (en) 2014-11-04 2019-02-12 Via Alliance Semiconductor Co., Ltd. Circuit substrate and semiconductor package structure
CN104409435A (zh) * 2014-11-07 2015-03-11 三星半导体(中国)研究开发有限公司 一种包含具有倾斜侧壁的凸起的焊盘
CN106601632A (zh) * 2015-10-14 2017-04-26 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法
CN105570736A (zh) * 2015-12-11 2016-05-11 苏州达方电子有限公司 光源装置
CN105570736B (zh) * 2015-12-11 2018-08-31 苏州达方电子有限公司 光源装置
CN108493205A (zh) * 2018-04-10 2018-09-04 武汉新芯集成电路制造有限公司 一种消除铝垫与显影液反应缺陷的方法

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