CN1601729A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN1601729A
CN1601729A CNA2004100447543A CN200410044754A CN1601729A CN 1601729 A CN1601729 A CN 1601729A CN A2004100447543 A CNA2004100447543 A CN A2004100447543A CN 200410044754 A CN200410044754 A CN 200410044754A CN 1601729 A CN1601729 A CN 1601729A
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semiconductor chip
electrode
jut
resin
film substrate
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CN100353533C (zh
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濑古敏春
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Sharp Corp
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Sharp Corp
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Abstract

半导体器件包括：具有配置在其表面上的布线图形的膜基板；安装在膜基板上并具有配置在其表面上的电极的半导体芯片；以及配置在膜基板与半导体芯片之间的绝缘树脂部，该树脂部通过将绝缘树脂涂敷在膜基板和半导体芯片的至少一方上并在将半导体芯片安装在膜基板上时在膜基板与半导体芯片之间限定的空间充填树脂而形成，其中，布线图形有一突起部，其剖面形状为朝向半导体芯片的电极而逐渐变细并凸入电极中，从而与电极进行电连接。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件及其制造方法。更具体地说，本发明涉及包含与柔性布线基板键合并安装在其上的半导体芯片的半导体器件及其制造方法。
背景技术
下述技术作为本发明的现有技术而著称。
(1)一种半导体器件制造方法，包括下述工序：在柔性布线基板上在规定的位置层叠具有Au凸点电极的半导体芯片；以每个凸点电极0.1至0.3N的压力将半导体芯片压到柔性布线基板上，同时在约为400℃至450℃的较高温度下加热半导体芯片，以便将半导体芯片的凸点电极热压焊到柔性布线基板的布线图形上；向柔性布线基板与半导体芯片之间的限定空间注入热固化树脂；使注入了的树脂热固化(例如，见日本特开2001-176918号专利公报)。
(2)一种半导体器件制造方法，包括下述工序：在柔性基板的表面涂敷光固化或热固化树脂，以覆盖配置在柔性基板上的布线图形；将半导体芯片安装在所涂敷的树脂上，并使布线图形与半导体芯片的凸点电极相向；将半导体芯片压到柔性基板上，挤出存在于布线图形与凸点电极之间的这部分树脂，以使凸点电极与布线图形接触；通过光照或在约为150℃以下的较低的温度下加热使树脂固化(例如，见日本专利第1689504号)。
(3)一种半导体器件制造方法，包括下述工序：在柔性基板的表面涂敷热固化树脂，以覆盖配置在柔性基板上的布线图形；将半导体芯片安装在所涂敷的树脂上，并使布线图形与半导体芯片的凸点电极相向；采用通电时用来发热的脉冲加热机，将半导体芯片压到柔性基板上，挤出存在于布线图形与凸点电极之间的这部分树脂，以使凸点电极与布线图形接触；对脉冲加热机通电，在约为100℃至250℃的较低的温度下加热半导体芯片，同时半导体芯片保持在压到柔性基板上的状态，使树脂固化(例如，见日本专利第2039510号)。
(4)一种半导体器件制造方法，包括下述工序：在柔性基板的表面涂敷UV固化/热固化树脂，以覆盖配置在柔性基板上的布线图形；将半导体芯片安装在所涂敷的树脂上，并使布线图形与半导体芯片的凸点电极相向；将半导体芯片压到柔性基板上，挤出存在于布线图形与凸点电极之间的这部分树脂，以使凸点电极与布线图形接触；在半导体芯片保持在压到柔性基板上的状态下，通过以紫外线照射树脂，使半导体器件周边的这部分树脂固化；通过加热使树脂完全固化(例如，见日本专利第2064463号)。
已知所谓TCP(带式载体封装)和COF(芯片安装在薄膜上)半导体器件作为包括柔性布线基板和安装在柔性布线基板上的半导体芯片的半导体器件。
在TCP器件中，柔性布线基板具有开口，并包括具有凸入开口中的末端部的布线图形，半导体芯片被安装在柔性布线基板上，以便在凸入开口中的布线图形的末端部上得到支撑。
反之，在COF器件中，柔性布线基板没有如在TCP器件中所配置的开口，半导体芯片被直接安装在柔性布线基板上。
近年来，有一种趋势是，半导体芯片具有其排列间距缩短而数目增加的管脚(凸点电极)。COF器件也应跟随这一趋势。
在COF器件的制造中，当半导体芯片在被压到柔性布线基板上的状态下被安装在柔性布线基板上时，布线图形容易变形。这可以引起所谓“边缘接触”，意味着被安装的半导体芯片的周边边缘触及布线图形。为了克服这一问题，在COF制造工艺中采用了MBB(微凸点键合)法、NCP(非导电膏)法和ACP(各向异性导电膏)法对COF器件进行键合和密封。
在MBB、NCP和ACP法中，凸点电极不像在现有技术制造方法(1)中所使用的那样在约为400℃至450℃的较高温度下被热键合到布线图形上，而是通过在约为100℃至250℃的较低的温度下使树脂固化，将凸点电极固定并连接到布线图形上。因此，MBB、NCP和ACP法被分类为用于COF制造工艺的低温键合技术。
COF器件应该满足下述要求：减少尺寸、减少厚度、减少重量，以及增加管脚数目、提高边缘接触问题的分辨率。为了同时满足这些要求，待连接到半导体芯片上的布线图形的连接部分的间距应该减少，作为柔性布线基板的基底的绝缘带的厚度和连接图形的厚度均应减少。
对于减少布线部分的间距以及减少绝缘带和布线图形的厚度的要求，其中凸点电极在约为400℃至450℃的较高温度下被热键合到布线图形上的现有技术制造方法(1)遇到下述问题。在安装时绝缘带的膨胀和收缩极大地影响了凸点电极对布线图形的定位，招致在布线图形与凸点电极之间的累计尺寸差。这使得难以在布线图形与凸点电极之间提供充分的接触面积，导致电连接不充分。另外，当半导体芯片被压到柔性布线基板上时，具有减少了厚度的布线图形更容易变形。因此，边缘接触更容易发生。
在现有技术制造方法(2)至(4)(被分类为低温键合技术)中，起因于布线图形的膨胀的累计尺寸差不太容易发生，其原因是半导体芯片在较低的温度下被加热。因为半导体芯片被安装在预先涂敷在柔性布线基板上的树脂上，并被压到柔性布线基板上，所以树脂介入布线图形与半导体芯片的周边边缘之间。因此，即使布线图形变形，边缘接触也不太容易发生。
但是，在现有技术制造方法(2)至(4)中，树脂存在于柔性布线基板与半导体芯片之间。因此，当半导体芯片被压到柔性布线基板上时，半导体芯片容易在部分存在于半导体芯片的电极与布线图形之间树脂上滑移。因此，有在布线图形与凸点电极之间发生位置偏移的可能性。另外，部分存在于布线图形与凸点电极之间的树脂会引起电连接失效。
因为低温键合技术被用来将凸点电极与布线图形连接，这种连接只通过对存在于柔性布线基板与半导体芯片之间的树脂加压并使之固化而提供的布线图形与凸点电极之间的接触来实现。因此，凸点电极以较低的机械强度被连接到布线图形上。在COF器件当使用时反覆经受低温和高温或高湿的情况下，半导体芯片可能与柔性基板分离，造成布线图形与凸点电极之间的电连接失效。
更具体地说，在COF器件当使用时因温度循环而反覆膨胀和收缩并且因吸收潮气而***的情况下，COF器件的柔性布线基板和/或半导体芯片容易因柔性布线基板与树脂之间以及半导体芯片与树脂之间的热膨胀系数的差异而与树脂分离。
此外，在加热时加压停止的状态下(恒定加热法)，生产率得到改善，但电连接失效容易发生。
发明内容
本发明是鉴于上述情况而进行的，旨在提供保证改善布线图形与凸点电极之间连接的可靠性、改善成品率和生产率的一种半导体器件及其制造方法。
按照本发明，提供一种半导体器件，该半导体器件包括：具有配置在其表面上的布线图形的膜基板；安装在膜基板上并具有配置在其表面上的电极的半导体芯片；以及配置在膜基板与半导体芯片之间的绝缘树脂部，该树脂部通过将绝缘树脂涂敷在膜基板和半导体芯片的至少一方上并在将半导体芯片安装在膜基板上时在膜基板与半导体芯片之间限定的空间充填树脂而形成，其中的布线图形有一突起部，其剖面形状为朝向半导体芯片的电极而逐渐变细并凸入电极中，从而实现与电极的电连接。
在本发明的半导体器件中，布线图形具有其剖面形状为朝向半导体芯片的电极而逐渐变细的突起部。因此，当在半导体芯片制造工艺中半导体芯片被压到膜基板上时，存在于布线图形的突起部与电极之间的这部分树脂被突起部的渐细的末端部挤出，突起部凸入电极中。因此，突起部与电极之间的电连接能够有效地实现。
这意味着即使连接只通过对树脂加压并使之固化而提供的突起部与电极之间的接触来实现，突起部与电极也能以增高了的机械强度彼此进行有效的电连接和物理连接。因为存在于突起部与电极之间的这部分树脂被突起部的渐细的末端部挤出，所以当半导体芯片被压到膜基板上时可能发生的突起部与电极之间的位置偏移受到抑制。因此，突起部与电极之间的连接的可靠性得到改善。
即使突起部与电极之间的累计尺寸差起因于在半导体器件制造工艺中对半导体芯片加热而导致膜基板的膨胀发生，突起部与电极之间的连接的可靠性也不会退降。这是由于突起部凸入电极中因而以充分的接触面积与电极连接的缘故。
即使因对半导体芯片加压而布线图形发生变形，由于绝缘树脂部介于膜基板与半导体芯片之间，所以边缘接触也会受阻。
附图说明
图1是示意性地示出本发明第1实施例的COF半导体器件的结构的图。
图2是沿图1中的A-A线所取的COF半导体器件的剖面图。
图3(a)至图7(a)和图3(b)至图7(b)是说明本发明第1实施例的COF半导体器件制造工艺的工序的图，分别表示各工序中提供的概略结构(对应于图1)和剖面(对应于图2)。
图8(a)和图9(a)以及图8(b)和图9(b)是说明本发明第2实施例的COF半导体器件制造工艺的工序的图，分别表示各工序中提供的概略结构(对应于图1)和剖面(对应于图2)。
图10是示出本发明第3实施例的COF半导体器件的放大局部图。
图11(a)至图13(a)和图11(b)至图13(b)是说明本发明第3实施例的COF半导体器件制造工艺的工序的图，分别表示各工序中提供的概略结构(对应于图1)和剖面(对应于图2)。
图14是示意性地示出本发明第4实施例的COF半导体器件的结构的图。
图15是沿图14中的B-B线所取的COF半导体器件的剖面图。
具体实施方式
本发明的半导体器件包括：具有配置在其表面上的布线图形的膜基板；安装在膜基板上并具有配置在其表面上的电极的半导体芯片；配置在膜基板与半导体芯片之间的绝缘树脂部，该树脂部通过将绝缘树脂涂敷在膜基板和半导体芯片的至少一方上并在将半导体芯片安装在膜基板上时在膜基板与半导体芯片之间限定的空间充填树脂而形成；以及其中的布线图形有一突起部，其剖面形状为朝向半导体芯片的电极而逐渐变细并凸入电极中，从而实现与电极的电连接。
布线图形是具有规定图形的诸如Cu、Al、Au或ITO之类的导电材料的薄膜。例如，通过对具有厚度约为5μm至约为18μm的铜箔构图并将铜箔图形镀锡或镀金而形成布线图形。薄膜的构图例如可通过刻蚀来实现。
膜基板是绝缘材料的柔性的可弯曲的薄膜。例如，具有厚度约为15μm至约为40μm的聚酰亚胺绝缘带可用作膜基板。
半导体芯片包括半导体基板、在半导体基板内形成的集成电路、以及配置在半导体基板的表面(与膜基板相向)上的供与布线图形电连接的电极。电极例如可以是Au的凸点电极。
绝缘树脂部例如由热固化树脂构成。热固化树脂的例子包括环氧树脂、硅酮树脂和丙烯酸树脂。在后面将要说明的本发明的半导体器件制造方法中，例如，通过配制法、印刷法等将树脂涂敷在膜基板上。
布线图形的突起部被电连接到半导体芯片的电极上，该突起部的剖面形状为朝向半导体芯片的电极而逐渐变细以便容易凸入半导体芯片的电极中。具有这一形状的突起部侧如可以通过调节刻蚀因子和图形形成时所需的布线图形的宽度而形成。
在本发明的半导体器件中，突起部可以有梯形截面形状，其末端部的宽度不大于电极的最大宽度的一半。按照这种配置，在半导体器件制造工艺中，当半导体芯片被压到膜基板上时，存在于突起部与电极之间的这部分树脂很容易被挤出，所以没有树脂残留在突起部与电极之间。此外，突起部很容易凸入电极中，并且突起部有充分的机械强度。
在本发明的半导体器件中，突起部凸入电极中的平均深度不小于电极高度的10％。按照这种配置，突起部一定被半导体芯片的电极咬住，所以突起部与电极之间的连接强度进一步得到增强。即使半导体器件在使用时因温度循环而反覆经受膨胀和收缩，或处于高湿度的环境下，半导体芯片也不太容易从膜基板分离出去。因此，布线图形与电极之间连接的可靠性能够进一步得到改善。
在本发明的半导体器件中，突起部和电极可以彼此热压键合。按照这种配置，由突起部材料与电极材料组合而成的扩散层或合金层在突起部与电极之间的连接界面内形成。因此，突起部与电极彼此更牢固地被连接在一起。即使半导体器件在使用时因温度循环而反覆经受膨胀和收缩，或处于高湿度的环境下，半导体芯片也不太容易从膜基板分离出去。因此，布线图形与电极之间连接的可靠性能够进一步得到改善。
按照本发明的另一方面，对上述发明的半导体器件提供了一种制造方法，包括下述工序：将绝缘树脂涂敷在膜基板上；将半导体芯片安装在所涂敷的树脂上，并将半导体芯片的与布线图形的突起部相向的电极配置在膜基板上；在规定的压力下将半导体芯片压到膜基板上，在规定的温度下将半导体芯片加热，从而突起部挤出存在于电极与突起部之间的这部分树脂并凸入电极中以与该电极连接，同时使树脂固化。
在该制造方法中，存在于布线图形的突起部与电极之间的这部分树脂被突起部的渐细的末端部挤出，当半导体芯片被压到膜基板上时，突起部凸入电极中。因此，能够有效地实现电连接。
这意味着即使连接只通过对树脂加压并使之固化而提供的突起部与电极之间的接触来实现，突起部与电极也能以增高了的机械强度彼此进行有效的电连接和物理连接。因为存在于突起部与电极之间的这部分树脂被突起部的渐细的末端部挤出，所以当半导体芯片被压到膜基板上时可能发生的突起部与电极之间的位置偏移受到抑制。因此，突起部与电极之间的连接的可靠性得到改善。
即使突起部与电极之间的累计尺寸差起因于对半导体芯片加热而导致膜基板的膨胀发生，突起部与电极之间的连接的可靠性也不会退降。这是由于突起部凸入电极中因而以充分的接触面积与电极连接的缘故。
即使当半导体芯片被压到膜基板上时布线图形发生变形，由于树脂被涂敷在介于膜基板与半导体芯片的周边边缘之间的膜基板上，边缘接触也会受阻。
当电极和布线图形分别由金和铜构成时，在本发明的制造方法中，可以对半导体芯片施加不低于约250×10-4gf/μm2的压力以使突起部凸入电极中。为了在半导体芯片与布线图形之间进行连接而对半导体芯片施加如此较高的压力时，布线图形很容易变形。但是，边缘接触受到介于膜基板与半导体芯片之间的树脂阻止。
在本发明的制造方法中，绝缘树脂有不高于约为210℃的固化温度。对于本情形而言，在对半导体芯片加压和加热的工序中，仅需要将半导体芯片在约为210℃或更高的温度下加热即可。在约为210℃下加热使膜基板的膨胀减至最小，因而阻止了起因于膜基板的膨胀的突起部与电极之间的累计尺寸差。在约为210℃的如此较低的加热温度被用来在半导体芯片与布线图形之间进行连接时，在突起部与电极之间的连接界面内既不形成扩散层，又不形成合金层。但是，在本发明的制造方法中，突起部凸入电极中，因而以充分的机械强度被连接到电极上去。
在本发明的制造方法中，当电极由金构成，突起部由镀锡和镀金的至少一方的导体构成时，扩散层和合金层的至少一方可以通过在不低于300℃下对半导体芯片加热以将电极热压键合到突起部上去而在电极与突起部之间的连接界面内形成。按照这种配置，由突起部材料与电极材料组合而成的扩散层和合金层的至少一方在布线图形的突起部与电极之间的连接界面内形成，所以突起部更加牢固地与电极连接在一起。  即使半导体器件在使用时因温度循环而反覆经受膨胀和收缩，或处于高湿度的环境下，半导体芯片也不太容易从膜基板分离出去。因此，布线图形与电极之间连接的可靠性能够进一步得到改善。
在本发明的制造方法中，当绝缘树脂的固化温度不高于210℃，电极由金构成，突起部由镀锡和镀金的至少一方的导体构成时，半导体芯片可以在围绕树脂的固化温度的温度下被热压以将电极与突起部连接在一起，同时使树脂固化，然后扩散层和合金层的至少一方可以通过在不低于300℃下对半导体芯片加热以将电极热压键合到突起部上去而在电极与突起部之间的连接界面内形成。
在约为210℃和约为300℃下半导体芯片的两步加热中，树脂在约为210℃的较低的温度下被固化以将突起部和电极固定在规定的连接位置上，然后半导体芯片在约为300℃的较高的温度下被加热以在突起部与电极之间的连接界面内形成由突起部材料与电极材料组合而成的扩散层和合金层的至少一方。其结果是，突起部和电极在规定的连接位置上彼此牢固地被连接在一起，从而连接的可靠性进一步得到改善。
在现有的制造方法中，当半导体芯片在约为300℃的较高温度下被加热时，担心在突起部与电极之间因膜基板的膨胀而产生累计尺寸差。但是，在本发明中，通过在约为210℃的较低的温度下使树脂固化，突起部在规定的连接位置被固定到电极上，这时，突起部凸入电极中，因而以充分的接触面积被连接到电极上。因此，在突起部与电极之间没有累计尺寸差。
在本发明的半导体器件制造方法中，半导体芯片可以被加热同时被压到膜基板上，然后在半导体芯片加压和加热工序中，对半导体芯片的加压和加热可同时停止。因为在本制造方法中加压和加热同时进行，半导体器件的生产率得到改善。
为了将半导体芯片压到膜基板上并加热半导体芯片，有下述两种类型的加热机：在对其通电后能够将半导体芯片在给定温度下加热的脉冲加热机；以及能恒定地加热半导体芯片的恒定加热机。
当使用脉冲加热机时，半导体芯片被压到膜基板上，在这种状态下，对机器通电，在给定的温度将半导体芯片加热规定的时间，然后停止通电，使半导体芯片冷却到常温，加压停止。
当使用恒定加热机时，半导体芯片被加热同时被压到膜基板上，加压和加热持续规定的时间，然后同时停止。
为了改善生产率，加压和加热同时进行的恒定加热机更为有利。在现有半导体器件的情形中，如果在加热时加压停止，半导体芯片的电极就有可能与膜基板的布线图形分离。因此，难以使用恒定加热机。
但是，在本发明中，布线图形的突起部凸入电极中供连接之用，所以在突起部与电极之间连接的机械强度得到改善。因此，即使在半导体芯片加热时对半导体芯片的加压停止，半导体芯片的电极也没有可能与膜基板的布线图形分离。当使用了在现有情况下不能使用的恒定加热机时，生产率得到改善。
在本发明的制造方法中，绝缘树脂可以包含导电粒子。
在使用了含导电粒子的绝缘树脂时，布线图形的突起部与电极彼此用存在于突起部与电极之间的连接界面内的导电粒子连接。因此，即使有一部分树脂残留在突起部与电极之间的连接界面内，突起部与电极也会通过导电粒子彼此电连接在一起。因此，连接可靠性进一步得到改善。
导电粒子可以是细金属粒子。细金属粒子的例子包括各自具有直径约为3μm至约为10μm的包金的树脂粒子和镍粒子。
此后，将参照附图通过其实施例详细地说明本发明。在下面的实施例中，同一零部件用同一参照符号表示。
第1实施例
本发明第1实施例的COF半导体器件的结构将参照图1和2进行说明。图1是示意性地示出第1实施例的COF半导体器件的结构的图，图2是沿图1中的A-A线所取的COF半导体器件的剖面图。
如图1和2所示，第1实施例的COF半导体器件包括：具有配置在其表面上的布线图形2的膜基板1；安装在膜基板1上并具有配置在其表面上的凸点电极6的半导体芯片3；以及配置在膜基板1与半导体芯片3之间的绝缘树脂部7。布线图形2包括突起部4，其剖面形状为朝向半导体芯片3的电极6而逐渐变细并分别凸入电极6中以与电极6进行电连接。
膜基板1是具有厚度约为15μm至约为40μm的聚酰亚胺带，可被柔性地弯曲。
配置在膜基板1上的布线图形2包括具有厚度约为5μm至约为18μm的镀锡或镀金(未图示)的铜箔图形。除去半导体芯片安装区和供外接的连接部以外的布线图形2的部分用阻焊剂5覆盖以便绝缘。
如上所述，各自具有逐渐变细的剖面形状(梯形剖面形状)的布线图形2的突起部4例如其下宽度W1约为10±4μm，上宽度W2约为4±3μm。另一方面，凸点电极6由Au等构成，其宽度W3约为15μm，高度约为15μm。突起部4分别凸入凸点电极6中至平均深度约为2μm，由此与凸点电极6连接。。
接着，第1实施例的COF半导体器件10的制造方法将参照图3(a)至7(a)和图3(b)至7(b)进行说明，这些图示出了第1实施例的COF半导体器件制造方法的工序。
如图3(a)至7(a)所示，准备形成有布线图形2的膜基板1。布线图形2包括配置在安装半导体芯片3(见图5(a)和5(b))的那部分上的突起部4。布线图形2的另一部分用阻焊剂5覆盖，所以突起部4从阻焊剂5中露出。
接着，如图4(a)和4(b)所示，绝缘树脂7(环氧树脂、硅酮树脂、丙烯酸树脂等)在欲安装半导体芯片3的膜基板的那部分上被涂敷到约为10μm至约为50μm的厚度。
然后，如图5(a)和5(b)所示，半导体芯片3被定位并安装在所涂敷的树脂7上，其凸点电极6隔着树脂7分别与布线图形的突起部4相向。
接着，如图 6(a)和6(b)所示，使用对其通电后适合于将芯片在给定的温度下加热的脉冲加热机在约为250×10-4gf/μm2的压力下将半导体芯片3压到膜基板1上。这时，存在于布线图形的突起部4与凸点电极6之间的树脂7的部分很容易被渐细的突起部4挤出，所以突起部4分别与凸点电极6接触而不必有树脂介入。此后，半导体芯片3再压到膜基板1上，从而渐细的突起部4与凸点电极6接触并凸入凸点电极6中某种程度，以相对于凸点电极6定位。
然后，脉冲加热机100被通电后使半导体芯片3在约为230℃至约为250℃下加热约1秒至约5秒，同时半导体芯片3保持在被压到膜基板1上的状态，从而树脂被固化。同时，布线图形的突起部4完全被啮入凸点电极6中。因此，完成布线图形2的突起部4与凸点电极6之间的连接。
此后，如图7(a)和7(b)所示，对脉冲加热机100的通电停止，脉冲加热机100的温度被降至常温。然后，对半导体芯片3的加压停止。因此，得到图1和2所示的COF半导体器件10。
第2实施例
第2实施例的半导体器件制造方法是第1实施例的半导体器件制造方法的变形。在该制造方法中，半导体器件10(见图1和2)以与第1实施例的制造方法中大致相同的方式制造，只是改变了半导体芯片的加压和加热工序而已。因此，对于将半导体芯片3定位并安装在树脂7上的工序及其先前的工序(见图3(a)至5(a)和图3(b)至5(b))不作说明，而仅参照图8(a)、8(b)、9(a)和9(b)说明半导体芯片3的加压和加热工序。
在第2实施例中，如图8(a)和8(b)所示，在约为250×10-4gf/μm2的压力下将半导体芯片3压到膜基板1上并使用恒定地保持在加热状态的恒定加热机200在约为230℃至约为250℃下加热约1秒至约5秒。
此后，如图9(a)和9(b)所示，对恒定加热机200的加压停止。因此，得到图1和2所示的COF半导体器件10。在第2实施例中，加压和加热同时进行，不必等待半导体芯片3冷却即可停止加压。因此，比起第1实施例的制造方法，生产率得到改善。
第3实施例
参照图10说明本发明第3实施例的COF半导体器件的结构。图10是第3实施例的COF半导体器件的放大局部图。
第3实施例的COF半导体器件实质上具有与第1或第2实施例的半导体器件10相同的结构(见图1和2)，只是突起部4的金属材料与凸点电极6的合金的合金层38存在于布线图形2的突起部4与凸点电极6之间的连接界面内，如图10所示。因此，连接可靠性进一步得到改善。
第3实施例的半导体器件制造方法实质上与第1实施例的制造方法相同，只是改变了半导体芯片的加压和加热工序而已。
因此，对于将半导体芯片3定位并安装在树脂7上的工序及其先前的工序(见图3(a)至5(a)和图3(b)至5(b))不作说明，而仅参照图11(a)至13(a)和11(b)至13(b)说明半导体芯片3的加压和加热工序。
在第3实施例中，如图11(a)和11(b)所示，在约为250×10-4gf/μm2的压力下将半导体芯片3压到膜基板1上并使用脉冲加热机100在约为210℃下加热约1秒至约5秒，从而布线2的突起部4分别与凸点电极6连接，树脂7被固化。
接着，如图12(a)和12(b)所示，脉冲加热机100的加热温度被增加至例如约为300℃，从而扩散层或合金层38在突起部4与凸点电极6之间的连接界面上形成。
此后，如图13(a)和13(b)所示，脉冲加热机100的加压停止。因此，得到第3实施例的COF半导体器件。
分别被设定在例如210℃和300℃的两种类型的恒定加热机200可以用来替代脉冲加热机100以在与使用脉冲加热机100的上述情形中相同的方式进行两步加热。在该情形中，加压和加热同时进行。因此，得到具有上述结构的COF半导体器件。
第4实施例
参照图14和15说明本发明第4实施例的COF半导体器件的结构。图14是示意性地示出第4实施例的COF半导体器件的结构的图。图15是沿图14中的B-B线所取的COF半导体器件的剖面图。
如图14和15所示，第4实施例的COF半导体器件40实质上具有与第1或第2实施例的半导体器件10相同的结构(见图1和2)，只是配置在半导体芯片3与膜基板1之间的树脂部47包含散布在其中的导电粒子49而已。某些导电粒子49存在于布线图形2的突起部4与凸点电极6之间的连接界面内，从而连接可靠性进一步得到改善。
第4实施例的半导体器件40的制造方法实质上与第1或第2实施例的制造方法相同，只是采用了包含导电粒子49的树脂47(环氧树脂、硅酮树脂、丙烯酸树脂等)而已。
按照本发明，布线图形包括各自具有朝向半导体芯片的电极的逐渐变细的剖面形状的突起部。因此，在半导体器件制造工艺中，当半导体芯片被压到膜基板上并加热时，存在于突起部与电极之间的这部分树脂被突起部的渐细的末端部挤出，突起部分别凸入电极中。因此，布线图形的突起部与电极之间的电连接能够有效地进行。

Claims (12)

1.一种半导体器件，包括：
具有配置在其表面上的布线图形的膜基板；
安装在膜基板上并具有配置在其表面上的电极的半导体芯片；以及
配置在膜基板与半导体芯片之间的绝缘树脂部，该树脂部通过将绝缘树脂涂敷在膜基板和半导体芯片的至少一方上并在将半导体芯片安装在膜基板上时在膜基板与半导体芯片之间限定的空间充填树脂而形成，
其中，布线图形有一突起部，其剖面形状为朝向半导体芯片的电极而逐渐变细并凸入电极中，从而实现与电极的电连接。
2.如权利要求1所述的半导体器件，
其中，突起部具有梯形剖面形状，其末端部的宽度不大于电极的最大宽度的一半。
3.如权利要求1所述的半导体器件，
其中，突起部凸入电极中的平均深度不小于电极高度的10％。
4.如权利要求1所述的半导体器件，
其中，突起部和电极彼此热压键合。
5.一种如权利要求1所述的半导体器件的制造方法，该方法包括下述工序：
将绝缘树脂涂敷在膜基板上，用树脂覆盖配置在膜基板上的布线图形的突起部；
将半导体芯片安装在所涂敷的树脂上，半导体芯片的电极与突起部相向；
在规定的压力下将半导体芯片压到膜基板上，在规定的温度下将半导体芯片加热，从而突起部挤出存在于电极与突起部之间的一部分树脂并凸入电极中以与该电极连接，同时使树脂固化。
6.如权利要求5所述的半导体器件制造方法，
其中，电极和布线图形分别由金和铜构成；以及
在半导体芯片加压和加热工序中，对半导体芯片施加不低于250×10-4gf/μm2的压力以使突起部凸入电极中。
7.如权利要求5所述的半导体器件制造方法，
其中，绝缘树脂具有不高于210℃的固化温度；
在半导体芯片加压和加热工序中，半导体芯片在不低于210℃下被加热。
8.如权利要求5所述的半导体器件制造方法，
其中，电极由金构成，突起部由镀锡和镀金的至少一方的导体构成；以及
在半导体芯片加压和加热工序中，扩散层和合金层的至少一方通过在不低于300℃下对半导体芯片加热以将电极热压键合到突起部上去而在电极与突起部之间的连接界面内形成。
9.如权利要求5所述的半导体器件制造方法，
其中，绝缘树脂具有不高于210℃的固化温度；
电极由金构成，突起部由镀锡和镀金的至少一方的导体构成；以及
在半导体芯片加压和加热工序中，半导体芯片在围绕树脂的固化温度的温度下被热压以将电极与突起部连接在一起，同时使树脂固化，然后扩散层和合金层的至少一方通过在不低于300℃下对半导体芯片加热以将电极热压键合到突起部上去而在电极与突起部之间的连接界面内形成。
10.如权利要求5所述的半导体器件制造方法，
其中，在半导体芯片加压和加热工序中，半导体芯片的加压和加热同时开始，然后同时停止。
11.如权利要求5所述的半导体器件制造方法，
其中，在半导体芯片加压和加热工序中，在半导体芯片的加压开始后，半导体芯片的加热开始；在半导体芯片的加热停止后，半导体芯片的加压停止。
12.如权利要求5所述的半导体器件制造方法，
其中，绝缘树脂包含导电粒子。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101479846B (zh) * 2006-06-26 2011-11-23 皇家飞利浦电子股份有限公司 利用已形成的耦合件进行倒装互连
CN110418512A (zh) * 2019-08-02 2019-11-05 合肥奕斯伟材料技术有限公司 一种提升COF Film耐折性的制作方法
CN112868273A (zh) * 2018-10-16 2021-05-28 株式会社富士 电路形成方法

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281466B1 (en) * 1999-06-28 2001-08-28 Newcor, Inc. Projection welding of an aluminum sheet
US7235886B1 (en) 2001-12-21 2007-06-26 Intel Corporation Chip-join process to reduce elongation mismatch between the adherents and semiconductor package made thereby
US20030116860A1 (en) * 2001-12-21 2003-06-26 Biju Chandran Semiconductor package with low resistance package-to-die interconnect scheme for reduced die stresses
JP2005019815A (ja) * 2003-06-27 2005-01-20 Seiko Epson Corp 半導体装置およびその製造方法、回路基板ならびに電子機器
JP2005195690A (ja) * 2003-12-26 2005-07-21 Toshiba Corp 金属含有樹脂粒子、樹脂粒子、及び電子回路の製造方法
JP3833669B2 (ja) 2004-04-08 2006-10-18 シャープ株式会社 半導体装置および半導体装置の製造方法
US6977213B1 (en) * 2004-08-27 2005-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. IC chip solder bump structure and method of manufacturing same
JP2006294665A (ja) * 2005-04-06 2006-10-26 Sharp Corp 半導体装置及びその製造方法
US7687400B2 (en) 2005-06-14 2010-03-30 John Trezza Side stacking apparatus and method
US7786592B2 (en) * 2005-06-14 2010-08-31 John Trezza Chip capacitive coupling
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US7838997B2 (en) 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US7946331B2 (en) 2005-06-14 2011-05-24 Cufer Asset Ltd. L.L.C. Pin-type chip tooling
US7215032B2 (en) 2005-06-14 2007-05-08 Cubic Wafer, Inc. Triaxial through-chip connection
JP2007150089A (ja) * 2005-11-29 2007-06-14 Matsushita Electric Ind Co Ltd 配線基板及びその製造方法ならびに半導体装置
US7534715B2 (en) * 2005-12-29 2009-05-19 Intel Corporation Methods including fluxless chip attach processes
JP4316627B2 (ja) * 2007-03-07 2009-08-19 三井金属鉱業株式会社 フレキシブル配線基材並びに半導体装置及びその製造方法
EP1973158B1 (de) 2007-03-23 2016-03-16 Delphi International Operations Luxembourg S.à r.l. Elektronisches Bauteil
JP5353153B2 (ja) * 2007-11-09 2013-11-27 パナソニック株式会社 実装構造体
JP2010034423A (ja) * 2008-07-30 2010-02-12 Fujitsu Ltd 加圧加熱装置及び方法
US8011947B2 (en) * 2009-08-12 2011-09-06 Giga-Byte Technology Co., Ltd. HDMI assembly and HDMI port for the same
US20110169158A1 (en) * 2010-01-14 2011-07-14 Qualcomm Incorporated Solder Pillars in Flip Chip Assembly
TWI562312B (en) * 2014-03-24 2016-12-11 Chipmos Technologies Inc Chip-on-film package structure
JP6628031B2 (ja) * 2015-11-04 2020-01-08 ローム株式会社 電子部品
US10586716B2 (en) * 2017-06-09 2020-03-10 Advanced Semiconductor Engineering, Inc. Semiconductor device package
JP6864875B2 (ja) * 2019-08-30 2021-04-28 日亜化学工業株式会社 発光モジュール及びその製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6468504A (en) 1987-09-03 1989-03-14 Susumu Suzuki Production of working glove
JPH0713934B2 (ja) 1988-07-29 1995-02-15 株式会社村田製作所 コンデンサブロック
JP2669541B2 (ja) 1988-08-31 1997-10-29 株式会社日立製作所 検体検査装置
JPH0797597B2 (ja) * 1989-06-02 1995-10-18 松下電器産業株式会社 半導体装置
JP3610999B2 (ja) * 1996-06-07 2005-01-19 松下電器産業株式会社 半導体素子の実装方法
US6204564B1 (en) * 1997-11-21 2001-03-20 Rohm Co., Ltd. Semiconductor device and method for making the same
KR19990069950A (ko) * 1998-02-16 1999-09-06 윤종용 플립칩본딩구조 및 이를 이용한 솔더범프의 제조방법
JP3570271B2 (ja) 1999-02-22 2004-09-29 オムロン株式会社 半導体センサ及びその製造方法
JP3494940B2 (ja) 1999-12-20 2004-02-09 シャープ株式会社 テープキャリア型半導体装置、その製造方法及びそれを用いた液晶モジュール
JP3732378B2 (ja) * 2000-03-03 2006-01-05 新光電気工業株式会社 半導体装置の製造方法
KR100791575B1 (ko) * 2001-12-26 2008-01-03 삼성전자주식회사 테이프캐리어형 반도체 장치

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101479846B (zh) * 2006-06-26 2011-11-23 皇家飞利浦电子股份有限公司 利用已形成的耦合件进行倒装互连
CN112868273A (zh) * 2018-10-16 2021-05-28 株式会社富士 电路形成方法
CN112868273B (zh) * 2018-10-16 2023-08-29 株式会社富士 电路形成方法
CN110418512A (zh) * 2019-08-02 2019-11-05 合肥奕斯伟材料技术有限公司 一种提升COF Film耐折性的制作方法

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