CN1674219A - 半导体器件和用于半导体器件的多层基板 - Google Patents

半导体器件和用于半导体器件的多层基板 Download PDF

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Publication number
CN1674219A
CN1674219A CNA2005100563661A CN200510056366A CN1674219A CN 1674219 A CN1674219 A CN 1674219A CN A2005100563661 A CNA2005100563661 A CN A2005100563661A CN 200510056366 A CN200510056366 A CN 200510056366A CN 1674219 A CN1674219 A CN 1674219A
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mentioned
semiconductor element
coefficient
base plate
multilager base
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CN100358103C (zh
Inventor
田中直敬
河野贤哉
永井朗
田崎耕司
安田雅昭
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Showa Denko Materials Co ltd
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Hitachi Chemical Co Ltd
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Abstract

本发明实现一种提高了凸点电极和基板电极的连接可靠性的半导体器件。将用于电连接金属凸点(2)和布线图形(4)、密封LSI芯片(1)的LSI电路面的粘接材料(3)的热固化后的弹性系数设为Ea，将承载基板(8)表层的绝缘材料(5)的热固化后的弹性系数设为Eb，并且在具有芯层的多层基板的情况下将其芯材料(6)的弹性系数设为Ec时，在常温及粘接材料(3)的热压接合温度下，用满足如下的关系式的材料体系来构成半导体器件。即，至少Ea＜Eb＜Ec，优选1/3Eb＜Ea＜Eb＜3Ea(＜Ec)。按这样的关系来设定弹性系数，由于不论压接载重的大小及其批量生产时的偏差如何都能够实现稳定连接的状态，因此，就能够确保低成本、高合格率。

Description

半导体器件和用于半导体器件的多层基板
技术领域
本发明涉及一种半导体器件，特别涉及一种用于确保半导体元件上的微细电极与基板连接的技术。
背景技术
在半导体器件的安装领域中，正关注一种倒装芯片安装技术，其涉及半导体元件与基板的连接，作为与器件的多管脚化和高密度化相对应的连接方式，不是利用现有的引线键合的回路连接、而是通过在半导体芯片上的电极部分形成的凸点电极直接与布线基板上的电极连接。
利用引线键合，就必须在半导体器件中承载的半导体芯片周围确保用于连接的电极焊盘区域，且管脚越多该区域越大。
另一方面，根据倒装芯片安装技术，由于能在承载芯片区域内完成连接，因而不仅能使安装面积小型化，而且还能缩短连接布线的长度。
并且，由于电路面成为承载基板侧，因此可以在其上层层叠相同尺寸或比其大的其它半导体芯片，适用于近来倍受关注的三维安装结构时也有利。
作为倒装芯片安装方式，虽然在芯片电极部分设置焊料凸点，利用焊料连接来实现电导通的方式是主流，但近来作为与狭窄间距化相对应的方式，在芯片电极部分设置金凸点并利用金凸点连接而实现电导通的方式正在增多。
在利用上述金凸点的连接方法中，相对于金/金的金属接合和在金凸点/基板电极间涂敷焊料膏来实现金/焊料连接的所谓的冶金学的接合，有利用金凸点和基板电极间的接触来实现电导通的非冶金学的接合方式。
冶金学接合方式在接合部的可靠性这一点上通常有优点，但由于具有焊盘连接工序，因此就具有成为高温加工的缺点。
另一方面，由于非冶金学接合方式除了能够以低温加工实现连接以外，还能够实现简单的低成本加工，所以认为，在实现未来的狭窄间距连接方面是一种有效的方式。
但是，非冶金学接合方式虽然存在上述优点，但由于是接触导通，所以存在若设计和材料的选定不合适连接可靠性就不稳定的缺点，现阶段不适用于通用的产品。
例如，在专利文献1及专利文献2中公开了与提高非冶金学接合方式中的连接可靠性相关的发明。这些专利文献1及2中，公开了为了均一地实现在半导体芯片上设置的凸点电极和在承载基板上形成的电极的接触状态，使基板表层绝缘层的弹性系数恰当的连接结构。
专利文献1  特开平9-199468号公报
专利文献2  特开平10-245615号公报
可是，作为半导体器件，基于超过现在的多功能化、小型化等需求，要求电极之间的间距进一步狭窄。
因此，在非冶金学接合方式中，为了实现上述狭窄间距化，存在如何使凸点电极和基板电极的接触状态稳定化的这样的问题。
由于伴随未来间距狭窄化的凸点电极的微细化，例如热压接合时密封凸点周围的粘接材料(非导电或各向异性导电树脂)的线膨胀系数大时，由于粘接材料的热收缩而使凸点电极的塑性变形加速，再次加热时就会产生接触面容易分离·断线的情况。
与此相反，在粘接材料的线膨胀系数小的情况下，若承载基板表层的刚性(弹性系数)下降，就不能得到稳定的规定接触挤压，也会产生接触面容易分离·断线的情况。
因此，如上述专利文献1及2中所述的技术，只是使承载基板表层的绝缘材料的刚性(弹性系数)恰当化，难以确保与狭窄间距连接相对应的非冶金学的倒装芯片连接的高可靠性。
并且，在现有技术中虽不是太大的问题，但对于未来间距的狭窄化，承载凸点电极和基板电极时的位置偏移就会成为问题。即，采用狭窄间距化的情况，例如，凸点承载位置相对于基板电极仅偏移10～15μm，接触导通区域就会减少一半左右。此倾向随着狭窄间距化的推进就更加显著。
因此，考虑半导体器件的实际批量生产过程时，即使允许凸点电极位置的上述程度的偏移，也必须不影响连接合格率(组装合格率)。
并且，为了实现在狭窄间距电极间的连接，必定需要将基板电极周围的布线图形微细化，因此对应于产生的热应力等，就会显著降低基板布线强度。
因此，考虑半导体器件中的安装结构整体的可靠性的情况下，需要不仅能够确保凸点电极接触导通部的连接可靠性，而且还能够确保对基板上的微细布线的连接可靠性的基板结构。
发明内容
本发明的目的在于实现一种提高凸点电极和基板电极的连接可靠性的半导体器件及用于半导体器件的多层基板。
为了实现上述目的，本发明按如下方式构成。
(1)本发明的半导体器件，包括：形成有金属性凸点电极的半导体元件；具有与该半导体元件的凸点电极配置位置相对应地配置的布线层及多个绝缘材料层的多层基板；用于在该多层基板的布线层和金属凸点接触的状态下使上述多层基板和上述半导体元件连接的、位于上述半导体元件和上述多层基板之间的热固化性粘接材料。
在本发明的半导体器件中，将上述热固化性粘接材料的热固化后的弹性系数设为Ea、并将上述多层基板的半导体元件侧绝缘材料层的热固化后的弹性系数设为Eb时，在常温环境或金属凸点和上述布线层的热压接合温度下，满足1/3Eb＜Ea＜Eb＜3Ea的关系。
(2)优选在上述(1)中，将隔着上述半导体元件侧绝缘材料层与半导体元件相对的芯材料层的弹性系数设为Ec时，在常温环境或上述金属凸点电极和布线层的热压接合温度下，满足3Ea＜Ec的关系。
(3)本发明的半导体器件，将热固化性粘接材料的热固化后的线膨胀系数设为αa、并将多层基板的半导体元件侧绝缘材料层的热固化后的线膨胀系数设为αb时，在常温环境或金属凸点和布线层的热压接合温度下，满足1/3αa＜αb＜αa＜3 αb的关系。
(4)优选在上述(3)中，将隔着上述半导体元件侧绝缘材料层与半导体元件相对的芯材料层的线膨胀系数设为αc，在常温环境或上述金属凸点电极和布线层的热压接合温度下，满足αc＜1/3αa的关系。
(5)在本发明的半导体器件中，将热固化性粘接材料的热固化后的弹性系数设为Ea、并将多层基板的半导体元件侧绝缘材料层的热固化后的弹性系数设为Eb、将隔着半导体元件侧绝缘材料层与半导体元件相对的芯材料层的弹性系数设为Ec时，在常温环境或金属凸点和布线层的热压接合温度下，满足Ea＜Eb＜Ec的关系。
(6)在本发明的半导体器件中，将热固化性粘接材料的热固化后的线膨胀系数设为αa、并将多层基板的半导体元件侧绝缘材料层的热固化后的线膨胀系数设为αb、将隔着半导体元件侧绝缘材料层与半导体元件相对的芯材料层的线膨胀系数设为αc时，在常温环境或上述金属凸点电极和布线层的热压接合温度下，满足αc＜αb＜αa的关系。
(7)优选上述在(1)、(2)或(5)中，上述弹性系数Ea、Eb、Ec将利用粘弹性测量法测量出的储存弹性系数或经过由毫微压痕(nanoindenter)的按压试验中得到的表层弹性系数作为基准。
(8)此外，优选在上述(3)、(4)或(6)中，上述线膨胀系数αa、αb、αc将利用热膨胀测量法测量出的线膨胀系数作为基准。
(9)此外，优选在上述(1)到(7)中，半导体元件的热压接合温度处于160℃～200℃的范围内。
(10)此外，优选在上述(1)到(7)中，上述粘接材料及绝缘材料层含有填料(filler)。
(11)此外，优选在上述(1)到(7)中，上述粘接材料含有导电粒子。
(12)本发明的用于半导体器件的多层基板，包括：与半导体元件的凸点电极配置位置相对应地配置的布线层；多个绝缘材料层；用于在上述布线层和半导体元件的金属凸点接触的状态下与半导体元件连接的、位于在上述半导体元件侧配置的绝缘材料层上的热固化性粘接材料。
在上述用于半导体器件的多层基板中，将上述热固化性粘接材料的热固化后的弹性系数设为Ea、并将半导体元件侧绝缘材料层的热固化后的弹性系数设为Eb时，在常温环境或金属凸点电极和布线层的热压接合温度下，满足1/3Eb＜Ea＜Eb＜3Ea的关系。
(13)优选在上述(12)中，将隔着上述半导体元件侧绝缘材料层与半导体元件相对的芯材料层的弹性系数设为Ec时，在常温环境或金属凸点电极和布线层的热压接合温度下，满足3Ea＜Ec的关系。
根据本发明，就能够实现提高凸点电极和基板电极的连接可靠性的半导体器件及用于半导体器件的多层基板。
因此，能够实现半导体器件制造组装时的高合格率化，同时在温度循环试验等的加速试验中与现有技术相比，能够实现高可靠性。
并且，针对未来电极间的间距狭窄化，相对于假设发生的凸点/焊盘间的位置偏移，也能够维持稳定的连接状态。
由此，即使相对于伴随狭窄间距化的基板布线的微细化，由于大幅度地减少了对布线的负载，因此也能够实现包含基板的模块结构整体的高可靠性。
附图说明
图1是本发明的第一实施方式的半导体器件的简要截面图。
图2是本发明的第二实施方式的半导体器件的简要截面图。
图3是本发明的第三实施方式的半导体器件的简要截面图。
图4是表示本发明中的半导体器件的制造过程图。
图5是表示基板表层绝缘材料的弹性系数对凸点连接状态影响的机理。
图6是表示压接时在凸点/焊盘间产生位置偏移时的凸点/焊盘间接触挤压状态。
图7是表示在每个凸点区域检测的初始连接电阻的结果的曲线图。
图8是表示在温度循环试验中的凸点连接部分的整体的连接电阻的变化图。
图9是表示利用根据有限要素方法的结构解析而计算出的在引出布线部中产生的等效塑性变形的结果的曲线图。
具体实施方式
下面，参照附图来详细说明本发明的实施方式。
图1是本发明的第一实施方式的半导体器件的简要截面图。
在图1中，在LSI芯片1的电极焊盘上形成有金属凸点2。虽然没有限制金属凸点2的材料种类，但其基本上可以由金合金构成，并利用引线键合加工形成柱状凸点、或利用电镀加工形成镀层凸点来形成金属凸点2。
在承载LSI芯片1的承载基板8上，形成在与LSI芯片1上形成的金属凸点2相对应的位置上配置的布线图形(表面镀金)4。此布线图形4构成布线层。在实施金属凸点2和布线图形4之间的位置对准之后，在承载基板8上，通过粘接材料3用高温加压焊接LSI芯片1，一并进行相互的电连接(基本上通过金属凸点2和布线图形4之间接触挤压来进行接触导通)与LSI电路面的密封。
在粘接材料3中，一般可以使用以热固化性的环氧树脂为主的非导电性粘接薄片(NCF：Non conductive film)或液状膏(NCP：Nonconductive paste)、或混有导电粒子的各向异性导电薄片(ACF：Anisotropic conductive film)等。
承载基板8包括芯材料料6和一般被称为装配层的绝缘材料层5，各层间通过Cu布线及Cu柱进行电连接。作为以狭窄间距实现布线形成的方法，一般利用半添加方法的布线形成工艺，当绝缘材料的刚性高时，由于未充分进行表面粗化，就会存在Cu镀层的粘接性降低的情况。在此情况下，提出了一种对Cu箔一侧进行机械的表面粗化后粘贴绝缘材料的方法，如利用此方法、即使绝缘材料的刚性高、也不会产生Cu镀层的粘接性的问题。
在承载基板8的背面侧(图1的下方侧面)，形成用于承载焊料球的区域(land)布线，通过助焊剂，将尺寸适合于焊料凸点7的承载间距的焊料球转印到各区域表面，经过回流焊工序形成焊料凸点7。但是，不一定必须形成焊料凸点7，也可以是没有焊料凸点7状态的半导体器件。
在此，将用于电连接金属凸点2和布线图形4并密封LSI芯片1的LSI电路面的粘接材料3的热固化后的弹性系数设为Ea、将承载基板8表层的绝缘材料5的热固化后的弹性系数设为Eb、并且在具有芯层的多层基板的情况下将其芯材料6的弹性系数设为Ec时，在本发明的第一实施方式中，在常温及粘接材料3的热压接合温度下，构成满足下面关系式(1)中所示关系的材料体系。
至少Ea＜Eb＜Ec，优选1/3Eb＜Ea＜Eb＜3Ea(＜Ec＝
                                     ---(1)
或者，在本发明的第一实施方式中，将粘接材料3的热固化后的线膨胀系数设为αa、将绝缘材料层5的线膨胀系数设为αb、并且在具有芯层的多层基板的情况下将其芯材料6的膨胀系数设为αc时，在常温及粘接材料3的热压接合温度下，构成满足下面关系式(2)中所示关系的材料体系。
至少，αa＞αb＞αc、优选(αc＜)1/3αa＜αb＜αa＜3αb  ---(2)
但是，上述关系式(1)的弹性系数，将利用对象材料的DMA法(粘弹性测量法)的储存弹性率测量或经过由毫微压痕的按压试验中得到的弹性系数作为基准，就上述关系式(2)中的线膨胀系数而言，将从利用对象材料的TMA法(热膨胀测量法)的测量结果中得到的线膨胀系数作为基准。
具体是，半导体芯片1的热压接合温度为200℃的情况下，例如芯材料6的弹性系数为15GPa，线膨胀系数为10ppm(面方向(XY方向))左右，表层绝缘材料5的弹性系数为1GPa、线膨胀系数为50ppm(面方向(XY方向))左右，粘接材料3的弹性系数为0.5GPa(表层绝缘材料5的1/3或以上)、线膨胀系数为100ppm(表层绝缘材料的3倍或以下)左右。
在常温环境中，例如，芯材料6的弹性系数为20GPa、线膨胀系数为12ppm(XY方向)左右，表层绝缘材料5的弹性系数为10GPa、线膨胀系数为20ppm(XY方向)左右，粘接材料3的弹性系数为5GPa(表层绝缘材料5的1/3或以上)、线膨胀系数为40ppm(表层绝缘材料的3倍或以下)左右。
再有，在关系式(1)中，使3Ea(＜Ec)是因为，如果芯材料6的弹性系数Ec比3Ea大，芯材料6就容易变形，热压接合时绝缘材料5(装配层)也容易变形。
如图1中所示，在承载基板8的芯材料6的两面形成的绝缘材料层5不一定是一层结构，根据产品的形态，可形成两层～四层的绝缘材料层，在此，根据连接金属凸点2的布线图形4的正下方的绝缘材料层特性，来规定作为对象的绝缘材料的弹性系数及线膨胀系数。
说明如上所述构成的本发明的第一实施方式的原理。
图5是在粘接材料3(在此假设为非导电膜)的弹性系数Ea在常温下为5～6GPa、在粘接材料3的热压接合温度下为0.5～0.6GPa左右(现在通常普遍使用的材料)的情况下、用其与基板表层绝缘材料5的弹性系数的关系来表示对凸点连接状态影响的机理的示意图。并且，图5(A)示出了低载重的情况，图5(B)示出了高载重的情况。
此外，若将基板表层绝缘材料5的弹性系数设为Eb，则在Ea＞Eb时，即当粘接材料3的弹性系数比绝缘材料5的弹性系数大，最左侧的图示出了这种情况。通过通常广泛使用的半添加工艺中的与使用绝缘材料的装配基板的组合就相当于在最左侧的图中所示的情况(不同于本发明)。
在半添加工艺中，在基板8的芯材料6上层叠绝缘材料5之后，在其表层形成非电解镀的Cu布线层4。为了确保绝缘材料5和Cu镀层4的粘接性，通常可实施所谓的表面粗化的化学处理。
因此，当绝缘材料5的弹性系数大(硬度高)时，由于难于进行表面粗化处理，所以在半添加工艺中通常广泛使用的绝缘材料5的弹性系数在常温下是2～3GPa的低弹性，小于粘接材料3在常温下的弹性系数(5～6GPa)(粘接材料3的热压接合温度也相同)。
如图5(A)中所示，此粘接材料3和基板绝缘材料5的材料体系中，当压接载重低时，就不能得到充分的凸点/焊盘间的接触挤压，就会导致接触状态不稳定。相反，如图5(B)中所示，当压接载重增大时，就会使基板侧Cu焊盘部分4的变形过大，就会提高发生如图所示的布线损害的可能性。
因此，在本材料体系的关系下，为了实现稳定的连接状态，就必须进行将压接载重调准(tuning)到合适范围等的工艺管理，就会大大地影响批量生产时的制造成本和合格率。
另一方面，图5的最右侧的图是不同于本发明、且假设与用含有常规广泛使用的玻璃布薄片的预浸材料片(prepreg)来制造的高刚性基板(一般不作为针对狭窄间距的装配基板)的组合的情况。
在这种常规预浸材料片的情况，常温下的弹性系数为15～20GPa左右，属于比粘接材料3的弹性系数大3倍或3倍以上时的情况(Eb＞3Ea)。在此情况下，不论压接载重的大小如何，都容易稳定地保持凸点/焊盘间的接触挤压。但是，由于与凸点2周围的粘接材料的刚性相比、基板表层的刚性非常高，所以在压接加工时和组装后的温度循环试验等中，凸点2的塑性变形就过大。特别是进行升温时，就会发生凸点/焊盘间的剥离，断线可能性就会变高。
并且，由于常规预浸材料的情况下的基板焊盘表面的变形量小，特别是当压接载重小时，就难于吸收焊盘间的初始高度偏差和凸点2的初始高度偏差，就会使连接状态整体地变得不稳定。
图5中央所示出的是使用根据本发明的材料体系的情况下的凸点连接状态。示出了在本发明的情况下，与弹性系数的一般关系即Ea＞Eb相反，以满足Ea＜Eb＜3Ea关系的材料体系接合的状态。
由于本发明的情况下的基板表层5的刚性比凸点2周围的粘接材料3大，所以，即使压接载重小，也能够稳定地保持凸点/焊盘间的接触挤压。
相反，即使压接载重高的情况，基板焊盘表面也会以恰当的程度变形，不仅可抑制凸点2的过大的塑性变形，而且还能够在不引起布线损害的范围内维持适度的弹性反力，由此就能够维持稳定的接合状态。
因此，在本发明的情况下，由于不论压接载重的大小和其批量生产时的偏差如何，都能实现稳定的连接状态，所以能够确保低成本、高的合格率。
图6是假设压接时在凸点/焊盘间发生位置偏移的情况下、利用根据有限要素法的结构解析计算出的凸点/焊盘间的接触挤压的结果。
图6(A)表示相对于预先规定的粘接材料3的弹性系数(Ea＝0.5～0.6GPa/200℃)、基板表层的绝缘材料5的弹性系数小的情况(Eb＝0.1GPa/200℃)的解析结果。此外，图6(B)表示相当于本发明的材料体系的弹性系数大的情况(Eb＝1GPa/200℃)的解析结果。
此外，图6(C)示出了将绝缘材料5的弹性系数为Eb＝0.1GPa/200℃和Eb＝1GPa/200℃时的位置偏移和接触挤压的关系进行比较的曲线图。
可是，今后，倒装芯片连接技术将要求应对50μm或50μm以下的非常狭窄间距的连接，当考虑半导体器件批量生产时的对准偏差时，就必须实现凸点/焊盘间的位置偏移可允许到某一程度的连接结构。
但是，在现在常规使用的与装配基板的组合(Ea＞Eb)中，由于基板表层5为低刚性，所以相对于凸点2的位置偏移就导致了基板侧焊盘表面倾斜，因此即使在凸点/焊盘相互重叠的区域中，也几乎不能获得接触挤压(仅凸点边缘部分)。
另一方面，在满足本发明的Ea＜Eb(并且＜3Ea)关系的材料体系(Eb＝1GPa/200℃)中，即使相对于凸点的位置偏移，就凸点/焊盘相互重叠的区域而言，也能够稳定地获得充分的接触挤压。
如上述所述，根据本发明的材料体系，即使针对在狭窄间距连接中可能会出现的凸点2的大的位置偏移(大约为凸点直径的一半)，也能够实现稳定的连接状态。
图7是表示实际使用试作的TEG样品、测量每个凸点区域(1～21ch)的初始(接触)连接电阻的结果。再有，TEG样品的芯片/基板间通过凸点连接部分以数字图形构成。为了确认凸点位置偏移的影响，在此试作样品中，虽然各个凸点位置的偏移程度不同，但作为装置设定，故意引入凸点直径一半左右的位置偏移来试作此样品。
在图7中，在与现在常规使用的装配基板的组合(Ea＞Eb＝0.1GPa/200℃)中，初始的连接电阻增高，而各测量区域的布线长度相等，所以认为这是由接触导通部的接触电阻之差引起的。
因此，换言之，图7中所示的曲线图是实际验证图6中所示的凸点位置偏移时的影响机理的测量结果。
另一方面，在图7中，以满足根据本发明的材料体系关系的材料结构试作的两种TEG样品的情况(Ea＜Eb＝1GPa/200℃、1.3GPa/200℃＜3Ea)中，即使引入凸点2的偏移也都能够获得相同水平的连接电阻值，并能够达到稳定水平。
再有，在图7中，每个测量区域的连接电阻值不同不是因为凸点连接部分的接触电阻没有改变而是由于各测量区域的布线长度不同。
图8是表示将上述TGE样品投入温度循环试验时的监测凸点连接部分整体电阻变化的结果图。图8(A)是现有的材料体系的情况，图8(B)是本发明的材料体系的情况。
如图8中所示，在满足根据本发明的材料体系的TGE样品的情况下，与现有的材料体系比较，不仅降低了初始的连接电阻，而且也减少了温度循环试验时的连接电阻变化，所以在宽的温度范围也能够实现稳定的连接。
此外，在本发明的材料***中，电的温度循环的寿命也是以-55/125℃的条件，循环1000个周期的寿命。
图9是表示基板8侧的连接焊盘用区域布线向周边方向引出的基板结构中、将形成有凸点2的半导体芯片1进行倒装芯片连接时，利用根据有限要素法的结构解析计算出的引出布线部产生的等效塑性变形(金属疲劳破坏的评价指标)的结果的曲线图。
图9所示的比较结果是假设应对无铅的回流焊条件、加热到260℃情况下所产生的变形值。此外，在图9表示现在常规使用的与装配基板的组合(Ea＞Eb＝0.1GPa/200℃)的情况和满足根据本发明的材料体系关系的材料结构(Ea＜Eb＝1GPa/200℃、(且＜3Ea))时的解析结果。
如图9所示，回流焊接加热时在基板布线所发生的等效塑性变形，在现在常规使用的装配基板的情况下(Ea＞Eb＝0.1GPa/200℃)变得非常大(超过1％)，由于今后将加速无铅化而导致加热温度上升，且布线的微细图形化也会进一步发展，从而变形量也将进一步增大。
另一方面，根据本发明的材料体系的情况(Ea＜Eb＝1GPa/200℃、(且＜3Ea))在相同加热条件下产生的变形量为0.1％或0.1％以下，表明对微细布线图形的载重变得非常小。
因此，应当理解，本发明相对于将来的回流加热温度的上升和布线的微细化，可实现能够确保高可靠性的模块结构。
如上所述，根据本发明的第一实施方式，由于粘接材料3的热固化后的弹性系数Ea、绝缘材料5的热固化后的弹性系数Eb、芯材料6的热固化后的弹性系数Ec，满足1/3Eb＜Ea＜Eb＜3Ea(＜Ec)的关系，所以能够实现提高凸点电极2和基板电极4的连接可靠性的半导体器件。
再有，可将多层基板8与LSI芯片分别制造销售，此后，与作为半导体器件的LSI芯片进行连接。在此多层基板8中，具有粘接材料3、绝缘材料5、布线图形4和芯材料6，假设粘接材料3的热固化后的弹性系数Ea、绝缘材料5的热固化后的弹性系数Eb、芯材料6的热固化后的弹性系数Ec，满足1/3Eb＜Ea＜Eb＜3Ea(＜Ec)的关系，就能够实现可用于半导体器件的多层基板，该多层基板可构成提高凸点电极2和基板电极4的连接可靠性的半导体器件。
图2是本发明的第二实施方式的半导体器件的简要截面图。此第二实施方式的基本结构与上述第一实施方式相同。但是，如图2中所示，在与第一实施方式相同的材料体系结构的一个承载基板8上承载多个LSI芯片1、1b。
作为LSI芯片1、1b的具体产品结构，也可是微处理器(微机)和存储器(DRAM)混载以及这些与快闪存储器的3芯片结构。此外，当将RF芯片与微机进行混载安装的情况下，也可以在其周边同时安装无源元件，进行单模块化。此外，将图形引擎等的发热量大的元件与存储器(DRAM)混载安装的情况下，在芯片上面粘接由铜或铝制造的散热板，就能够降低热电阻。
即使在此第二实施方式中，也能够获得与第一实施方式相同的效果。
图3是本发明的第三实施方式的半导体器件的简要截面图。
此第三实施方式是将多个半导体芯片1、1b以三维的形式进行层叠的例子。即，在第三实施方式中，下层的半导体芯片1承载在与第一实施方式相同的材料体系结构中的基板8上。并且，上层的半导体芯片1b通过粘接材料9固定在下层的半导体芯片1的上面。
由于利用倒装芯片连接下层半导体芯片1，故无论上层芯片1b比下层芯片1面积小还是大，都能够承载在下层的半导体芯片1上。此外，上层的芯片1b通过引线键合10与在承载基板8上形成的电极部分4电连接。
为了保护上层芯片1b的电路面，对整个芯片承载区域进行传递模塑，用树脂11密封。
在上述第三实施方式中，毫无疑问，下层半导体芯片1也能够获得与第一实施方式相同的效果，即使在上层半导体芯片1b的引线键合连接中，通过与第一实施方式相同的作用效果，也能够实现稳定的连接。
即，实现利用超声振动的引线键合时的金属接合的前提条件，是能够在接合时维持稳定的接触状态。
因此，已经表明，不仅是利用金属凸点的接触挤压的接触导通连接形态，即使是利用超声波振动的金属凸点的金属间接合的实施方式，只要利用满足第一实施方式中所示的关系式(1)的材料体系来构成，就能够获得相同的效果。
再有，在图示出的第三实施方式中，虽然示出了层叠两个半导体器件1、1b的两层芯片的情况下的例子，但是，也可在芯片1b的上层层叠3层、4层，利用引线键合10，与在承载基板8上形成的电极部分4电连接。
在图4中，示出了利用根据本发明的半导体器件的制造工序及现有技术的半导体器件的制造工序。
在图4中，在现有工艺中，在半导体芯片的电极上形成金属凸点，利用晶片的切割、将带有凸点的芯片分割成单个芯片。并且，在基板上的芯片承载位置上，实施薄片状粘接材料的粘贴或涂敷膏状粘接材料，在将芯片上电极的凸点位置和基板上的布线图形位置对准之后，进行预压接。最后，以达到粘接材料的固化温度进行加热，实施正式压接，结束连接加工。
在现有技术中的制造工艺中，在粘贴薄片状的粘接材料的加工和涂敷膏状粘接材料的过程中，由于对承载的产品芯片尺寸和连接间距等进行单独设定，故在应对定作的多品种少量生产中，就会存在导致TAT(产品交货期)的长期化。
将尺寸不同的多个半导体芯片同时承载在基板上的情况下，就可能进一步长期化。
相对于此，在本发明的制造过程1中，在晶片级的状态下，事先粘贴薄片状的粘接材料，在粘贴薄片状粘接材料的状态下，切割成带有凸点的单个芯片。此后，将带NCF的芯片进行单片化并实施常温预压接后，进行正式压接。
由此，不需要在基板的芯片承载位置上事先粘贴粘接薄片等过程，就能够仅以位置对准后的正式压接工艺来完成连接加工。
此制造工程1，在如第二实施方式那样同时承载、连接多个半导体芯片1、1b时特别有效。
此外，制造工艺2与现有技术相同，通过切割晶片对芯片进行单片化。此后，如现有技术那样，不在基板上粘贴NCF，将单独制造的多层基板与芯片进行常温预压接。然后进行正式压接。
如上述实施方式所述，在单独制造的多层基板中，粘接剂3、绝缘材料5、芯材料6的弹性系数Ea、Eb、Ec满足1/3Eb＜Ea＜Eb＜3Ea(＜Ec)的关系。
此制造工艺2，由于是由多层基板8和粘接材料3的材料体系构成的结构，所以在半导体器件的组装加工中，例如，基板厂家就以将粘接材料(图中NCF)预压接在事先制作出的多层基板的半导体元件承载面的状态作为出厂产品的形态。
由此，半导体厂家仅利用热压接合半导体元件的加工就能完成安装，从而能够实现制造过程的短周期及低成本化。
对于基板厂家，也可以作为将基板与粘接材料组合的多层基板体系来进行销售，其中也能够具有新的附加价值，所以对于两者都是有效的过程。
最近，正在关注高密度地安装现存的多个LSI、实现与***LSI同等水平的高性能化和小型模块化的***·内·封装技术。
本发明的倒装片技术，在加速上述***·内·封装技术的开发上占有重要的地位。
因此，应当认为，本发明是用于实现数字照相机和便携式电话等的高性能化和大幅度小型化的关键技术，且产业上的利用价值非常高。
再有，在上述的例子中，将粘接剂材料3的热效应后的弹性系数Ea和芯材料6的弹性系数Ec的关系设为3Ea＜Ec，这是为了避免热压接合时绝缘材料层5容易变形，此关系对于本发明的效果不是必要的。
此外，可以将本发明的半导体元件的热压接合温度设为160℃～200℃的范围。
此外，粘接材料3及绝缘材料5、6也可以含有填料。
并且，粘接材料3可以含有导电粒子。

Claims (13)

1、一种半导体器件，包括：形成有金属性凸点电极的半导体元件；具有与该半导体元件的凸点电极配置位置相对应地配置的布线层及多个绝缘材料层的多层基板；用于在该多层基板的布线层和金属凸点接触的状态下使上述多层基板和上述半导体元件连接的、位于上述半导体元件和上述多层基板之间的热固化性粘接材料，
其特征在于：将上述热固化性粘接材料的热固化后的弹性系数设为Ea、并将上述多层基板的半导体元件侧绝缘材料层的热固化后的弹性系数设为Eb时，在常温环境或金属凸点和上述布线层的热压接合温度下，满足1/3Eb＜Ea＜Eb＜3Ea的关系。
2、根据权利要求1所述的半导体器件，其特征在于：将隔着上述半导体元件侧绝缘材料层与上述半导体元件相对的芯材料料层的弹性系数设为Ec时，在常温环境或上述金属凸点电极和上述布线层的热压接合温度下，满足3Ea＜Ec的关系。
3、一种半导体器件，包括：形成有金属性凸点电极的半导体元件；具有与该半导体元件的凸点电极配置位置相对应地配置的布线层及多个绝缘材料层的多层基板；用于在该多层基板的布线层和金属凸点接触的状态下使上述多层基板和上述半导体元件连接的、位于上述半导体元件和上述多层基板之间的热固化性粘接材料，
其特征在于：将上述热固化性粘接材料的热固化后的线膨胀系数设为αa、并将上述多层基板的半导体元件侧绝缘材料层的热固化后的线膨胀系数设为αb时，在常温环境或金属凸点和上述布线层的热压接合温度下，满足1/3αa＜αb＜αa＜3αb的关系。
4、根据权利要求3所述的半导体器件，其特征在于：将隔着上述半导体元件侧绝缘材料层与上述半导体元件相对的芯材料料层的线膨胀系数设为αc时，在常温环境或上述金属凸点电极和上述布线层的热压接合温度下，满足αc＜1/3αa的关系。
5、一种半导体器件，包括：形成有金属性凸点电极的半导体元件；具有与该半导体元件的凸点电极配置位置相对应地配置的布线层及多个绝缘材料层的多层基板；用于在该多层基板的布线层和金属凸点接触的状态下使上述多层基板和上述半导体元件连接的、位于上述半导体元件和上述多层基板之间的热固化性粘接材料，
其特征在于：将上述热固化性粘接材料的热固化后的弹性系数设为Ea、并将上述多层基板的半导体元件侧绝缘材料层的热固化后的弹性系数设为Eb、将隔着上述半导体元件侧绝缘材料层与半导体元件相对的芯材料料层的弹性系数设为Ec时，在常温环境或金属凸点和上述布线层的热压接合温度下，满足Ea＜Eb＜Ec的关系。
6、一种半导体器件，包括：形成有金属性凸点电极的半导体元件；具有与该半导体元件的凸点电极配置位置相对应地配置的布线层及多个绝缘材料层的多层基板；用于在该多层基板的布线层和金属凸点接触的状态下使上述多层基板和上述半导体元件连接的、位于上述半导体元件和上述多层基板之间的热固化性粘接材料，
其特征在于：将上述热固化性粘接材料的热固化后的线膨胀系数设为αa、将上述多层基板的半导体元件侧绝缘材料层的热固化后的线膨胀系数设为αb、将隔着上述半导体元件侧绝缘材料层与半导体元件相对的芯材料料层的线膨胀系数设为αc时，在常温环境或上述金属凸点电极和上述布线层的热压接合温度下，满足αc＜αb＜αa的关系。
7、根据权利要求2所述的半导体器件，其特征在于：上述弹性系数Ea、Eb、Ec以利用粘弹性测量法测量出的储存弹性系数或经过利用毫微压痕的按压试验中得到的表层弹性系数作为基准。
8、根据权利要求4所述的半导体器件，其特征在于：上述线膨胀系数αa、αb、αc以利用热膨胀测量法测量出的线膨胀系数作为基准。
9、根据权利要求1所述的半导体器件，其特征在于：半导体元件的热压接合温度处于160℃～200℃的范围内。
10、根据权利要求1所述的半导体器件，其特征在于：上述粘接材料及绝缘材料层含有填料。
11、根据权利要求1所述的半导体器件，其特征在于：上述粘接材料含有导电粒子。
12、一种用于半导体器件的多层基板，包括：与半导体元件的凸点电极配置位置相对应地配置的布线层、多个绝缘材料层和热固化性粘接材料，所述热固化性粘接材料用于在上述布线层和半导体元件的金属凸点接触的状态下与上述半导体元件连接，并位于在上述半导体元件侧配置的绝缘材料层上，
其特征在于：将上述热固化性粘接材料的热固化后的弹性系数设为Ea、并将半导体元件侧绝缘材料层的热固化后的弹性系数设为Eb时，在常温环境或上述金属凸点电极和上述布线层的热压接合温度下，满足1/3Eb＜Ea＜Eb＜3Ea的关系。
13、根据权利要求12所述的用于半导体器件的多层基板，其特征在于：将隔着上述半导体元件侧绝缘材料层与上述半导体元件相对的芯材料料层的弹性系数设为Ec时，在常温环境或上述金属凸点电极和上述布线层的热压接合温度下，满足3Ea＜Ec的关系。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102194707A (zh) * 2010-03-01 2011-09-21 南茂科技股份有限公司 制造半导体结构的方法
CN108436604A (zh) * 2018-04-23 2018-08-24 宜特(上海)检测技术有限公司 应用于低介电材质覆晶芯片的防脱层研磨方法
CN105593986B (zh) * 2013-09-27 2018-10-19 瑞萨电子株式会社 半导体装置及其制造方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5338513B2 (ja) 2009-06-24 2013-11-13 富士通株式会社 パターン引き出し構造体及び半導体装置
US20140145328A1 (en) * 2009-07-13 2014-05-29 Georgia Tech Research Corporation Interconnect assemblies and methods of making and using same
WO2011008759A1 (en) * 2009-07-13 2011-01-20 Georgia Tech Research Corporation Interconnect assemblies and methods of making and using same
CN106449490B (zh) * 2016-12-07 2019-05-24 北京中电科电子装备有限公司 一种倒装芯片封装设备及控制方法
CN112889354A (zh) * 2018-10-17 2021-06-01 亮锐控股有限公司 电路组件

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199468A (ja) 1996-01-12 1997-07-31 Tokyo Electron Ltd 処理方法と装置
TW383435B (en) * 1996-11-01 2000-03-01 Hitachi Chemical Co Ltd Electronic device
JP3470857B2 (ja) 1997-03-05 2003-11-25 Ｊｆｅスチール株式会社 転炉型精錬容器における溶銑の脱燐精錬方法
US5919329A (en) * 1997-10-14 1999-07-06 Gore Enterprise Holdings, Inc. Method for assembling an integrated circuit chip package having at least one semiconductor device
JP2002050718A (ja) * 2000-08-04 2002-02-15 Hitachi Ltd 半導体装置
AU2001290314A1 (en) * 2000-09-29 2002-04-08 Hitachi Chemical Co. Ltd. Resin-sealed semiconductor device, and die bonding material and sealing materialfor use therein
JP3854054B2 (ja) * 2000-10-10 2006-12-06 株式会社東芝 半導体装置
JP2002270718A (ja) * 2001-03-07 2002-09-20 Seiko Epson Corp 配線基板及びその製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
JP4024563B2 (ja) * 2002-03-15 2007-12-19 株式会社日立製作所 半導体装置
JP2004253738A (ja) * 2003-02-21 2004-09-09 Toshiba Corp パッケージ基板及びフリップチップ型半導体装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102194707A (zh) * 2010-03-01 2011-09-21 南茂科技股份有限公司 制造半导体结构的方法
CN102194707B (zh) * 2010-03-01 2013-03-27 南茂科技股份有限公司 制造半导体结构的方法
CN105593986B (zh) * 2013-09-27 2018-10-19 瑞萨电子株式会社 半导体装置及其制造方法
CN108436604A (zh) * 2018-04-23 2018-08-24 宜特(上海)检测技术有限公司 应用于低介电材质覆晶芯片的防脱层研磨方法

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