CN1599045A - 具有横向漂移区掺杂剂分布的dmos晶体管的制造方法 - Google Patents
具有横向漂移区掺杂剂分布的dmos晶体管的制造方法 Download PDFInfo
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Abstract
本发明涉及一种在一半导体基体(10)中制造DMOS晶体管的方法,该半导体基体(10)具有一个沟槽形漂移区(29,30,33),该漂移区包括一个源极侧的侧面区域(29),一个沿横向延伸的底部区域(30)和一个漏极侧的侧面区域(33),本发明的特征是,通过至少一次从上部进行的掺杂剂的注入,在所述底部区域(30)内产生一个沿横向(36)分布的掺杂剂浓度梯度,所述注入仅涉及底部区域(30)的一个局部区域(40)。
Description
技术领域
本发明涉及一种在一块半导体基体上制造DMOS晶体管的方法,具有一个沟槽形漂移区,该漂移区包括一个源极侧的侧面区域,一个沿横向延伸的底部区域和一个漏极侧的侧面区域。
背景技术
这种方法已经公开在德国专利文献DE 10131705 A1中。
DMOS晶体管相对于普通MOS晶体管(金属氧化物半导体晶体管)的区别是,在晶体管的控制栅极的边缘和漏区之间设置一个漂移区,即在该区域内,载流子只能在一个施加在区域的相对的两端的电场作用下运动。在一个横向的DMOS晶体管(LDMOS晶体管)中,所述漂移区沿横向延伸,位于控制栅极的边缘和沿横向隔开的漏区之间。
DMOS晶体管主要应用于高压器件中,作用在晶体管的漏区和源区之间的电压,即所谓的漏极电压可大于100伏。
在美国专利文献US 5 539 238中公开的DMOS晶体管被制成深沟道结构,其中的掺杂区与沟槽(沟)的侧壁和底面相连,该区域就是晶体管的所谓漂移区。通过沿沟槽侧壁部分垂直地构成漂移区,可减小晶体管的长度。该方法的缺点是,施加在沟槽结构边缘上的反向电压(Sperrspannung)会在电位曲线上呈现不均匀性,从而导致反向电压的不希望的减小。此外,漂移区的总长度不是减小了,而是仅在垂直和横向的部分上被分开。换句话说:特征导通电阻Rsp=Rdson/面积,并没有减小,但减小恰恰是所希望的。根据该方法,无论是掺杂不足的侧壁和特征导通电阻Rsp,还是晶体管的面积消耗都有所增加,这是人们不希望看到的。
另外一种方法公开在欧洲专利文献EP 0 837 509 A1中。根据该文献,采用LOCOS氧化法在一个DMOS晶体管内制出自调节漂移区。其缺点是,对漂移区的掺杂是在氧化之前进行的,在氧化时扩散到氧化物中的掺杂剂的比例无法精确地确定。此外,氧化时产生的温度负荷会造成很宽的掺杂剂分布,使得掺杂剂的浓度具有很大的不精确性。另外,在氧化物的下面需要较大的硅层厚度,以通过所谓的“RESURF”效应提高反向电压,这是公知方法。缩写RESURF表示“缩小的表面场(reduced surface field)”。场的缩小的原因是漂移区载流子浓度的减小。从总体上看,由于工艺的分散性造成晶体管电参数的分散性的不希望的增加。
在DMOS晶体管领域中进行开发的首要目标是,进一步减小结构尺寸,这些结构在施加反向电压时具有较低的场强,以避免产生会导致器件内部击穿的载流子。
在DMOS晶体管的开发中,另一个目标是,实现更低的特征导通电阻Rsp。为此,应减少集成电路的面积消耗,而在集成电路中,DMOS晶体管占据了整个芯片面积的一大部分。
发明内容
本发明的任务是提供一种方法,使用该方法可在小面积上制造高反向电压DMOS晶体管。
该任务通过开始所述类型的方法被解决,通过至少一次从上部进行的掺杂剂的注入,在所述底部区域内产生一个沿横向分布的掺杂剂浓度梯度,所述注入仅涉及底部区域的一个局部区域。
迄今为止,在漂移区内沿横向上的均匀掺杂分布是通过注入和/或扩散产生的。通过这种方法得到的掺杂分布在垂直方向上可做到精确调节。但在横向上的浓度改变是无法通过这种方法实现的。为提高击穿电压,减小电阻,最好是让漂移区在漏极侧的掺杂率高于源极侧的掺杂率。同样有利的是,让漂移区中间的掺杂率高于边缘的掺杂率。这些效果已经通过本发明所述方法得到实现。
所述新方法的一个主要优点是,提供了在参数区内进一步优化的可能性,所述参数区主要是由特征导通电阻(Einschaltwiderstand)Rsp、击穿电压Vbreak和SOA(可靠操作区)表面的大小和形状确定的。这种进一步优化的可能性在于,在沟槽形结构的底部区域产生掺杂剂浓度的横向梯度。这样,便可在必要时在源极侧的侧壁相对漏极侧的侧壁产生不同的掺杂剂浓度,这两处与底部区域相连即定义出晶体管的漂移区,所得到的DMOS晶体管具有更小的总面积。另外,通过沿沟槽形结构底部产生的不同程度的掺杂剂浓度,使得利用和强化RESURF效应产生了最佳效果。
由于RESURF效应,使底部的掺杂剂分部中的梯度至少与源极侧侧壁的掺杂分布相结合,对截止状态以及导通状态下的击穿电压产生了重要影响,而漏极侧的掺杂剂分布主要是影响导通电阻Rdson,所以特别有利于在沟槽形结构底部的部位上使掺杂分布适应电气要求。
一个优选的方案是,所述底部区域在漏极侧的侧壁附近的掺杂率高于底部区域在源极侧的侧壁附近的掺杂率。
通过该方案可进一步降低导通电阻Rsp。
另一个选择方案是,所述底部区域中央区的掺杂率高于漏极侧的侧壁和/或源极侧的侧壁附近的边缘侧的部分区域,因为这样按趋势可实现提高反向电压。
另一个优选的方案是,在从上部进行掺杂剂注入之前,通过一个掩模将底部区域的一个互补的局部掩盖。再一个优选的方案是,采用一个自调节式掩模加工步骤。下一个优选的方案是,所述掩模是通过利用光刻和腐蚀的结构转移(Strukturübertragung)产生的。所述掩模的正图或负图最好是通过一个光刻胶层来确定。
通过以上特征,使用通用掩模工艺以能够再现的高精度产生掺杂剂浓度的梯度,其中的通用掩模步骤能够毫无问题地集成到普通的DMOS晶体管制造方法中。
另一个优选的方案是,该方法是在为定义漂移区而进行的硬掩模打开之后采用的。
在此时刻所需的方法步骤不必改变之前或之后的方法步骤,即可集成到通常的制造方法内。
另一个优选的方案是,位于半导体基体内的所述沟槽形漂移区连同一个第一导电类型的第一槽区和一个第二导电类型的第二槽区是部分或全部在所述第二槽区内产生的。
第二个槽在源区方向上延伸得越宽,特征导通电阻Rsp减小得就越多,因为在沟槽形结构的底部和第二槽,具有相同的掺杂极性。同时,晶体管还具有高的击穿电压,因为第一和第二槽的掺杂浓度大大小于源区和漏区的浓度。此外,两个槽区是通过LOCOS氧化法在同一个掩模步骤中以自调节的方式制成的。在此有利的效果是,第一槽更深更长,以通过一个横向PN结在沟槽形结构的下面产生RESURF效应,从而提高击穿电压。
另一个优选的方案是,所述沟槽形漂移区的漏极侧的侧壁和漏区之间制出一个间隔,该间隔优选在0.5微米至4.0微米之间。
本申请人所作的试验表明,在晶体管的击穿范围可实现一种对称性,其条件是在沟槽形结构的漏极侧的侧壁和漏区之间的间隔处在所述界线以内。由于附加的漏极侧电阻产生的电压降可抑制电流密度在局部的升高。特别是与横向调节器相结合可使这种晶体管具有有利的ESD保护结构。
另一个优选的方案是,在所述沟槽形漂移区的侧壁和底部区域内产生的掺杂浓度值高于第一槽区内的掺杂浓度值。
通过该方案可提高RESURF效应,并且由此在提高反向电压的同时降低特征导通电阻Rsp。使沟槽形结构的源极侧的侧壁和漏极侧的侧壁具有相同的掺杂浓度,可简化掺杂剂的渗入,并且可少许提高特征导通电阻Rsp,因为只要漏区直接在沟槽形结构的侧壁上开始,并且漏极侧的掺杂深度在沟槽形结构的深度范围内,则掺杂剂的各个浓度是叠加的。
另一个优选的方案是,所述沟槽形漂移区的高宽比大于0.5,沟槽形结构的宽度位于0.5微米至4.0微米范围内。
本申请人在侧壁和底部不同掺杂剂浓度的试验表明,所述沟槽形结构的高宽比和宽度的绝对值在所给出的数值定义的区间内是有利的。
另一个优选的方案是,所述沟槽形漂移区在底部区域处的宽度小于处在表面的宽度,即向下变细。
通过该方案可抑制沟槽形结构边缘场强过高的现象。
另一个优选方案是,所述沟槽形漂移区是用STI腐蚀法产生的,并且用一种绝缘材料、特别是用一种氧化物填充。
因为掺杂是在硅腐蚀之后采用低能注入实现的,随后并不产生具有高温负荷的厚的LOCOS氧化层,所以在沟槽形结构的下面可在很小的垂直距离上产生空间上高掺杂的区域,它们可形成一个具有低电阻的埋入的电流路径。此外还减小了晶体管的面积消耗,因为相对LOCOS氧化法,通过自调节与同时降低温度负荷相结合,可减小沟槽形结构内的掺杂剂分布的工艺分散度。
一种优选的方案是,所述沟槽形构造是采用LOCOS氧化法制成的。
在这种情况下,所述沟槽形结构是通过V形沟道腐蚀产生的,在随后的由于低的温度负荷而优选地采用的高压氧化法的LOCOS氧化中,将该沟槽形结构填充。侧壁和底部的掺杂在LOCOS氧化之前进行,其中提高围绕在氧化时扩散入氧化物中的部分的掺杂剂的加入剂量。
另一种优选的方案是,所述半导体基体在一层半导体衬底构成的表层下面具有一个绝缘的中间层,并且位于所述表层内的DMOS晶体管是由半导体衬底制成的。
另一种优选的方案是,所述位于沟槽形漂移区下面的半导体衬底构成的表层的厚度处在沟槽形漂移区深度的一半至5倍之间的范围内。
一种优选的方案是,用于利用一块半导体基体制造DMOS晶体管的方法,所述半导体基体包括由半导体衬底构成的、一个具有第二导电类型的源区和漏区的表层,以及一个包围着所述源区的属于第一导电类型的第一槽区,和一个包围着所述漏区的属于第二导电类型的第二槽区,并且在所述半导体基体的由半导体衬底构成的表层的表面上构造有一个栅区,该栅区自源区开始,完全在第一槽区上面延伸,其中所述沟槽形结构是从半导体基体的表面出发,在半导体衬底构成的表层内制成的,而且在沟槽形结构的底部区域内产生第二导电类型的掺杂,而且在所述沟槽形结构的源极侧的侧壁内以第二浓度值产生第二导电类型的掺杂,并在所述沟槽形结构的漏极侧的侧壁内以第三浓度值产生第二导电类型的掺杂。
申请人所作的试验表明,本发明所述方法,特别是根据最后所述方案制成的DMOS晶体管非常适于生产高反向特性的集成电路,该集成电路具有一个用于控制电感负载的输出驱动器。该方案在很大程度上特别适于制造具有一个绝缘中间层的硅晶片制成的DMOS晶体管,这种硅晶片被称为“绝缘硅”(SOI)晶片。
本发明的其他优点参见说明书和附图。
显而易见,以上所述以及下面将要说明的特征不仅适用于所给出的组合方式,而且也适用于其他组合方式或单独存在,这些并不会超出本发明的范围。
附图说明
下面对照附图所示实施例对本发明作进一步的说明。以下各图均为示意图。
图1表示一个SOI晶片的剖视图,它以本发明所述方法的一个实施例作为基础;
图2表示图1所示SOI晶片处在所述方法的较靠后的一个阶段;
图3表示一个掩模步骤,以在漂移区的底部制出掺杂剂浓度梯度;
图4表示所得到的掺杂层的断面。
具体实施方式
图1所示的是一个半导体基体10,它具有一个处在绝缘的中间层14上面的半导体衬底12。这种半导体基体10的一个典型实例的代表是“绝缘硅”晶片,即(SOI)晶片。其中的绝缘的中间层14通常为二氧化硅层。为制造DMOS晶体管,首先要在硅半导体基体10中制出一个第一槽区16和一个第二槽区18。对两个槽区16和18这样进行掺杂,在其内部建立不同的导电类型。为产生P导电类型,例如,对第一槽区16以受主杂质掺杂(三价替代杂质,如硼原子)。同样,为产生N掺杂,对第二槽区18以施主杂质掺杂(五价替代杂质,如砷或磷)。
所述槽区16、18通过光刻胶层中的掩模采用光刻技术来确定。以湿法化学腐蚀步骤在直到硅表面上的光刻胶窗口内去掉氧化层。将一种分散氧化物(Streuoxid)覆盖在暴露出来的硅表面上,然后通过离子注入法进行掺杂。完成了注入步骤之后进行退火和活化工序,使掺杂剂原子深入扩散并活化。在一种SOI晶片的实例中,掺杂剂原子通过扩散工序最后有利地能一直向下抵达绝缘氧化层14。其中有利的方案是,让第一槽区16的扩散时间更长,从而在随后产生的沟槽形结构下面形成一个横向PN结,它可强化RESURF效应,并且能以所希望的方式提高击穿电压。图2表示的即是一个这样的PN结,但其中的横向部分表示得不十分明显。
在下一个工艺步骤中,采用一种例如由氮化物(Nitrit)和/或氧化物制成的硬掩模20将开口21腐蚀出来。其中的腐蚀窗口也是由一个光刻胶掩模定义的。随后通过开口21注入掺杂剂(施主杂质),并且通过热退火和活化步骤(再扩散),在扩散工序中让掺杂剂渗入半导体基体10内,从而在渗入后在半导体基体10中的开口21的下面调整出掺杂剂分布22。
为在掺杂区22的侧面边缘范围内产生不同的浓度,掺杂剂原子的注入以一个例如为60度的倾角进行。在随后进行的工序中,掺杂区22在某种程度上被空心化。这就是说,例如可通过各向异性的STI(浅槽绝缘)腐蚀法制出沟槽结构26。在所述的“浅槽绝缘”工艺中,通过各向异性的腐蚀工艺可在被氮化物保护层覆盖的区域之间产生沟槽,然后再用绝缘材料、如二氧化硅或多晶硅填充。其中所述沟槽的高宽比,即沟槽深度与沟槽宽度之比应小于1,即字面意义上呈扁状。换句话说,一个扁平的沟槽,其宽度大于其深度。
制出了沟槽形结构26之后,事先已经产生的掺杂区22还保留有源极侧的侧面区域29,一个底部区域30和一个漏极侧的侧面区域33。
产生出了沟槽形结构26之后,接着进行的步骤是在沟槽形结构26的侧面区域29、33和底部区域30上确定所要求的掺杂剂分布。为在底部区域30创造产生出一个用于产生横向的掺杂剂浓度梯度的确定的初始状态,可继续进行STI腐蚀,直至完全除掉底部区域30内可能尚存的掺杂剂。直至此时所进行的掺杂,仅仅是确定了侧壁28、32内的掺杂剂浓度,但底部区域30内的掺杂尚未确定。为了能对底部区域30进行掺杂,同时不明显改变侧面区域28和32内的掺杂,首先要在侧壁28和32上面形成一层保护层,其方式是在侧壁上覆盖一薄层分散氧化物。
通过氧化步骤,在第一次注入步骤中余留的掺杂剂同时从侧壁28和32扩散入更深层的范围,其中所形成的第一区域29的源极侧具有第一掺杂剂浓度,第二区域33的漏极侧具有第二掺杂剂浓度。因为注入是在一个倾角下进行的,在注入时该倾角例如是在漏极侧区域33的方向上倾斜的,所以特别是在这种情况下,所述第一掺杂剂浓度与第二掺杂剂浓度是不同的。
下面对照图3加以说明,如何在底部区域30内,在位于底部区域30表面下面的底部区域30中产生横向掺杂剂浓度梯度。
为此首先制出仅将底部区域30部分覆盖的光刻胶掩模34。通过以预定数量的掺杂剂从上方垂直注入,得到一个源极侧的底部区域38和一个漏极侧的底部区域40,其中这两个局部区域38和40的掺杂剂浓度是各不相同的。接着在打开的硬掩模上进行附加的掩模工序,以定义出漂移区。在采用LOCOS氧化工艺的情况下,应在LOCOS之前用一个注入掩模对漂移区的范围进行附加注入。在采用STI工艺的情况下,应在漂移区的底部注入之前或之后,对漂移区的范围进行附加注入。在这两种情况中,要用一个掩模将漂移区的一部分覆盖,并对敞开的区域进行附加掺杂。在后面的工序中,将分别在右边产生漏区,在左边形成源区。
在图3所示的结构具有一个掺杂剂浓度梯度36,它包括首先被覆盖的底部区域38以及随后未被覆盖的底部区域40,后者内所注入的掺杂剂浓度更高。如上所述,对底部区域掺杂剂的注入是从上面垂直进行的,即平行于箭头42所指示的注入方向。显而易见,通过后面的掩模和注入步骤,将光刻掩模34沿横向移动到底部区域30上,可在底部区域30以几乎任意细分的步距实现横向上掺杂剂的变化。
其中有利的效果是,开口的一侧以自调节方式位于硬掩模20的一个边缘31上。这并不强制要求掩模由光刻胶制成;它也可由其他材料制成。显而易见,也可将所述梯度调整到与箭头36不平行的位置。另一个选择是,底部区域30中间的局部的掺杂率高于该中间局部与侧壁28、32之间的边缘区的掺杂率。换句话说,作为对漏极侧附加掺杂的替代,也可对漂移区中间进行附加掺杂。
通过后续的公知工序,可依照图1-3所示的结构继续对DMOS晶体管进行加工,详见图4所示。其中,例如可首先用一种绝缘材料、如CVD氧化物43(CVD=化学气相淀积)将尚敞开的沟槽形结构26填充。并通过CMP步骤(CMP=化学机械法抛光)对沟槽形结构26的表面进行平整。填充沟槽形结构优选地与填充用于确定器件盒(Bauelementeboxen)的其他沟结构同时进行。
在后续的工序中,进一步定义出栅区44、漏区46和源区56,用一层经过钝化的氧化层48覆盖,并通过接触窗工艺,经金属触点50、52和54与印制导线***连接。通过应用具有沟道绝缘的SOI晶片,将所制出的晶体管置于各相互绝缘的器件盒内。
漏区46的优选地确定方式是,它直接与沟槽形结构26的漏区侧的侧壁32相连。其效果是,在漏区侧第二区域33和漏区46内的掺杂剂浓度相互叠加。源区56的优选地确定方式是,它与P型槽区16相连,其中P型槽16在横向上直接与N型槽18相连。
图4中的阴影线的方向分别表示掺杂的极性。凡是负极性区,用自左上至右下的阴影线表示,凡是正极性区,用自左下至右上的阴影线表示。显而易见,相应的极性也可互换。此外,掺杂剂浓度的高低在相应的区域内是用阴影线的密度表示的。
最后还通过工序表示出DMOS晶体管的制造过程。它是基于公知工艺过程实现的,但通过一次或多次自上的注入,在漂移区内附加地产生出所希望的横向浓度分布。采用这种工序可在一块集成电路上同时制造出N型和P型DMOS晶体管。
本发明所述方法也可用于在大块衬底(bulk-Substraten)上制造DMOS晶体管。DMOS晶体管优选在具有绝缘中间层的晶片半导体衬底12的表层内制造。一种有利的方案是,在沟槽形结构下面余留的半导体衬底表层的厚度为沟槽形结构深度的一半至5倍。一个另外的优点是,两个槽区16、18直接与绝缘的中间层14相连,以抑制寄生电容。再一种有利的方案是,半导体衬底12所需的层厚处在几个纳米的范围内,因为与沟槽形结构的底部相连接的高掺杂掩埋沟道仅具有极小的垂直尺寸。
Claims (19)
1、在一半导体基体(10)中制造DMOS晶体管的方法,该半导体基体(10)具有一个沟槽形漂移区(29,30,33),该漂移区包括一个源极侧的侧面区域(29),一个沿横向延伸的底部区域(30)和一个漏极侧的侧面区域(33),其特征是,通过至少一次从上部进行的掺杂剂的注入,在所述底部区域(30)内产生一个沿横向(36)分布的掺杂剂浓度梯度,所述注入仅涉及底部区域(30)的一个局部区域(40)。
2、如权利要求1所述的方法,其特征是,所述底部区域(30)在一个漏极侧的侧壁(28)附近的掺杂率高于底部区域(30)在一个源极侧的侧壁(32)附近的掺杂率。
3、如权利要求1所述的方法,其特征是,所述底部区域(30)的一个中央区的掺杂率高于一个漏极侧的侧壁(28)和/或一个源极侧的侧壁(32)附近的边缘侧的部分区域。
4、如以上权利要求中任何一项所述的方法,其特征是,在该从上部进行的掺杂剂的注入之前,通过一个掩模(34)将底部区域(30)的一个互补的局部区域(38)掩盖。
5、如权利要求4所述的方法,其特征是,采用一个自调节式掩模加工步骤。
6、如权利要求5所述的方法,其特征是,所述掩模是通过利用光刻和腐蚀的结构转移被制出的。
7、如权利要求5所述的方法,其特征是,所述掩模(34)的正图或负图是通过一层光刻胶层来确定。
8、如以上权利要求中任何一项所述的方法,其特征是,该方法是在为定义该漂移区而进行的一个硬掩模(20)打开之后进行的。
9、如权利要求8所述的方法,其特征是,该方法是在可能进行的LOCOS氧化之前进行的。
10、如以上权利要求中任何一项所述的方法,其特征是,位于半导体基体(12)中的所述沟槽形漂移区(29,30,33)连同一个第一导电类型的第一槽区(16)和一个第二导电类型的第二槽区(18)部分或全部在所述第二槽区(18)内被产生。
11、如以上权利要求中任何一项所述的方法,其特征是,所述沟槽形漂移区(29,30,33)的一个漏极侧侧壁(33)和一个漏区(46)之间制出一个间隔,该间隔优选在0.5微米至4.0微米之间。
12、如以上权利要求中任何一项所述的方法,其特征是,在所述沟槽形漂移区(29,30,33)的所述侧壁(28,32)和底部区域(30)内产生的掺杂浓度值高于该第一槽区(16)内的掺杂浓度值。
13、如以上权利要求中任何一项所述的方法,其特征是,所述沟槽形漂移区(29,30,33)的高宽比大于0.5,该沟槽形结构的宽度位于0.5微米至4.0微米的范围内。
14、如以上权利要求中任何一项所述的方法,其特征是,所述沟槽形漂移区(29,30,33)在该底部区域(30)中的宽度小于在表面的宽度。
15、如以上权利要求中任何一项所述的方法,其特征是,所述沟槽形漂移区(29,30,33)是用STI腐蚀法产生的,并且用一种绝缘材料、特别是用一种氧化物填充。
16、如以上权利要求中任何一项所述的方法,其特征是,所述沟槽形漂移区(29,30,33)是用LOCOS氧化法产生的。
17、如以上权利要求中任何一项所述的方法,其特征是,所述半导体基体(12)在一个半导体衬底(12)构成的表层下面具有一个绝缘的中间层(14),并且在所述表层内的该DMOS晶体管是由半导体衬底(12)制成的。
18、如权利要求17所述的方法,其特征是,所述位于该沟槽形漂移区(29,30,33)下面的由半导体衬底(12)构成的表层的厚度处在该沟槽形漂移区(29,30,33)深度的一半至5倍之间的范围内。
19、如权利要求18所述的方法,其特征是,用于利用一半导体基体(10)制造DMOS晶体管的方法中,所述半导体基体(10)包括由一个半导体衬底(12)构成的、一个具有第二导电类型的一个源区(56)和一个漏区(46)的表层,以及一个包围着所述源区(56)的属于第一导电类型的第一槽区(16),和一个包围着所述漏区(46)的属于第二导电类型的第二槽区(18),并且在所述半导体基体(10)的由半导体衬底(12)构成的表层的表面上构造有一个栅区(44),该栅区自源区(56)开始,完全在该第一槽区(16)上面延伸,其中所述沟槽形漂移区(29,30,33)是从该半导体基体(10)的表面出发,在该半导体衬底(12)构成的该表层内制成的,而且在该沟槽形结构的底部区域(30)内产生第二导电类型的掺杂,而且在所述沟槽形漂移区(29,30,33)的源极侧的侧面区域(29)中以第二浓度值产生第二导电类型的掺杂,及在所述沟槽形漂移区(29,30,33)的漏极侧的侧面区域(33)中以第三浓度值产生第二导电类型的掺杂。
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DE10345347A DE10345347A1 (de) | 2003-09-19 | 2003-09-19 | Verfahren zur Herstellung eines DMOS-Transistors mit lateralem Driftregionen-Dotierstoffprofil |
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EP (1) | EP1517361A3 (zh) |
JP (1) | JP2005094012A (zh) |
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Cited By (7)
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CN101536163B (zh) * | 2005-06-10 | 2013-03-06 | 飞兆半导体公司 | 电荷平衡场效应晶体管 |
CN100466289C (zh) * | 2005-12-09 | 2009-03-04 | Atmel德国有限公司 | 具有优化的边缘结构的dmos晶体管 |
CN102637722A (zh) * | 2011-02-12 | 2012-08-15 | 飞思卡尔半导体公司 | 半导体器件及相关制作方法 |
CN102637722B (zh) * | 2011-02-12 | 2016-10-19 | 飞思卡尔半导体公司 | 半导体器件及相关制作方法 |
CN102800688A (zh) * | 2011-05-27 | 2012-11-28 | 旺宏电子股份有限公司 | 半导体结构及其操作方法 |
CN102800688B (zh) * | 2011-05-27 | 2015-03-04 | 旺宏电子股份有限公司 | 半导体结构及其操作方法 |
CN104766861A (zh) * | 2014-01-06 | 2015-07-08 | 株式会社东芝 | 半导体装置及其制造方法 |
Also Published As
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EP1517361A2 (de) | 2005-03-23 |
CA2481834A1 (en) | 2005-03-19 |
US7064385B2 (en) | 2006-06-20 |
US20050062102A1 (en) | 2005-03-24 |
DE10345347A1 (de) | 2005-04-14 |
JP2005094012A (ja) | 2005-04-07 |
EP1517361A3 (de) | 2007-09-05 |
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