CN1532930A - 半导体装置、电子设备及它们的制造方法，以及电子仪器 - Google Patents

半导体装置、电子设备及它们的制造方法，以及电子仪器 Download PDF

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CN1532930A
CN1532930A CNA2004100287544A CN200410028754A CN1532930A CN 1532930 A CN1532930 A CN 1532930A CN A2004100287544 A CNA2004100287544 A CN A2004100287544A CN 200410028754 A CN200410028754 A CN 200410028754A CN 1532930 A CN1532930 A CN 1532930A
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carrier substrate
semiconductor chip
semiconductor
semiconductor device
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CN100442502C (zh
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青栁哲理
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

本发明确保散热性的同时，可以实现不同种类芯片的三维安装结构。半导体芯片(23)用ACF接合法安装在半导体封装PK11的上，在其上面，叠层：用引线接合法连接叠层结构的半导体芯片(33a)、(33b)的半导体封装PK12，以半导体芯片(23)的背面露出的状态，把载体基板(31)安装在载体基板(21)上。

Description

半导体装置、电子设备及它们的制造方法，以及电子仪器
技术领域
本发明涉及半导体装置、电子设备、电子仪器、半导体装置的制造方法和电子设备的制造方法，特别适用于半导体封装等的层叠结构上的。
背景技术
在以往的半导体装置中，为了谋求节省半导体芯片安装时的空间，如专利文献1中所公开内容，通过载体基板三维安装半导体芯片的方法。
【专利文献1】
特开平10-284683
然而，在通过载体基板三维安装半导体芯片的方法中，一面确保散热性的同时层叠不同种类芯片是困难的。
发明内容
因此，本发明的目的是提供一种一面确保散热性的同时，可以层叠不同种类芯片三维安装的半导体装置、电子设备、电子仪器、半导体装置的制造方法和电子设备的制造方法。
为了解决上述问题，根据本发明之一形态的半导体装置，其特征在于，包括：第一载体基板；面朝下安装在上述第一载体基板上的第一半导体芯片；第二载体基板；装载在上述第二载体基板上的第二半导体芯片；为了使上述第二载体基板保持在上述第一半导体芯片上的形态，连接上述第二载体基板和上述第一载体基板的突出电极；密封上述第二半导体芯片的密封部件；为了使上述第一半导体芯片的背面露出，设在上述第一载体基板与上述第二载体基板之间的树脂。
由此，面朝下安装在上述第一载体基板上的第一半导体芯片，在其背面露出的状态，可以把封装不同的第二半导体芯片叠层在第一半导体芯片上。因此，第二载体基板叠层在第一载体基板时，可以确保第一半导体芯片的散热性的同时，也可以实现不同种类芯片的三维安装结构。
另外，根据本发明之一形态的半导体装置，其特征在于，上述第二载体基板以横跨上述第一半导体芯片的形态，固定在第一载体基板。
由此，第一半导体芯片和第二半导体芯片可以重叠布置，可以减少安装多个半导体芯片时的安装面积，节省半导体芯片安装时的空间成为可能。
另外，根据本发明之一形态的半导体装置，其特征在于，上述密封部件是模制成形树脂。
由此，包括第二载体基板的不同种类封装可以叠层在第一载体基板上，即使半导体芯片的种类不同时，也可以实现半导体芯片的三维安装。
另外，根据本发明之一形态的半导体装置，其特征在于，上述密封部件的侧壁和上述第二载体基板的侧壁的位置一致。
由此，第二载体基板叠层在第一载体基板时，可以抑制高度的增大的同时，利用密封第二半导体芯片的密封部件来可以加强第二载体基板的一面全体的同时，不进行密封部件的单元分割且可以密封第二半导体芯片，装载在第二载体基板上的第二半导体芯片的装载面积的增大成为可能。
另外，根据本发明之一形态的半导体装置，其特征在于，上述第一半导体芯片是通过压焊接合来连接在上述第一载体基板上。
由此，可以谋求第一半导体芯片连接在第一载体基板上时的低温化，减少实际使用时的第一载体基板的弯曲(翘曲)成为可能。
另外，根据本发明之一形态的半导体装置，其特征在于，包含上述第一载体基板和装载在上述第一载体基板的上述第一半导体芯片的半导体装置，和包含上述第二载体基板和装载在上述第二载体基板的上述第二半导体芯片的半导体装置，在相同的温度下具有不同的弹性模量。
由此，一方的载体基板来可以抑制另一方的载体基板中所产生的弯曲成为可能，可以提高第一载体基板与第二载体基板之间的连接可靠性。
另外，根据本发明的实施方式的半导体装置，其特征在于：装载上述第一半导体芯片的第一载体基板是倒装片接合法安装的球栅阵列；装载上述第二半导体芯片的第二载体基板是模制成形密封的球栅阵列或芯片尺寸封装。
由此，可以抑制三维安装结构的高度增大的同时，层叠不同种类封装成为可能，即使半导体芯片的种类不同，半导体芯片安装时的节省空间化成为可能。
另外，根据本发明之一形态的半导体装置，其特征在于，上述第一半导体芯片是并列装载在上述第一载体基板的多个半导体芯片。
由此，在多个的第一半导体芯片上，重叠布置第二半导体芯片成为可能，减少安装多个半导体芯片时的安装面积，半导体芯片安装时的节省空间成为可能。
另外，根据本发明之一形态的半导体装置，其特征在于，上述第二半导体芯片是层叠的多个半导体芯片。
由此，在第一半导体芯片上叠层多个不同种类或不同尺寸的第二半导体芯片成为可能，使它具有种种功能的同时，半导体芯片实际安装时的节省空间成为可能。
另外，根据本发明之一形态的半导体装置，其特征在于，上述第二半导体芯片是并列装载在上述第二载体基板的多个的半导体芯片。
由此，可以抑制叠层第二半导体芯片时的高度的增大的同时，在第一半导体芯片上布置多个第二半导体芯片成为可能，可以抑制三维安装时连接可靠性的降低的同时，半导体芯片安装时的节省空间成为可能。
另外，根据本发明之一形态的半导体装置，其特征在于，包括：载体基板；面朝下安装在上述载体基板上的第一半导体芯片；在电极底座形成面上，形成再布置配线层的第二半导体芯片；为了使上述第二半导体芯片保持在上述第一半导体芯片上，连接上述第二半导体芯片和上述载体基板的突出电极。
由此，即使半导体芯片的种类或尺寸不同时，在第一半导体芯片和第二半导体芯片之间，不介入载体基板，而使第一半导体芯片的背面露出的状态，在第一半导体芯片上布置第二半导体芯片的方式，在载体基板上倒装片接合法安装第二半导体芯片成为可能。
因此，叠层半导体芯片时，可以抑制高度增大的同时，确保散热性成为可能，三维安装时，可以抑制半导体芯片的可靠性的降低的同时，半导体芯片安装时的节省空间成为可能。
另外，根据本发明之一形态的电子设备，其特征在于，包括：第一载体基板；装载在上述第一载体基板上的第一电子零件；第二载体基板；装载在上述第二载体基板的第二电子零件；为了使上述第二载体基板保持在上述第一电子零件上的形态，连接上述第二载体基板和上述第一载体基板的突出电极；密封上述第二电子零件的密封部件；以及，为了使上述第一电子零件的背面露出，设在上述第一载体基板与上述第二载体基板之间的树脂。
由此，面朝下安装在第一载体基板上的第一电子零件的背面露出的状态，封装的不同的第二电子零件叠层在第一电子零件成为可能。因此，即使在第一载体基板上叠层第二载体基板时，也可以确保第一电子零件的散热性的同时，实现不同种类零件的三维安装结构成为可能。
另外，根据本发明之一形态的电子仪器，其特征在于，包括：第一载体基板；装载在上述第一载体基板上的第一半导体芯片；第二载体基板；装载在上述第二载体基板上的第二半导体芯片；为了使上述第二载体基板保持在上述第一半导体芯片上的形态，连接上述第二载体基板和上述第一载体基板的突出电极；密封上述第二半导体芯片的密封部件；以及，为了使上述第一半导体芯片的背面露出，设在上述第一载体基板与上述第二载体基板之间的树脂和安装上述第一载体基板的母基板。
由此，面朝下安装在第一载体基板上的第一半导体芯片的背面露出的状态，封装的不同的第二半导体芯片叠层在第一半导体芯片上成为可能，并可以确保第一半导体芯片的散热性的同时，可以实现不同种类芯片的三维安装结构。
另外，根据本发明之一形态的半导体装置的制造方法，其特征在于，包括：将第一半导体芯片面朝下安装在第一载体基板上，以使背面露出的工序；在第二载体基板上安装第二半导体芯片的工序；密封树脂来密封上述第二半导体芯片的工序；通过上述突出电极，连接上述第二载体基板与上述第一载体基板，以便使上述第二载体基板离开一定间隙保持在上述第一半导体芯片的工序。
由此，即使第一载体基板上叠层第二载体基板时，面朝下安装在第一载体基板上的第一半导体芯片的背面露出成为可能。因此，可以有效放出第一半导体芯片所产生的热成为可能的同时，封装的不同的第二半导体芯片叠层在第一半导体芯片成为可能，确保散热性的同时，实现不同种类芯片的三维安装结构成为可能。
另外，根据本发明的半导体装置的制造方法，其特征在于，用上述密封树脂来密封上述第二半导体芯片的工序包括：将安装在上述第二载体基板上的多个的第二半导体芯片，用密封树脂来一体地模制成形的工序；和将由上述密封树脂来模制成形的上述第二载体基板，按每一个上述第二半导体芯片切断的工序。
由此，每一个第二半导体芯片上用不着按单元分割密封树脂，可以用密封树脂来密封第二半导体芯片成为可能的同时，利用密封树脂可以加强第二载体基板的一面全体。
因此，即使第二半导体芯片种类不同或尺寸不同的情况下，模制成形时的金属模可以实现通用化，不仅有效进行密封树脂工序，还可以增大安装在第二载体基板上的第二半导体芯片的装载面积。
另外，根据本发明之一形态的电子设备的制造方法，其特征在于，包括：使第一电子零件的背面露出的形态，将其安装在第一载体基板上的工序；在第二载体基板上安装第二电子零件的工序；用密封树脂来密封上述第二电子零件的工序；通过上述突出电极连接上述第二载体基板与上述第一载体基板，以便使上述第二载体基板离开一定间隙保持在上述第一电子零件上的工序。
由此，即使是在第一载体基板上叠层第二载体基板的情况下，也可以使面朝下安装在第一载体基板的第一电子零件的背面露出。因此，可以有效放出第一电子零件中所产生的热的同时，封装的不同的第二电子零件叠层在第一电子零件成为可能，确保散热性的同时，可以实现不同种类零件的三维安装结构。
附图说明
图1是表示实施方式1的半导体装置结构的剖面图。
图2是表示实施方式2的半导体装置结构的剖面图。
图3是表示实施方式3的半导体装置结构的剖面图。
图4是表示实施方式4的半导体装置制造方法的剖面图。
图5是表示实施方式5的半导体装置制造方法的剖面图。
图6是表示实施方式6的半导体装置结构的剖面图。
图中，
21、30、41、51、61、61a~61c、71、81、101、111、201-载体基板，22a、22c、32a、32c、42a、42c、52a、52c、72a、72b、82、102a、102c、112a、112c、202a、202c-岸面，22b、32b、42b、52b、102b、112b、202b-内部配线，23、33a、33b、43、53a、53b、62a~62c、73、103、113a~113c、203、211-半导体芯片，24、26、36、44、46、55a、56、65a~65c、74、77、83、104、121、123、206、218-突出电极，
25、45、54a、75、105、205-各向异性导电薄膜，34a、34b、54b-粘接层，15、35a、35b、55b、63a~63c-导电性引线，37、57、64、64a~64c、84、120a、120b、122-密封树脂，76-助溶剂，114a~114c、212-电极底座，115a~115c、117a~117c、213-绝缘膜，116a~116c-通孔，118a~118c-导电膜，119a~119c-穿透电极，214-应力缓和层，215-再布置配线，216-焊料保护膜，217-开口部，PK11、PK12、PK21、PK22、PK31、PK32、PK41、PK42、PK51、PK52-半导体助件
具体实施方式
下面，结合附图，说明有关本发明实施方式的半导体装置、电子设备和其制造方法。
图1是表示实施方式1的半导体装置结构的剖面图。另外，该实施方式1是利用ACF接合方法装有半导体芯片(或半导体二极管)23的半导体封装PK11的上面，叠层半导体封装PK12的半导体装置，而所述半导体封装PK12是以引线接合法连接叠层结构的半导体芯片(或半导体二极管)33a、33b的封装。
在图1中，载体基板21设在半导体封装PK11上，在载体基板21的两面，分别形成岸面22a、22c的同时，在载体基板21的内，形成内部配线22b。并且，半导体芯片23露出背面的形态，面朝下安装在载体基板21上，面朝下安装用突出电极24设在半导体芯片23上。并且，设在半导体芯片23上的突出电极24通过各向异性导电薄膜25以ACF(各向异性导电薄膜Anisotropic Conduction Film)方式接合在岸面22c上。另外，在母基板安装载体基板21用的突出电极26设在载体基板21的背面的岸面22a上。
这里，通过ACF接合方式把半导体芯片23安装在载体基板21，不需要引线接合或模制成形密封用的空间，不仅节省三维安装时的空间成为可能，还可以谋求在载体基板21上接合半导体芯片23时的低温化，还可以减少实际使用时的载体基板21的弯曲。
另一方面，载体基板31设在半导体封装PK12上，在载体基板31的两面，分别形成岸面32a、32c的同时，在载体基板31的内，形成内部配线32b。并且，通过粘接层34a，半导体芯片33a面朝下安装在载体基板31上，半导体芯片33a通过导电性引线35a连接在岸面32c上。并且，以避开导电性引线35a的形态，在半导体芯片33a上面朝下安装半导体芯片33b，半导体芯片33b通过粘接层34b固定在半导体芯片33a上的同时，通过导电性引线35b引线连接在岸面32c。
另外，设在载体基板31背面的岸面32a上面，设有在载体基板21安装载体基板31用的突出电极36，以便使载体基板31离开半导体芯片23而保持。这里，突出电极36是避开半导体芯片23的安装区域而布置的，例如，突出电极36可以布置在载体基板31的背面的周围。
于是，通过设在载体基板21上的岸面22c上连接突出电极36，以使半导体芯片23的背面露出的状态，使载体基板31安装在载体基板21上。
由此，面朝下安装在载体基板21上的半导体芯片23的背面露出的状态，把封装的不同的半导体芯片33a、33b叠层在半导体芯片23成为可能。因此，即使载体基板31叠层在载体基板21上的情况下，也可以确保半导体芯片23的散热性的同时，不同种类半导体芯片23、33a、33b可以实现三维安装结构。
另外，用密封树脂37来密封半导体芯片33a、33b，密封树脂37可以利用如环氧树脂等的热固化性树脂的模制成形等方法来形成。
这里，半导体芯片33a、33b的安装面的一侧的载体基板31的一面全体上，由于模制成形形成密封树脂37，即使种种种类的半导体芯片33a、33b安装在载体基板31的情况下，模制成形时的金属模可以实现通用化，可以有效进行密封树脂工序的同时，因为不需要单元分割密封树脂37的空间，可以增大装载在载体基板31的半导体芯片33a、33b的装载面积。
另外，作为载体基板21、载体基板31，可以利用两面基板、多层配线基板、积层基板(build up)、带基板或薄膜基板等；作为载体基板21、载体基板31的材质可以利用聚酰亚胺树脂、玻璃环氧树脂、BT树脂、芳族和环氧树脂的混合或陶瓷等。另外，作为突出电极24、26、36，例如可以利用Au片、利用焊锡料被覆的Cu片、Ni片或焊锡球等。这里，作为突出电极26、36，利用焊锡球的方法，可以使用通用的BGA来叠层不同种类的半导体封装PK11和PK12，可以挪用生产线。另外，作为导电性引线35a、35b，可以利用Au引线、Al引线等。另外，在上述实施方式中，说明了为了把载体基板31安装在载体基板21上，将突出电极36设在载体基板31的岸面32a的方法，但是，突出电极36设在载体基板21的岸面22c上，也是可以的。
另外，在上述实施方式中，说明了利用ACF接合方式把半导体芯片23安装在载体基板21的方法，但是，也可以利用例如，NCF(绝缘薄膜Nonconductive Film)接合、ACP(各向异性导电胶Anisotropic ConductivePaste)接合、NCP(绝缘胶Nonconductive Paste)接合等的其他的接合方法；利用焊锡接合或合金接合等的金属接合法。并且，在上述实施方式中，说明了在载体基板21上安装一个半导体芯片23的方法，但是，在载体基板21上安装多个半导体芯片23，也是可以的。
图2是表示本发明实施方式2的半导体装置结构的图。另外，在该实施方式2是，在利用ACF接合方式安装半导体芯片43的半导体封装PK11的上面，层叠了分别利用倒装片接合法和引线接合法连接叠层结构半导体芯片53a、53b的半导体封装PK22的。
图2中，载体基板41设在半导体封装PK21上，在载体基板41的两面分别形成岸面42a、42c的同时，在载体基板41内，形成内部配线42b。并且，半导体芯片43露出背面地面朝下安装在载体基板41上，面朝下安装用的突出电极44设在半导体芯片43上。并且，设在半导体芯片43上的突出电极44通过各向异性导电薄膜45以ACF方式接合在岸面42c上。另外，在母基板上安装载体基板41用的突出电极46就设在载体基板41的背面的岸面42a上。
这里。由于半导体芯片43以ACF接合方式安装在载体基板41上，不需要引线接合或模制成形密封用的空间，所以不仅节省三维安装时的空间成为可能，可以谋求在载体基板41上接合半导体芯片43时的低温化，还可以减少实际使用时的载体基板41的弯曲成为可能。
另一方面，载体基板51设在半导体封装PK22上，在载体基板51的两面，分别形成岸面52a、52c的同时，在载体基板51内，形成内部配线52b。并且，半导体芯片53a倒装片接合法安装在载体基板51上，倒装片接合法用的突出电极55a设在半导体芯片53a上。并且，设在半导体芯片53a的突出电极55a通过各向异性导电薄膜54a、以ACF接合方式接合在岸面52c上。并且，半导体芯片53b面朝下安装在半导体芯片53a上，半导体芯片53b通过粘接层54b固定在半导体芯片53a上的同时，通过导电性引线55b引线连接在岸面52c。
这里，在面朝下安装的半导体芯片53a上，通过面朝下安装半导体芯片53b的方法，用不着介入载体基板，可以把尺寸相同或尺寸大于半导体芯片53a的半导体芯片53b叠层在半导体芯片53a上面，可以缩小安装面积。
另外，设在载体基板51背面的岸面52a的上面，设有将载体基板51安装在载体基板41用的突出电极56，以便使载体基板51离开半导体芯片43一定间隔保持。这里，突出电极56是避开半导体芯片43装载区域来布置，例如，突出电极56可以布置在载体基板51的背面的周围。并且，在设在载体基板41上的岸面42c上，接合突出电极56的方法，以半导体芯片43的背面露出的状态，使载体基板51安装在载体基板41上的。
由此，面朝下安装在载体基板41上的半导体芯片43的背面露出的状态，封装的不同的半导体芯片53a、53b可以叠层在半导体芯片43上。因此，即使把载体基板51叠层在载体基板41上的情况下，也可以确保半导体芯片43散热性的同时，可以实现不同种类的半导体芯片43、53a、53b的三维安装结构。
另外，作为突出电极46、56，例如可以利用焊锡球。由此，利用通用的GBA的方法，可以叠层不同种类封装PK21、PK22，并可以挪用生产线。
另外，利用密封树脂57来密封半导体芯片53a、53b，密封树脂57可以利用环氧树脂等的热固化性树脂的模制成形来形成。
这里，半导体芯片53a、53b的安装面的一侧的载体基板51的一面全体上，通过模制成形密封树脂57，即使种种种类的半导体芯片53a、53b安装在载体基板51的情况下，模制成形时的金属模也可以实现通用化，可以有效进行密封树脂工序的同时，因为没有必要单元分割密封树脂57的空间，可以增大装载在载体基板51的半导体芯片53a、53b的装载面积。
图3是表示本发明实施方式3的半导体装置的制造方法的剖面图。另外，这个实施方式3是利用密封树脂64来一体性模制成形多个的半导体芯片62a~62c之后，切断每一个半导体芯片62a~62c的方法，在分别安装半导体芯片62a~62c的载体基板61a~61的一面全体上，分别形成密封树脂64a~64c的。
在图3(a)中，在载体基板61上，设有装载多个的半导体芯片62a~62c的装载区域。并且，在载体基板61上安装多个的半导体芯片62a~62c，分别通过导电性引线63a~63c引线连接在载体基板61上。另外，除了利用引线连接半导体芯片62a~62c的方法以外，还可以利用倒装片接合法、在载体基板61上安装半导体芯片62a~62c的方法，还可以利用半导体芯片62a~62c的叠层结构安装在载体基板61的方法。
接着，如图3(b)所示，利用密封树脂64来一体性地模制成形安装在载体基板61的多个的半导体芯片62a~62c。这里，通过密封树脂64来一体性地模制成形安装在载体基板61的多个的半导体芯片62a~62c的方法，即使种种种类半导体芯片62a~62c安装在载体基板61的情况下，模制成形时的金属模可以实现通用化，可以有效进行密封树脂工序的同时，因为没有必要单元分割密封树脂64的空间，可以增大装载在载体基板61的半导体芯片62a~62c的装载面积。
接着，如图3(c)所示，在每一个载体基板61a~61c的背面，形成焊锡球等的突出电极65a~65c。然后，如图3(d)所示，把载体基板61和密封树脂64切断成每一个半导体芯片62a~62c的方法，被分别分割成用密封树脂64a~64c来密封半导体芯片62a~62c的载体基板61a~61c。另外，切断每一个半导体芯片之后，形成焊锡球等的突出电极，也是可以的。
这里，利用一体性地切断载体基板61和密封树脂64的方法，在半导体芯片62a~62c的安装面的一侧的载体基板61a~61c的一面全体上，可以分别形成密封树脂64a~64c。因此，可以抑制制造工序的复杂化的同时，可以提高突出电极65a~65c布置区域的刚性，可以减少载体基板61a~61c的弯曲。
图4是表示本发明实施方式4的半导体装置制造方法的剖面图。另外，该实施方式4是利用ACF接合方法安装半导体芯片73的半导体封装PK31上面，叠层密封树脂84来密封半导体封装PK32的。
在图4(a)中，载体基板71设在半导体封装PK31上，在载体基板71两面，分别形成岸面72a、72b。并且，半导体芯片73倒装片接合法安装在载体基板71，倒装片接合法安装用的突出电极74设在半导体芯片73上。并且，设在半导体芯片73上的突出电极74通过各向异性导电性薄膜75，用ACF接合方法连接在岸面72b。
另一方面，载体基板81设在半导体封装PK32，在载体基板81的背面形成岸面82，在岸面82上，形成焊锡球等的突出电极83。另外，在载体基板81的上面，安装半导体芯片，在装有半导体芯片的载体基板81的一面全体是用密封树脂84来密封的。另外，在载体基板81上面，也可以安装引线接合法连接的半导体芯片；倒装片接合法来安装半导体芯片来安装半导体芯片的叠层结构，也是可以的。
接着，在半导体封装PK31上叠层半导体封装PK32时，在载体基板71的岸面72b上供给助溶剂76。另外，也可以在载体基板71的岸面72b上供给焊锡膏来代替助溶剂76。
接着，如图4(b)所示，在半导体封装PK31上固定半导体封装PK32，进行逆流处理的方法，在岸面72b上接合突出电极83。
接着，如图4(c)所示，在设在载体基板71的背面的岸面72a上形成在母基板上安装载体基板71用的突出电极77。
图5是表示本发明实施方式5的半导体装置制造方法的剖面图。另外，该实施方式5是倒装片接合方法安装的半导体芯片103的载体基板101上面，三维安装层叠结构的半导体芯片113a~113c的。
在图5中，载体基板101设在半导体封装PK41上，在载体基板101两面分别形成岸面102a、102c的同时，在载体基板101内形成内部配线102b。并且，半导体芯片103露出背面的形态，面朝下安装在载体基板101上，面朝下安装用突出电极104设在半导体芯片103上。并且，设在半导体芯片103上的突出电极104通过各向异性导电薄膜105以ACF接合在岸面102c上。另外，在载体基板101上安装半导体芯片103时，除了ACF接合以外，也可以利用如NCF接合、NCP接合、ACP接合等的其他的压焊接合方法，也可以利用焊锡接合或合金接合等的金属接合方法。另外，在母基板上安装载体基板101用的突出电极106设在载体基板101的背面设置的岸面102a上。
另一方面，载体基板111设在半导体封装PK42上，在载体基板111两面分别形成岸面112a、112c的同时，在载体基板111内形成内部配线112b。
另外，电极底座114a~114c分别设在半导体芯片113a~113c上的同时，以每一个电极底座114a~114c露出的形态，分别设有绝缘膜115a~115c。并且，对应于每一个电极底座114a~114c的位置，在半导体芯片113a~113c上形成通孔116a~116c，在通孔116a~116c内，通过绝缘膜117a~117c和导电膜118a~118c分别形成穿透电极119a~119c。
并且，形成有穿透电极119a~119c的半导体芯片113a~113c是分别通过穿透电极119a~119c而叠层，在半导体芯片113a~113c之间的间隙里分别注入树脂120a、120b。
另外，倒装片接合法安装半导体芯片113a~113c叠层结构用的突出电极121就设在半导体芯片113a上形成的穿透电极119a的上面。并且，突出电极121连接在载体基板111上设有的岸面112c上的同时，利用密封树脂122来密封安装在载体基板111上的半导体芯片113a的表面，半导体芯片113a~113c的叠层结构安装在载体基板111上。
另外，设在载体基板111背面的岸面112a上面，设有把载体基板111安装在载体基板101上用的突出电极123，以使载体基板111离开一定距离保持在半导体芯片103上。
这里，突出电极123避开半导体芯片103的装载区域布置的，例如，在载体基板111的周围可以布置突出电极123。然后，设在载体基板101上的岸面102c上接合突出电极123的方法，以半导体芯片103的背面露出的状态，载体基板111安装在载体基板101上。
由此，在半导体芯片113a~113c的叠层结构和半导体芯片103之间，用不着介入载体基板，以半导体芯片103的背面露出的状态，在半导体芯片103上可以倒装片接合法来安装半导体芯片113a~113c的叠层结构。因此，叠层时，可以抑制高度增大的同时，确保半导体芯片103的散热性成为可能，可以抑制三维安装的半导体芯片103、113a~113c可靠性的降低，同时，半导体芯片103和不同种类半导体芯片113a~113c的多层层叠成为可能。
另外，作为突出电极104、106、121、123，可以利用如Au片、由焊锡材料等被覆的Cu片、Ni片或焊锡球。另外，在上述实施方式中，说明了在载体基板111上安装半导体芯片113a~113c的三层结构的方法，但是，安装在载体基板111上的半导体芯片的叠层结构也可以是两层或四层。
图6是表示本发明实施方式6的半导体装置制造方法的剖面图。另外，这个实施方式6是在倒装片接合法的方法安装半导体芯片203的载体基板201上面，三维安装W-CSP(集成电路基板级一芯片大小封装)的实施方式。
在图6中，载体基板201设在半导体封装PK51上，在载体基板201两面分别形成岸面202a、202c的同时，在载体基板201内形成内部配线202b。并且，以半导体芯片203露出背面的形态，面朝下安装在载体基板201上，面朝下安装用的突出电极204设在半导体芯片203上。并且，设在半导体芯片203上的突出电极204通过各向异性导电薄膜205，以ACF方式接合在岸面202c上。另外，安装在母基板上用的突出电极206设在载体基板201的背面的岸面202a上。
另一方面，载体基板211设在半导体封装PK52上，电极底座212设在半导体芯片211的同时，以电极底座212露出的形态，设有绝缘膜213。并且，电极底座212露出的形态，在半导体芯片211上形成应力缓和层214，在电极底座212上形成延伸在应力缓和层214的再布置配线215。并且，在再布置配线215上形成焊料保护膜216，在焊料保护膜216上形成开口部217以便在应力缓和层214上露出再布置配线215。并且，在载体基板201上面朝下安装半导体芯片211用的突出电极218设在通过开口部217露出的再布置配线215的上面，以便使半导体封装PK52离开半导体芯片203保持。
这里，突出电极218是避开半导体芯片203的装载区域来布置，例如，突出电极218可以布置在半导体芯片211的周围。并且，突出电极218连接在载体基板201上设有的岸面202c上，以半导体芯片203的背面露出的状态，使半导体封装PK52安装在载体基板201上。
由此，在倒装片接合法安装半导体芯片203的载体基板201上，可以叠层W-CSP。因此，在半导体芯片203、211的种类或尺寸不同的情况下，在半导体芯片203、211之间没有必要介入载体基板，以半导体芯片203的背面露出的状态，在半导体芯片203上可以三维安装半导体芯片211。其结果，半导体芯片203、211叠层时，可以抑制高度增大的同时，可以确保半导体芯片203的散热性，可以抑制三维安装的半导体芯片203、211的可靠性的降低，同时，可以节省安装半导体芯片203、211时的空间。
另外，把半导体封装PK52安装在载体基板201上时，可以利用ACF接合、NCF接合等的压焊接合方法，也可以利用焊锡接合、合金接合等的金属接合。另外，作为突出电极204、206、208，可以利用Au片、焊锡材料被覆的Cu片、Ni片或焊锡球等。另外，在上述实施方式中，虽然说明了在载体基板201上倒装片接合法安装一个半导体芯片203的上面，安装半导体封装PK52的方法，但是，在载体基板201上倒装片接合法安装多个半导体芯片203的上面，安装半导体封装PK52，也是可以的。
另外，上述半导体装置和电子设备可以应用在液晶显示装置、手机、携带式情报终端机、摄像机、数码相机、MD(微型随身听)、唱机(player)等的电子仪器，可以实现电子仪器的小型·轻量化的同时，可以提高电子仪器的可靠性。
另外，在上述实施方式中，说明了半导体芯片或半导体封装的安装方法，但是，本发明并不限于半导体芯片或半导体封装的安装方法，可以应用在安装弹性表面波(SAW)元件等的陶瓷元件、光变频器、光开关等的光学元件、磁传感器、生物传感器等的各种传感器的安装。

Claims (16)

1、一种半导体装置，其特征在于，包括：
第一载体基板；
面朝下安装在上述第一载体基板上的第一半导体芯片；
第二载体基板；
装载在上述第二载体基板上的第二半导体芯片；
为了使上述第二载体基板保持在上述第一半导体芯片上的形态，连接上述第二载体基板和上述第一载体基板的突出电极；
密封上述第二半导体芯片的密封部件；
为了使上述第一半导体芯片的背面露出，设在上述第一载体基板与上述第二载体基板之间的树脂。
2、根据权利要求1所述的半导体装置，其特征在于：上述第二载体基板以横跨上述第一半导体芯片的形态，固定在第一载体基板。
3、根据权利要求1或2所述的半导体装置，其特征在于：上述密封部件是模制成形树脂。
4、根据权利要求1或2所述的半导体装置，其特征在于：上述密封部件的侧壁和上述第二载体基板的侧壁的位置一致。
5、根据权利要求1~4中的任意1项所述的半导体装置，其特征在于：上述第一半导体芯片是利用压焊接合在上述第一载体基板上。
6、根据权利要求1～5中的任意1项所述的半导体装置，其特征在于：包含上述第一载体基板和装载在上述第一载体基板的上述第一半导体芯片的半导体装置，和包含上述第二载体基板和装载在上述第二载体基板的上述第二半导体芯片的半导体装置，在相同的温度下具有不同的弹性模量。
7、根据权利要求1～6中的任意1项所述的半导体装置，其特征在于：装载上述第一半导体芯片的第一载体基板是倒装片接合法安装的球栅阵列；装载上述第二半导体芯片的第二载体基板是模制成形密封的球栅阵列或芯片尺寸封装。
8、根据权利要求1～7中的任意1项所述的半导体装置，其特征在于：上述第一半导体芯片是并列装载在上述第一载体基板的多个半导体芯片。
9、根据权利要求1～8中的任意1项所述的半导体装置，其特征在于：上述第二半导体芯片是层叠的多个半导体芯片。
10、根据权利要求1～9中的任意1项所述的半导体装置，其特征在于：上述第二半导体芯片是并列装载在上述第二载体基板的多个的半导体芯片。
11、一种半导体装置，其特征在于，包括：
载体基板；
面朝下安装在上述载体基板上的第一半导体芯片；
在电极底座形成面上，形成再布置配线层的第二半导体芯片；
为了使上述第二半导体芯片保持在上述第一半导体芯片上，连接上述第二半导体芯片和上述载体基板的突出电极。
12、一种电子设备，其特征在于，包括：
第一载体基板；
装载在上述第一载体基板上的第一电子零件；
第二载体基板；
装载在上述第二载体基板的第二电子零件；
为了使上述第二载体基板保持在上述第一电子零件上的形态，连接上述第二载体基板和上述第一载体基板的突出电极；
密封上述第二电子零件的密封部件；以及
为了使上述第一电子零件的背面露出，设在上述第一载体基板与上述第二载体基板之间的树脂。
13、一种电子仪器，其特征在于，包括：
第一载体基板；
装载在上述第一载体基板上的第一半导体芯片；
第二载体基板；
装载在上述第二载体基板上的第二半导体芯片；
为了使上述第二载体基板保持在上述第一半导体芯片上的形态，连接上述第二载体基板和上述第一载体基板的突出电极；
密封上述第二半导体芯片的密封部件；以及
为了使上述第一半导体芯片的背面露出，设在上述第一载体基板与上述第二载体基板之间的树脂和安装上述第一载体基板的母基板。
14、一种半导体装置的制造方法，其特征在于，包括：
将第一半导体芯片面朝下安装在第一载体基板上，以使背面露出的工序；
在第二载体基板上安装第二半导体芯片的工序；
密封树脂来密封上述第二半导体芯片的工序；
通过上述突出电极，连接上述第二载体基板与上述第一载体基板，以便使上述第二载体基板离开一定间隙保持在上述第一半导体芯片的工序。
15、根据权利要求14所述的半导体装置的制造方法，其特征在于，用上述密封树脂来密封上述第二半导体芯片的工序包括：
将安装在上述第二载体基板上的多个的第二半导体芯片，用密封树脂来一体地模制成形的工序；和
将由上述密封树脂来模制成形的上述第二载体基板，按每一个上述第二半导体芯片切断的工序。
16、一种电子设备的制造方法，其特征在于，包括：
使第一电子零件的背面露出的形态，安装在第一载体基板上的工序；
在第二载体基板上安装第二电子零件的工序；
用密封树脂来密封上述第二电子零件的工序；
通过上述突出电极连接上述第二载体基板与上述第一载体基板，以便使上述第二载体基板离开一定间隙保持在上述第一电子零件上的工序。
CNB2004100287544A 2003-03-18 2004-03-15 半导体装置、电子设备及它们的制造方法，以及电子仪器 Expired - Fee Related CN100442502C (zh)

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