CN1180924A - 形成带有组合可控缓冲层的功率半导体器件的方法 - Google Patents
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Abstract
一种制造半导体器件的方法及器件,其中,在P+半导体衬底上生长N型牺牲备用层,以吸收衬底中掺杂剂的外扩散。N+缓冲层生长于N型备用层上,N-外延层生长于N+缓冲层上。因备用层的存在,使得最终器件中N+缓冲层的整体掺杂浓度得到精确的控制,备用层在进一步的器件制造过程期间被衬底掺杂剂耗尽。
Description
本发明涉及半导体器件,和制造功率半导体器件及半导体高压开关的方法,在P+半导体衬底上生长N型牺牲备用层(shelf layer),以减小由于掺杂剂从衬底向外扩散而造成的备用层上的N+缓冲层整体掺杂浓度的变化。
在制造如高压开关(例如600-1200伏的绝缘栅双极晶体管)等半导体器件时,要符合严格限定的预定规格(即,最终器件中允许变化的范围很小)。然而,器件制造处理引起的变化会导致某些器件不符合规格,降低了器件的成品率。例如,一种导电率测量规格为1200V的IGBT,要求其集电极发射极饱和电压VCE(SAT)(有时表示成VCE(ON))保持较低,保持在2.0-3.0伏数量级,并严格分布于要求的电压附近。
在某些器件中,例如高压电压开关,尽管已发现在器件制造过程期间VCE(SAT)变化的严重程度至少可以部分控制,但VCE(SAT)会发生不希望的变化,导致器件成品率降低。例如,参见图1,制造高压开关包括在P+衬底14和N-外延层16之间生长N+缓冲层12(所示的该结构是开关的一部分,开关结构的其余部分与本发明无关,且已是众所周知的)。现已发现,在缓冲层12的初始掺杂浓度和厚度增加时,特别是在进行了寿命控制后,VCE(SAT)变化变差(这里还使用整体掺杂浓度这一术语,整体掺杂浓度是指层的掺杂浓度相对于层厚的积分。)。
制造过程中进行半导体器件寿命控制的辐射或其它方法影响着某些器件特性的易变性。辐射用于控制载流子的寿命,一般在器件制造的后期进行,不可避免地要引起器件特性的某些变化。如果缓冲层12的掺杂浓度和厚度也变化,从而引起整体掺杂浓度变化的话,则会放大这种易变性。因此,要求控制缓冲层12的整体掺杂浓度,从而使所有器件的特性严格分布在所要求水平附近。
最终半导体器件中缓冲层12所需的整体掺杂浓度决定着初始浓度、厚度和辐射剂量的选择,并且存在着可以获得所需结果的折衷方法。例如,可以保持辐射剂量较低,作为补偿使初始掺杂浓度和厚度增加。因为器件制造过程中(例如外延生长,高温推进(drives)等)掺杂剂从衬底14向外扩散进入缓冲层12,减小了其厚度和/或掺杂浓度(即,N型区的部分被P型掺杂剂埋没),所以要增加初始掺杂浓度和/或厚度。因此,现有技术中,初始掺杂浓度和层厚开始时大于所需的量,以适应这种收缩性。但令人满意地是避免较高的初始掺杂浓度和缓冲层厚度增加(及附带的较高的整体掺杂浓度),同时保持低辐射剂量,使外延生长更具有可制造性。
如果对N+缓冲层的外扩散作用可以减弱(外扩散自身并不会停止),则初始掺杂浓度和缓冲层厚度(及辐射剂量)可以保持较低。在这种情况下,便可以控制VCE(SAT)的变化,从而可以更容易地满足最终产品的VCE(SAT)规格及其它特性。
一般要求半导体开关有很快的关断能力,某些功率器件甚至为几百纳秒。决定关断速度的一个因素是邻近衬底14和缓冲层12间的PN结18的掺杂浓度。此区域中掺杂浓度高可以使开关操作的关断速度很快,达到令人满意的程度,而邻近PN结18的掺杂浓度低则不会有此效果。
不知是否可以批量生产这种VCE(SAT)严格分布于所要求电压附近且关断速度很快的外延型及寿命可控的半导体功率开关。但是,对N+缓冲层12整体掺杂浓度的严格控制与在PN结18附近提供高掺杂浓度矛盾。
因此,本发明的目的是提供一种制造半导体器件的方法,可以解决上述已知问题。
本发明另一目的是提供一种制造半导体器件的方法,在衬底上生长一层牺牲备用层,以避免由于衬底中掺杂剂外扩散引起的备用层上的缓冲层整体掺杂浓度下降。
再一目的是提供一种通过在衬底和上层缓冲层之间生长备用层减小器件制造过程中引起的半导体器件VCE(SAT)的易变性的方法,备用层的掺杂浓度低于上层缓冲层的掺杂浓度,这样该层可以吸收随后器件处理过程中衬底中掺杂剂的外扩散,但几乎不改变N+缓冲层的净整体掺杂浓度。
本发明涉及一种避免第一导电类型的缓冲层整体掺杂浓度下降的方法,这种下降是由第二导电类型的半导体衬底中的掺杂剂外扩散引起的,在最终的半导体器件中,缓冲层位于衬底和第一导电类型的外延层之间,其特征在于,该方法包括以下步骤:
(a)在衬底上生长备用层;
(b)备用层掺杂成第一导电类型,掺杂浓度低于缓冲层的掺杂浓度及衬底的掺杂浓度;及
(c)衬底中掺杂剂的外扩散基本上耗尽备用层,从而使备用层在最终半导体器件中基本上不存在。
本发明还公开了一种在半导体器件衬底上形成外延层的方法,其特征在于,该方法包括以下步骤:
(a)在掺杂成第二导电类型的半导体器件衬底上生长第一导电类型的备用层;
(b)在备用层上生长第一导电类型的缓冲层;
(c)在缓冲层上生长第一导电类型的外延层,所述衬底有第一电阻率,备用层有大于第一电阻率的第二电阻率,缓冲层有小于第二电阻率的第三电阻率,外延层有大于第三电阻率的第四电阻率,备用层在外延层生长期间吸收衬底中掺杂剂的外扩散。
下面将结合附图用实施例说明本发明,其中:
图1是现有技术半导体器件的部分垂直剖面图;
图2是展示根据本发明实施例提供备用层的步骤的部分半导体器件的垂直剖面图;
图3是展示图2所示实施例中对数掺杂浓度作为半导体器件厚度的函数的曲线图。
按实施例,半导体器件具有牺牲备用层,该层生长于半导体衬底之上,用于避免由于衬底中的掺杂剂外扩散引起的备用层上的缓冲层的整体掺杂浓度下降。备用层吸收衬底中掺杂剂的外扩散,在最终的器件中该层几乎消失。备用层的宽度可以根据器件外延生长和随后处理过程的热量总预算来确定,从而使该备用层能基本上被耗尽。备用层的精确电阻率并不重要,但其电阻率应该大于相邻层的电阻率(衬底和缓冲层),要求其电阻率既不高也不低,不要使将在其中生长各层的外延反应器出问题或因其耗尽影响缓冲层整体掺杂水平。
对于高压开关的优选实施例,参照图2,在P+半导体衬底14上外延生长N备用层20,并在衬底14上外延生长N+缓冲层22。备用层20掺杂的浓度低于相邻的缓冲层22和衬底14,最好比缓冲层22和衬底14低一到两个数量级。例如,备用层20可以掺杂成低于缓冲层22掺杂浓度的约5%。
备用层20吸收在形成备用层后的步骤期间从衬底14和缓冲层22中向外扩散的掺杂剂,所述形成备用层20后的步骤包括生长缓冲层22、外延层16、及随后的高温晶片处理。备用层20的掺杂浓度和厚度选择成使备用层20被外扩散的掺杂剂耗尽,这样,备用层20便在最终的半导体器件中不存在或基本不存在。最终器件中实际残留的备用层20会使器件开关波形的关断电流尾部衰减,这是不希望的。
在图3中可以更清楚地看出由备用层20对掺杂剂的吸收,图3中,实线表示的是初始掺杂浓度和厚度,而虚线表示的是最终掺杂浓度和厚度。由于衬底14和缓冲层22的外扩散,备用层22几乎消失。而且,衬底14和缓冲层22之间的PN结的位置从备用层20的边缘移向靠近缓冲层22的位置。一些掺杂剂还从缓冲层22外扩散到外延层16,尽管由此缓冲层22的厚度变化很小,但如果用慢扩散N型掺杂剂,则缓冲层22的整体掺杂浓度基本上不改变。
引起备用层20几乎完成消失的外扩散可能稍有残余,所以在新PN结处掺杂浓度稍有下降,尽管该下降对器件的工作来说是微不足道的。例如,在用2.1伏正向压降模拟1200伏器件的最终掺杂浓度时,可以得到约300ns的关断时间(150℃时的tFALL),同时发现,如果允许备用层保留于最终器件中的话,则关断时间为约420ns(最坏情况下获得420ns,但实际是可以避免的,从而达到约300ns的要求关断时间)。
于是显示出了两种效果。缓冲层22的整体掺杂浓度基本上与初始浓度相同,这样便不需要增大掺杂浓度和厚度来补偿随后该区的收缩。另外,邻近PN结的掺杂浓度很高,因而,容易快速关断器件。
备用层20的掺杂浓度和厚度可以根据半导体器件的性质进行选择。在高压开关中,备用层20的厚度可以约为4-6微米,掺杂浓度为1E16-5E16原子/cm3,缓冲层的厚度可以约为4-10微米,掺杂浓度为5E17-5E18原子/cm3。外延层16的厚度和电阻率取决于开关的电压能力,对于1200伏的开关来说,厚度可以是约90-100微米,电阻率可以为60-100Ωcm,对于600伏的开关来说,厚度可以为40-50微米,电阻率可以为30-40Ωcm。衬底14可以是常规衬底,一般电阻率小于或等于0.02Ωcm。
本发明的方法可以用于稳定缓冲层,减小各种半导体器件中例如VCE(AST)等具体特性的易变性。例如,该方法可以包括首先确立一层的所需的初始掺杂浓度和厚度及辐射剂量的步骤。该步骤一般可以由本领域的普通技术人员根据器件的设计规格来完成,本发明不再介绍。此后,可以在衬底上生长第一导电类型的备用层,备用层的掺杂浓度应小于相邻层的掺杂浓度,然后以所确立的初始掺杂浓度和厚度在备用层上生长另一层。此后,可以在处理这种器件的常规过程中进行所确立辐射剂量的辐射。在随后的外延生长和高温处理过程中吸收相邻层中掺杂剂的外扩散,从而使该层的整体掺杂浓度基本与初始掺杂浓度相同。
这里公开了一种制造半导体器件的方法和器件,其中在P+半导体衬底上生长N型牺牲备用层,以吸收衬底中掺杂剂的外扩散。在N型备用层上生长N+缓冲层,并在N+缓冲层上生长N-外延层。由于N型备用层的存在,在进一步的器件制造中会被衬底掺杂剂耗尽,使得最终器件中N+缓冲层的整体掺杂浓度得到精确的控制。
Claims (9)
1.一种控制因第二导电类型半导体衬底中掺杂剂外扩散引起的第一导电类型缓冲层的整体掺杂浓度减小的方法,最终的半导体器件中,缓冲层位于衬底和第一导电类型的外延层之间,其特征在于,该方法包括以下步骤:
(a)在衬底上生长备用层;
(b)备用层掺杂成第一导电类型,其掺杂浓度低于缓冲层的掺杂浓度及衬底的掺杂浓度;及
(c)衬底中掺杂剂的外扩散基本上耗尽备用层,从而使备用层在最终半导体器件中基本上不存在。
2.根据权利要求1的方法,其特征在于,掺杂备用层的步骤包括将备用层掺杂到比缓冲层的掺杂浓度小一到两个数量级之间的步骤,掺杂备用层的步骤最好包括将备用层掺杂到小于缓冲层掺杂浓度的5%的步骤。
3.根据权利要求1或2的方法,其中,最终半导体器件是高压半导体开关,生长备用层的步骤包括备用层生长至厚4-6μm的步骤,生长缓冲层的步骤包括生长缓冲层至厚4-10μm的步骤。
4.根据权利要求3的方法,其中,掺杂备用层的步骤还包括掺杂备用层至N-浓度约为5E16原子/cm3(±一个数量级)的步骤,掺杂缓冲层的步骤包括掺杂缓冲层至N+浓度约为1E18原子/cm3(±一个数量级)的步骤,而衬底掺杂成P+浓度大于1E18原子/cm3,其中第一导电类型为N型。
5.一种控制器件制造期间半导体器件的VCE(SAT)变化的方法,该方法通过改变生长于第二导电类型半导体衬底上的第一导电类型缓冲层的初始掺杂浓度进行控制,其特征在于,该方法包括以下步骤:
(a)确立缓冲层的初始掺杂浓度,以提供所需的VCE(SAT);
(b)在衬底上生长第一导电类型的备用层,该备用层的掺杂浓度比缓冲层的初始掺杂浓度小;及
(c)在备用层上以所确立的初始掺杂浓度生长缓冲层,在生长缓冲层期间,备用层吸收衬底中掺杂剂的外扩散,从而在缓冲层上生长了外延层后缓冲层的整体掺杂浓度基本与初始掺杂浓度相同。
6.根据权利要求5的方法,其特征在于,所要求的VCE(SAT)小于3.5伏,其中确立初始整体掺杂浓度的步骤包括将初始掺杂浓度设定在5E17和5E18原子/cm3之间的步骤,和将初始厚度设定在4和10μm之间的步骤。
7.一种在半导体器件衬底上形成外延层的方法,该方法包括以下步骤:
(a)在掺杂成第二导电类型的半导体器件衬底上生长第一导电类型的备用层;
(b)在备用层上生长第一导电类型的缓冲层;
(c)在缓冲层上生长第一导电类型的外延层,所述衬底有第一电阻率,备用层有大于第一电阻率的第二电阻率,缓冲层有小于第二电阻率的第三电阻率,外延层有大于第三电阻率的第四电阻率,备用层在外延层生长期间吸收衬底中掺杂剂的外扩散。
8.根据权利要求7的方法,其中,第一电阻率小于或等于0.02Ω-cm,第二电阻率为0.1-0.4Ω-cm,第三电阻率为0.1-0.3Ω-cm,第四电阻率大于30Ω-cm。
9.一种制造半导体器件的方法,所述半导体器件具有衬底,衬底上有缓冲层,缓冲层上有外延层,所述方法包括以下步骤:在缓冲层和衬底之间提供备用层,并提供具有所要求的整体掺杂浓度的缓冲层,缓冲层的厚度不会阻止衬底通过缓冲层的扩散,这不是因为备用层存在的缘故。
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US708,712 | 1991-05-31 | ||
US08/708,712 US5872028A (en) | 1996-09-05 | 1996-09-05 | Method of forming power semiconductor devices with controllable integrated buffer |
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EP (1) | EP0828290A3 (zh) |
JP (1) | JPH1092841A (zh) |
KR (1) | KR100490801B1 (zh) |
CN (1) | CN1180924A (zh) |
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Cited By (6)
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CN107785424A (zh) * | 2016-08-31 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
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US5940689A (en) * | 1997-06-30 | 1999-08-17 | Harris Corporation | Method of fabricating UMOS semiconductor devices using a self-aligned, reduced mask process |
JP4904625B2 (ja) * | 2001-02-14 | 2012-03-28 | 富士電機株式会社 | 半導体装置 |
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DE102016107557A1 (de) * | 2016-04-22 | 2017-10-26 | Nexwafe Gmbh | Siliziumwafer für ein elektronisches Bauelement und Verfahren zu dessen Herstellung |
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US4696701A (en) * | 1986-11-12 | 1987-09-29 | Motorola, Inc. | Epitaxial front seal for a wafer |
IT1218200B (it) * | 1988-03-29 | 1990-04-12 | Sgs Thomson Microelectronics | Procedimento di fabbricazione di un dispositivo semiconduttore mos di poterza a modulazione di conducibilita' (himos) e dispositivi con esso ottenuti |
JPH0691263B2 (ja) * | 1988-10-19 | 1994-11-14 | 株式会社東芝 | 半導体装置の製造方法 |
US5237183A (en) * | 1989-12-14 | 1993-08-17 | Motorola, Inc. | High reverse voltage IGT |
JP2555942B2 (ja) * | 1993-08-27 | 1996-11-20 | 日本電気株式会社 | 光制御デバイス |
EP0683529B1 (en) * | 1994-05-19 | 2003-04-02 | Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno | Power integrated circuit ("PIC") structure with a vertical IGBT, and manufacturing process thereof |
-
1996
- 1996-09-05 US US08/708,712 patent/US5872028A/en not_active Expired - Lifetime
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1997
- 1997-08-13 TW TW086111623A patent/TW333707B/zh active
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- 1997-08-25 CA CA002213840A patent/CA2213840A1/en not_active Abandoned
- 1997-09-02 JP JP9237135A patent/JPH1092841A/ja active Pending
- 1997-09-04 CN CN97117591A patent/CN1180924A/zh active Pending
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Publication number | Publication date |
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CA2213840A1 (en) | 1998-03-05 |
US5872028A (en) | 1999-02-16 |
KR19980024376A (ko) | 1998-07-06 |
JPH1092841A (ja) | 1998-04-10 |
EP0828290A3 (en) | 1999-01-13 |
EP0828290A2 (en) | 1998-03-11 |
KR100490801B1 (ko) | 2005-08-29 |
TW333707B (en) | 1998-06-11 |
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