CA1041673A - Transistor - Google Patents
TransistorInfo
- Publication number
- CA1041673A CA1041673A CA233,056A CA233056A CA1041673A CA 1041673 A CA1041673 A CA 1041673A CA 233056 A CA233056 A CA 233056A CA 1041673 A CA1041673 A CA 1041673A
- Authority
- CA
- Canada
- Prior art keywords
- emitter
- zone
- transistor
- base
- emitter zone
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 6
- 238000009792 diffusion process Methods 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims abstract description 3
- 230000035515 penetration Effects 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000000969 carrier Substances 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 11
- 230000010354 integration Effects 0.000 abstract description 3
- 239000000306 component Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 230000003321 amplification Effects 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 241000429017 Pectis Species 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002674 ointment Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
ABSTRACT
A semiconductor component particularly suitable for integration has at least two zones of different conductivity types, each of the zones being provided with at least one electrode, at least one of the electrodes consisting of initially undoped polycrystalline silicon which has subse-quently been doped by diffusion or ion implantation. The invention is particularly applicable to transistors the emitter electrode being made of polycrystalline silicon.
A semiconductor component particularly suitable for integration has at least two zones of different conductivity types, each of the zones being provided with at least one electrode, at least one of the electrodes consisting of initially undoped polycrystalline silicon which has subse-quently been doped by diffusion or ion implantation. The invention is particularly applicable to transistors the emitter electrode being made of polycrystalline silicon.
Description
The present invention relates to semiconductor components having at least two zones of different conductivity types, each of which zones is provided with at least one electrode, and to integrated circuits including .
such components.
A process has already been proposed in German Patent Specification No. P 24 29 957.8 for the production of a doped zone of one conductivity ~ ;~
type in a semiconductor body, in which a polycrystalline semiconductor layer is deposited on the surface of the body at the region which is to be doped, ;
the deposited polycrystalline semiconductor layer being undoped, and sub~
sequently diffusing the dopant which produces the doped zone of one conduct~
ivity type from the gas phase through the polycrystalline semi-conductor layer into the semiconductor body.
This process differs from the so called "DOPOS'I technique, in which doped, polycrystalline silicon is used as a dopant source to produce ~ ~;
the emitter of a transistor (see "Proceedings of the 4th Conference on ^~
Solid State Devlces", Toky~, 1972).
It is an object of the present invention to provide a semi~
oonductor component of the type referred to above which can have particularly ~ ;
small dimensions and is therefore suîtable for integration, and in the case of a transistor has a high current amplification and a high emitter yield.
According to the invention, there is provided a transistor having ;
~ , an emitter zone, a base one beneath the emitter ~one, and an emitter electrode consisting of initially undoped polycrystalline silicon, which is doped by diffusion or ion implantation after formation therethrough of the emitter zone~ wherein said emitter zone possesses a very high yield with a Gummel coefficient GE ~ 1 x 10 s.cm , the Gummel coefficient GE being ~ -defined by the equation~
.
~ -2-, ~," . , ~ , " . . . . .
',`'~ ': "
~ eff ( ) GE J D~ tx) where N f~(X~ is the effective doping of the emitter zone between a surface of contact with the emitter electrode (x = 0) and the emitter penetration depth ~ and D (x) is the diffusion coefficient of minority carriers in the emitter zone, the penetration depth of the emitter zone in the monocrystal ~ -... : .
being less than 0.1 ~ and the penetration depth of the base zone beneath the `~ ;
emitter zone being in the range of 0.2 to 0.7 Components in accordance with the invention have a low internal `~
track resistance and a low noise level, and in the case of transistors a ;~
high current amplification.
.~ The present invention facilitates the production of transistors A~
having a very small area requirement and a high current amplification, even though the base doping below the emitter zone is high. The emitter yield is considerably greater than in conventional transistors. A gauge ~or the `~ .... . .
yield is the so-called emitter-Gummel coefficient which in transistors `~
,.~
14 ~ ~;
according to the invention, may be as much as 4 x 10 s.cm , in comparison with the value of 2 x 1013 s.cm for conventional transistors. (These 'r;. ~''` .
figures relate to emitter depths of 3 to 4 y).
The strong base doping, in combination with the high current : .
amplification~ causes the current amplification maximum and the cut-off ''!`' frequency to be displaced by a factor of approximately 5 in the direction ~;
of higher emitter currents. This means that the ~`
:
-,:
.,~
: ::
" ~ ,,, ,, , " , .... .
emitter length can be reduced by a factor of approximately 5 for the same current capacity as compared with conventional tran3istors. At the same time the emitter/base capacitance and, due to the possibillty of reducing the area of the base zone, al~o the ba~e~collector and collector/substrate capacitance~ are at the same time reduced.
Conveniently, the base 20ne is bou~ded by an oxide layer in a direction at right-angles to the plane of the emittex electrode. ;
The emitter zone may also convenie~tly be bounded by an oxide layer in a direction at right-an~le9 to the plane of the emitter electrode.
lhe use of this "o~ide insulation technique" as it is ~alled enables ;
sub~tantially smaller transistors to be produced in integrated circuits.
~ ~he in~ention will now be ~uxther described with reference to the drawing~ in which :-~igure 1 is a schematic side-se~ctional ~iew o~ a known ., . . .~ .
transistor; and Figure~ 2 to 4 are si~ilar ~ie~s to that of Figure 1 o~ ~`
three embodiments of the i~vention~ .
In the ~arious ~igures "corresponding elements are denoted by the ~ame reference numeral.
Re~erring to Figure 1, a p-conducting ~emiconductor substrate ~ ~
1 has epitaxially deposited thereon an n-conducting ~emiconductor ~-layer 2~ At the boundary between the layer 2 and the substra~e 1, a strongly doped n+~-conductlng zone 3 is located beneath a known transistor ~ormed in the layer 2. '~his ~one 3 serve~ as a "buried laye~ he transistor itself has an n+-conducting emittex zone 6 and a p-conducting ba~e æone 8 with a ba~e terminal zone 9; the collector æone of the trans~ stor consi~tsof that par-t of the seml-conductor la,yer 2 locat ed between p-conducti~g i~olating wall~ 7 .
A~ n+-conducting Pone 5 extending from the ~ur~ace to the æone 3 ~ also provided ~or contacting the ~one 3. On the 3urface ~1 o~ l;
,' , , I .
the ~emiconductor layer 2 there iB ar.ranged a ~ilicon dioxide . ~-layer 22 ha~ing window~ 23, 24 and 24'therein leading to the collector, the base and the emit-ter zones re~pecti~ely. The metal csntact~ for the ~arious zones (whic~ contacts for simplicity hav.e been omitted from the drawing) contact the respective zones through these wlndo~Js. A~ illustrated in ~igure 1, the base %one 8 possesse~ a bulging portion 25 beneath the emitter zone 6 due to the so-called ~emitter-dip-e~ect", as a result o~ which the frequency characteristics of the transi~tor~ :
10 are impairedO ~ `
~igure 2 illustrates a transi~tor in accordanoe with the invent~on which di~fers from the ~nown transistor of Figure 1 by ~ :
having an emitter electrode 10 which consists of initially undoped polycrystalline silicon which has subse~uently been doped by di~f-u~ion or ion imp~antation. ~he emitte.r zone 16 o~ this transistorhas a con~iderably ~maller depth of penetration into the mono-cry~tal than the emitter zone 6 of the known transistor. Moreover, .
the base zone 18 of the transi~tor of ~igure 2 does not have a. ~.. :
bulging po~t~on corre po~ding to the portion 25 o~ the known tran~istor.
~he transistor illustrated in ~igure 2 is produced in the u~ual way except for the production of the emitter zone 16. ~he - zone~ 5, 7, 9, 18 axe thus introduce~ into the epitaxially de- .
po~ited semiconductor layer 2 making u~e of a mask. ~he zone 3 was also initially di~fused into the surface o~ the semiconductor substrate 1 before the deposition of the layer 2 also by using a masklng technique. ~aturally~ the individual zone~ can al~o be producea by lon impla~tation or other suitable method~, if desiredO ~ -Xt i.s however, essential that the doping o~ the emitter 30 zone 16 should be carried out through undoped polycry~talline ilicon ~or which purpo~e the emltter electrode 10 is usedO
~his means that t prlor to the forma1;ion of the emltter zone 16 ~,',;, ,,,. . , , . ~ .
3 : `
by dif~uslon, the emitter electrode 10 iæ applied to the ~urface 21 o~ the base zone 18 in the window 24, and that the dlffusion to ~orm the emitter zone 16 is then carried out through the emitter electrode 10. This also applie~ to the 5 embodiments illustrated in ~igures 3 and 4. ~he penetration .
depth o~ these emitter zones i~ thu~ kept'extremely small (~ee German Patent Specification ~ P. 24 29 95708). :~
-~he-exemplary embodiments o~ ~igures 3 and 4 di~fer ~rom -the exemplary embodiment of ~igure 2 in that, lnst ead of the isolatin~ zone~ 7, which together with the semiconductor substrate :~
1 form an isolated trough in which the transi~tor is located, 3ilicon dioxide layer~ 13 and 14 are provided for the isolation of the transistor from adjacent component~. In Figure 3 the base - zone 18 is bounded by a silioon dioxide layer 14 and a silicon 1~ dioxide layer.12~ In the exemplar~ embodiment of ~igure 4, the emitter ~one 16 is al~o bounded on at least one side by the silicon dioxide la~er 1~. Also, a~ îs u~ual, a æilicon dioxide layer 15 i~ provided on the surface of' the crystal to insulate ::;
the emitter electrode 10 from the.base ~one 18. ~he collector electrode is connected thr0ugh a hl~hly doped n~-conducting ~one .
20 bounaea by the silicon dioxi~e layer ~2 and a ~urther silicon.
dioxide layer 13, and through the n~-conducting zone 3 to that ~:
part o~ the ~emiconductor layer 2 lying between the ~illcon dioxide 1ayer~ 12 and 14.
~n the exemplary embodiment o~ ~igures 3 and ~, the base ~:
zone 18, one gide o~ a bage contact ~n the contact windo~ 34, ~ ~-the collector ~one and a collector contact in the contact window . 33 are bounded by various ones of the ~ilicon dioxide layer~ 12, 13 and 14~ wh~ch ~imultaneously serve for isola~lon purpose~ In 30 the exemplary embodiment of ~igure 4, the emitter ~one 16 and ~he emitter contact 1~ are additionall~ bounded by the ~ilicon dioxide layer 14 on at lea~t one ~3ide. ' ., ,. .. ....... . . .. .
. . . . - . . :
, ~,,, . , ,: , . -73.
As can be ~een from the ~arious ~igures, the u~e of the oxide boundaries ha~ the advantage that it enables particularly small structure~ to be produced, so that the semiconductor compo-nent in accordance with -the invention produced is particularly ~uitable ~or integration~
~ he emall penetration depth o~ the e~itter zone.prevent~
any pos~ibility o~ a short-circuit between the emitter zone and the collector ~one which can occur in the case of an oxide-bounded emitter zone when the emitter zone has a normal penetration depth ~ .
10 as in Figure 1. ~he possibility of such a short-circuit is due ~ ;
to the fact that, becau~e of the "pile-down" effect, the p-n ~unction between the base ~one 18 and the collector zone is bent upwardly to some extent at the boundary with the silicon dioxide layers 12 and 149 as indicated in ~igure 4 by broken lines 40. .
~he use sf a polycry~talline emitter electrode 10, together with the ~ery small penetrat~ion depth of the emitter zone 16, thus fac~lltate~ the use of an o~ide boundary which itself in tur~
leads to the possibility of very small dime~sions for the component.
~ comparison between the propertie~ of the known transistor : : 20 of Figure 1 and the individual exemplary embodiments of ~igure~ 2 to 4, i~ given in the following ~able, in which ~I~, FB~ ~E~ CB' :
CE,. RB and RC signi~y respectively the tr~nsistor sur~ace, the . base surface, the emitter sux~ace, the ba~e capacita~ce, the . - .
emitter capacitance9 the resi~tance of the base zone and the :
resista~ce of the collector ~one, the base zone having a layex resi~tance of 500 ohm~/square with a penetration depth of about 0~7 ~-_ _ _ _, __ _ . I'ransietor ~ ~B ~ C~ aE ~B R~
shown in (~2j (~2) (I~) (P~ (P~) (oh~ ~hm) .
~___~ _~ ~ _~ ., ~ig. 1 2j100 440 48 0.16 0O12200 40 Flg. 2 1,700 260 16 00095 0005400 100 Fig. 3 750 215 16 0.080 0005400 100 ~ig. 4 410 60 16 000~2 0.041,000 200 __ _~ __ ~, :.:
. .,,:. , . ,~ .,.. . :
~" ~
such components.
A process has already been proposed in German Patent Specification No. P 24 29 957.8 for the production of a doped zone of one conductivity ~ ;~
type in a semiconductor body, in which a polycrystalline semiconductor layer is deposited on the surface of the body at the region which is to be doped, ;
the deposited polycrystalline semiconductor layer being undoped, and sub~
sequently diffusing the dopant which produces the doped zone of one conduct~
ivity type from the gas phase through the polycrystalline semi-conductor layer into the semiconductor body.
This process differs from the so called "DOPOS'I technique, in which doped, polycrystalline silicon is used as a dopant source to produce ~ ~;
the emitter of a transistor (see "Proceedings of the 4th Conference on ^~
Solid State Devlces", Toky~, 1972).
It is an object of the present invention to provide a semi~
oonductor component of the type referred to above which can have particularly ~ ;
small dimensions and is therefore suîtable for integration, and in the case of a transistor has a high current amplification and a high emitter yield.
According to the invention, there is provided a transistor having ;
~ , an emitter zone, a base one beneath the emitter ~one, and an emitter electrode consisting of initially undoped polycrystalline silicon, which is doped by diffusion or ion implantation after formation therethrough of the emitter zone~ wherein said emitter zone possesses a very high yield with a Gummel coefficient GE ~ 1 x 10 s.cm , the Gummel coefficient GE being ~ -defined by the equation~
.
~ -2-, ~," . , ~ , " . . . . .
',`'~ ': "
~ eff ( ) GE J D~ tx) where N f~(X~ is the effective doping of the emitter zone between a surface of contact with the emitter electrode (x = 0) and the emitter penetration depth ~ and D (x) is the diffusion coefficient of minority carriers in the emitter zone, the penetration depth of the emitter zone in the monocrystal ~ -... : .
being less than 0.1 ~ and the penetration depth of the base zone beneath the `~ ;
emitter zone being in the range of 0.2 to 0.7 Components in accordance with the invention have a low internal `~
track resistance and a low noise level, and in the case of transistors a ;~
high current amplification.
.~ The present invention facilitates the production of transistors A~
having a very small area requirement and a high current amplification, even though the base doping below the emitter zone is high. The emitter yield is considerably greater than in conventional transistors. A gauge ~or the `~ .... . .
yield is the so-called emitter-Gummel coefficient which in transistors `~
,.~
14 ~ ~;
according to the invention, may be as much as 4 x 10 s.cm , in comparison with the value of 2 x 1013 s.cm for conventional transistors. (These 'r;. ~''` .
figures relate to emitter depths of 3 to 4 y).
The strong base doping, in combination with the high current : .
amplification~ causes the current amplification maximum and the cut-off ''!`' frequency to be displaced by a factor of approximately 5 in the direction ~;
of higher emitter currents. This means that the ~`
:
-,:
.,~
: ::
" ~ ,,, ,, , " , .... .
emitter length can be reduced by a factor of approximately 5 for the same current capacity as compared with conventional tran3istors. At the same time the emitter/base capacitance and, due to the possibillty of reducing the area of the base zone, al~o the ba~e~collector and collector/substrate capacitance~ are at the same time reduced.
Conveniently, the base 20ne is bou~ded by an oxide layer in a direction at right-angles to the plane of the emittex electrode. ;
The emitter zone may also convenie~tly be bounded by an oxide layer in a direction at right-an~le9 to the plane of the emitter electrode.
lhe use of this "o~ide insulation technique" as it is ~alled enables ;
sub~tantially smaller transistors to be produced in integrated circuits.
~ ~he in~ention will now be ~uxther described with reference to the drawing~ in which :-~igure 1 is a schematic side-se~ctional ~iew o~ a known ., . . .~ .
transistor; and Figure~ 2 to 4 are si~ilar ~ie~s to that of Figure 1 o~ ~`
three embodiments of the i~vention~ .
In the ~arious ~igures "corresponding elements are denoted by the ~ame reference numeral.
Re~erring to Figure 1, a p-conducting ~emiconductor substrate ~ ~
1 has epitaxially deposited thereon an n-conducting ~emiconductor ~-layer 2~ At the boundary between the layer 2 and the substra~e 1, a strongly doped n+~-conductlng zone 3 is located beneath a known transistor ~ormed in the layer 2. '~his ~one 3 serve~ as a "buried laye~ he transistor itself has an n+-conducting emittex zone 6 and a p-conducting ba~e æone 8 with a ba~e terminal zone 9; the collector æone of the trans~ stor consi~tsof that par-t of the seml-conductor la,yer 2 locat ed between p-conducti~g i~olating wall~ 7 .
A~ n+-conducting Pone 5 extending from the ~ur~ace to the æone 3 ~ also provided ~or contacting the ~one 3. On the 3urface ~1 o~ l;
,' , , I .
the ~emiconductor layer 2 there iB ar.ranged a ~ilicon dioxide . ~-layer 22 ha~ing window~ 23, 24 and 24'therein leading to the collector, the base and the emit-ter zones re~pecti~ely. The metal csntact~ for the ~arious zones (whic~ contacts for simplicity hav.e been omitted from the drawing) contact the respective zones through these wlndo~Js. A~ illustrated in ~igure 1, the base %one 8 possesse~ a bulging portion 25 beneath the emitter zone 6 due to the so-called ~emitter-dip-e~ect", as a result o~ which the frequency characteristics of the transi~tor~ :
10 are impairedO ~ `
~igure 2 illustrates a transi~tor in accordanoe with the invent~on which di~fers from the ~nown transistor of Figure 1 by ~ :
having an emitter electrode 10 which consists of initially undoped polycrystalline silicon which has subse~uently been doped by di~f-u~ion or ion imp~antation. ~he emitte.r zone 16 o~ this transistorhas a con~iderably ~maller depth of penetration into the mono-cry~tal than the emitter zone 6 of the known transistor. Moreover, .
the base zone 18 of the transi~tor of ~igure 2 does not have a. ~.. :
bulging po~t~on corre po~ding to the portion 25 o~ the known tran~istor.
~he transistor illustrated in ~igure 2 is produced in the u~ual way except for the production of the emitter zone 16. ~he - zone~ 5, 7, 9, 18 axe thus introduce~ into the epitaxially de- .
po~ited semiconductor layer 2 making u~e of a mask. ~he zone 3 was also initially di~fused into the surface o~ the semiconductor substrate 1 before the deposition of the layer 2 also by using a masklng technique. ~aturally~ the individual zone~ can al~o be producea by lon impla~tation or other suitable method~, if desiredO ~ -Xt i.s however, essential that the doping o~ the emitter 30 zone 16 should be carried out through undoped polycry~talline ilicon ~or which purpo~e the emltter electrode 10 is usedO
~his means that t prlor to the forma1;ion of the emltter zone 16 ~,',;, ,,,. . , , . ~ .
3 : `
by dif~uslon, the emitter electrode 10 iæ applied to the ~urface 21 o~ the base zone 18 in the window 24, and that the dlffusion to ~orm the emitter zone 16 is then carried out through the emitter electrode 10. This also applie~ to the 5 embodiments illustrated in ~igures 3 and 4. ~he penetration .
depth o~ these emitter zones i~ thu~ kept'extremely small (~ee German Patent Specification ~ P. 24 29 95708). :~
-~he-exemplary embodiments o~ ~igures 3 and 4 di~fer ~rom -the exemplary embodiment of ~igure 2 in that, lnst ead of the isolatin~ zone~ 7, which together with the semiconductor substrate :~
1 form an isolated trough in which the transi~tor is located, 3ilicon dioxide layer~ 13 and 14 are provided for the isolation of the transistor from adjacent component~. In Figure 3 the base - zone 18 is bounded by a silioon dioxide layer 14 and a silicon 1~ dioxide layer.12~ In the exemplar~ embodiment of ~igure 4, the emitter ~one 16 is al~o bounded on at least one side by the silicon dioxide la~er 1~. Also, a~ îs u~ual, a æilicon dioxide layer 15 i~ provided on the surface of' the crystal to insulate ::;
the emitter electrode 10 from the.base ~one 18. ~he collector electrode is connected thr0ugh a hl~hly doped n~-conducting ~one .
20 bounaea by the silicon dioxi~e layer ~2 and a ~urther silicon.
dioxide layer 13, and through the n~-conducting zone 3 to that ~:
part o~ the ~emiconductor layer 2 lying between the ~illcon dioxide 1ayer~ 12 and 14.
~n the exemplary embodiment o~ ~igures 3 and ~, the base ~:
zone 18, one gide o~ a bage contact ~n the contact windo~ 34, ~ ~-the collector ~one and a collector contact in the contact window . 33 are bounded by various ones of the ~ilicon dioxide layer~ 12, 13 and 14~ wh~ch ~imultaneously serve for isola~lon purpose~ In 30 the exemplary embodiment of ~igure 4, the emitter ~one 16 and ~he emitter contact 1~ are additionall~ bounded by the ~ilicon dioxide layer 14 on at lea~t one ~3ide. ' ., ,. .. ....... . . .. .
. . . . - . . :
, ~,,, . , ,: , . -73.
As can be ~een from the ~arious ~igures, the u~e of the oxide boundaries ha~ the advantage that it enables particularly small structure~ to be produced, so that the semiconductor compo-nent in accordance with -the invention produced is particularly ~uitable ~or integration~
~ he emall penetration depth o~ the e~itter zone.prevent~
any pos~ibility o~ a short-circuit between the emitter zone and the collector ~one which can occur in the case of an oxide-bounded emitter zone when the emitter zone has a normal penetration depth ~ .
10 as in Figure 1. ~he possibility of such a short-circuit is due ~ ;
to the fact that, becau~e of the "pile-down" effect, the p-n ~unction between the base ~one 18 and the collector zone is bent upwardly to some extent at the boundary with the silicon dioxide layers 12 and 149 as indicated in ~igure 4 by broken lines 40. .
~he use sf a polycry~talline emitter electrode 10, together with the ~ery small penetrat~ion depth of the emitter zone 16, thus fac~lltate~ the use of an o~ide boundary which itself in tur~
leads to the possibility of very small dime~sions for the component.
~ comparison between the propertie~ of the known transistor : : 20 of Figure 1 and the individual exemplary embodiments of ~igure~ 2 to 4, i~ given in the following ~able, in which ~I~, FB~ ~E~ CB' :
CE,. RB and RC signi~y respectively the tr~nsistor sur~ace, the . base surface, the emitter sux~ace, the ba~e capacita~ce, the . - .
emitter capacitance9 the resi~tance of the base zone and the :
resista~ce of the collector ~one, the base zone having a layex resi~tance of 500 ohm~/square with a penetration depth of about 0~7 ~-_ _ _ _, __ _ . I'ransietor ~ ~B ~ C~ aE ~B R~
shown in (~2j (~2) (I~) (P~ (P~) (oh~ ~hm) .
~___~ _~ ~ _~ ., ~ig. 1 2j100 440 48 0.16 0O12200 40 Flg. 2 1,700 260 16 00095 0005400 100 Fig. 3 750 215 16 0.080 0005400 100 ~ig. 4 410 60 16 000~2 0.041,000 200 __ _~ __ ~, :.:
. .,,:. , . ,~ .,.. . :
~" ~
Claims (4)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A transistor having an emitter zone, a base zone beneath the emitter zone, and an emitter electrode consisting of initially undoped polycrystalline silicon, which is doped by diffusion or ion implantation after formation therethrough of the emitter zone, wherein said emitter zone possesses a very high yield with a Gummel coefficient GE > 1 x 1014 s.cm-4, the Gummel coefficient GE being defined by the equation:
where Neff(x) is the effective doping of the emitter zone between a surface of contact with the emitter electrode (x = 0) and the emitter penetration depth xE and Dp(x) is the diffusion coefficient of minority carriers in the emitter zone, the penetration depth of the emitter zone in the mono-crystal being less than 0.1 µ and the penetration depth of the base zone beneath the emitter zone being in the range of 0.2 to 0.7 µ.
where Neff(x) is the effective doping of the emitter zone between a surface of contact with the emitter electrode (x = 0) and the emitter penetration depth xE and Dp(x) is the diffusion coefficient of minority carriers in the emitter zone, the penetration depth of the emitter zone in the mono-crystal being less than 0.1 µ and the penetration depth of the base zone beneath the emitter zone being in the range of 0.2 to 0.7 µ.
2. A transistor as claimed in claim 1, wherein the Gummel coefficient GE of the emitter zone is 3 x 1014 s.cm-4.
3. A transistor as claimed in claim 1 wherein the base zone is bounded by respective oxide layers at right-angles to a plane containing the emitter electrode.
4. A transistor as claimed in claim 1, 2 or 3 wherein the emitter zone is bounded at least at one side, by an oxide layer at right-angles to a plane containing the emitter electrode.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2439408A DE2439408A1 (en) | 1974-08-16 | 1974-08-16 | SEMICONDUCTOR COMPONENT |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1041673A true CA1041673A (en) | 1978-10-31 |
Family
ID=5923395
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA233,056A Expired CA1041673A (en) | 1974-08-16 | 1975-08-07 | Transistor |
Country Status (9)
| Country | Link |
|---|---|
| JP (1) | JPS5164370A (en) |
| AT (1) | AT372805B (en) |
| BR (1) | BR7505197A (en) |
| CA (1) | CA1041673A (en) |
| DE (1) | DE2439408A1 (en) |
| FR (1) | FR2282166A1 (en) |
| GB (1) | GB1494802A (en) |
| IT (1) | IT1040480B (en) |
| ZA (1) | ZA754328B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61224448A (en) * | 1985-03-29 | 1986-10-06 | Toshiba Corp | Manufacture of semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4855663A (en) * | 1971-11-10 | 1973-08-04 | ||
| JPS499186A (en) * | 1972-05-11 | 1974-01-26 |
-
1974
- 1974-08-16 DE DE2439408A patent/DE2439408A1/en not_active Ceased
-
1975
- 1975-06-20 GB GB26264/75A patent/GB1494802A/en not_active Expired
- 1975-07-07 ZA ZA00754328A patent/ZA754328B/en unknown
- 1975-07-15 AT AT0546075A patent/AT372805B/en not_active IP Right Cessation
- 1975-08-05 IT IT26108/75A patent/IT1040480B/en active
- 1975-08-06 FR FR7524515A patent/FR2282166A1/en active Granted
- 1975-08-07 CA CA233,056A patent/CA1041673A/en not_active Expired
- 1975-08-14 BR BR7505197*A patent/BR7505197A/en unknown
- 1975-08-15 JP JP50099451A patent/JPS5164370A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| ATA546075A (en) | 1983-03-15 |
| IT1040480B (en) | 1979-12-20 |
| ZA754328B (en) | 1976-06-30 |
| AT372805B (en) | 1983-11-25 |
| JPS5164370A (en) | 1976-06-03 |
| FR2282166A1 (en) | 1976-03-12 |
| DE2439408A1 (en) | 1976-02-26 |
| FR2282166B1 (en) | 1980-10-17 |
| BR7505197A (en) | 1976-08-03 |
| GB1494802A (en) | 1977-12-14 |
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