CN108470763B - 包括掩埋层的半导体器件 - Google Patents

包括掩埋层的半导体器件 Download PDF

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CN108470763B
CN108470763B CN201810155053.9A CN201810155053A CN108470763B CN 108470763 B CN108470763 B CN 108470763B CN 201810155053 A CN201810155053 A CN 201810155053A CN 108470763 B CN108470763 B CN 108470763B
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semiconductor layer
semiconductor
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semiconductor substrate
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CN108470763A (zh
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A.迈泽
R.鲁道夫
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Infineon Technologies AG
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Abstract

公开了包括掩埋层的半导体器件。一种半导体器件包括第一导电类型的半导体衬底。第二导电类型的第一半导体层在半导体衬底上。第二导电类型的掩埋半导体层在第一半导体层上。第二导电类型的第二半导体层在掩埋半导体层上。沟槽延伸通过第二半导体层、掩埋半导体层以及第一半导体层的每个进入到半导体衬底中。绝缘结构衬垫沟槽的壁。进一步地，导电填充物在沟槽中，并且在沟槽的底部处电耦合到半导体衬底。

Description

包括掩埋层的半导体器件
背景技术
在各种各样的半导体功率应用中，例如在用于诸如受保护的低侧、高侧和桥配置或者完整的功率***集成电路（IC）的汽车和工业应用的功率驱动器中要求芯片诊断功能和保护电路。功率器件以及模拟和数字电路可以通过单片集成而被以所谓的“智能功率”或“BCD”（双极CMOS DMOS）技术组合在单个芯片中。智能功率技术可以是关于隔离技术（例如自隔离、结隔离或电介质隔离）而被分类的，或者是关于功率器件的类型（例如电流流动方向的指定）而被分类的。
要求相邻的电路元件（例如双极结型晶体管（BJT）或场效应晶体管（FET））的电隔离以允许电路元件中的每个工作在特定的工作电压范围中，由此避免例如在特定的工作电压范围内电路元件的电击穿的风险。因此，想要的是改进半导体器件的电隔离技术。
发明内容
本公开涉及一种半导体器件，其包括第一导电类型的半导体衬底。第二导电类型的第一半导体层在半导体衬底上。第二导电类型的掩埋半导体层在第一半导体层上。第二导电类型的第二半导体层在掩埋半导体层上。沟槽延伸通过第二半导体层、掩埋半导体层和第一半导体层中的每个进入到半导体衬底中。绝缘结构衬垫沟槽的壁。导电填充物在沟槽中并且在沟槽的底部处电耦合到半导体衬底。
本公开还涉及一种制造半导体器件的方法。方法包括在第一导电类型的半导体衬底上形成第二导电类型的第一半导体层。方法进一步包括将第二导电类型的掺杂剂注入到第一半导体层中。方法进一步包括在第一半导体层上形成第二导电类型的第二半导体层，其中注入的掺杂剂构成布置在第一和第二半导体层之间的掩埋半导体层。方法进一步包括形成延伸通过第二半导体层、通过掩埋半导体层、通过第一半导体层并进入到半导体衬底中的沟槽。方法进一步包括形成衬垫沟槽的壁的绝缘结构，以及在沟槽中形成导电填充物，导电填充物在沟槽的底部处电耦合到半导体衬底。
在阅读随后的详细描述以及在查看随附附图时本领域技术人员将认识到附加的特征和优点。
附图说明
随附附图被包括以提供本发明的进一步的理解并且随附附图被合并在本说明书中并构成本说明书的一部分。附图图示了实施例并且与描述一起用于解释本发明的原理。本发明的其它实施例和意图的优点将是容易领会的，因为它们通过参考随后的详细描述而变得被更好地理解。
图1是用于图示包括沟槽隔离和衬底接触结构的半导体器件的半导体主体部分100的示意性横截面视图。
图2A至图2E是用于图示沿着图1的线A-A'的各种掺杂浓度分布的线图。
图3是用于图示被通过沟槽隔离和衬底接触结构电绝缘的电路元件的半导体主体部分100 的示意性横截面视图。
图4A至图4F是用于图示用于制造包括沟槽隔离和衬底接触结构的半导体器件的处理流程的示意性横截面视图。
具体实施方式
在随后的详细描述中，参照形成在此的一部分并且其中通过说明的方式示出其中可以实践本公开的特定实施例的随附附图。要理解的是，可以利用其它的实施例并且可以在不脱离本发明的范围的情况下作出结构或逻辑上的改变。例如，针对一个实施例图示或描述的特征可以被使用在其它实施例上或者与其它实施例结合使用以产生又一进一步的实施例。意图的是本公开包括这样的修改和变化。使用不应当被解释为限制所附权利要求的范围的特定语言来描述各示例。附图不是按比例的并且仅用于说明性的目的。为了清楚，如果没有另外声明，则在不同的附图中相同的元件已经由的对应的标号指定。
术语“具有”，“包含”，“包括”和“包括有”等是开放的并且术语指示存在所声明的结构、元件或特征但是不排除存在附加的元件或特征。除非上下文另外清楚地指示，否则量词“一”、“一个”和指示词“该”意图包括复数以及单数。
术语“电连接”描述在电连接的元件之间的永久的低欧姆连接，例如在相关元件之间的直接接触或者经由金属和/或高掺杂的半导体的低欧姆连接。术语“电耦合”包括：适配于信号传输的一个或多个的（多个）中间元件可以存在于电耦合的元件之间，电耦合的元件例如为暂时地以第一状态提供低欧姆连接并且以第二状态提供高欧姆电退耦的元件。
各图通过挨着掺杂类型“n”或“p”指示“-”或“+”来图示相对掺杂浓度。例如，“n-”意味着与“n”掺杂区域的掺杂浓度相比更低的掺杂浓度，而“n+”掺杂区域与“n”掺杂区域相比具有更高的掺杂浓度。相同的相对掺杂浓度的掺杂区域不一定具有相同的绝对掺杂浓度。例如，两个不同的“n”掺杂区域可以具有相同或不同的绝对掺杂浓度。
如在本说明书中使用的术语“横向的”意图描述实质上平行于半导体衬底或主体的第一或主表面的定向。这例如可以是晶片或管芯的表面。
如在本说明书中使用的术语“竖向的”意图描述实质上被垂直于第一表面、即平行于半导体衬底或主体的第一表面的法线方向而布置的定向。
在本说明书中，半导体衬底或半导体主体的第二表面被认为要由下表面或背侧表面形成，而第一表面被认为要由半导体衬底的上表面、前表面或主表面形成。如在本说明书中使用的术语“在...之上”和“在...之下”因此描述结构特征相对于另一个结构特征的相对位置。
在本说明书中，p掺杂被提及为第一导电类型而n掺杂被提及为第二导电类型。替换地，可以利用相反的掺杂关系形成半导体器件，从而第一导电类型可以是n掺杂并且第二导电类型可以是p掺杂。
图1是用于图示一个或多个实施例的半导体主体部分100的示意性横截面视图。
n掺杂的第一半导体层104在p掺杂的半导体衬底102上。n+掺杂的掩埋半导体层106在第一半导体层上。n掺杂的第二半导体层108在n+掺杂的掩埋半导体层106上。沟槽110延伸通过n掺杂的第二半导体层108、n+掺杂的掩埋半导体层106和n掺杂的第一半导体层104中的每个进入到p掺杂的半导体衬底102中。绝缘结构112衬垫沟槽110的壁114。导电填充物116在沟槽中。导电填充物116在沟槽110的底部处电耦合到p掺杂的半导体衬底102。
p掺杂的半导体衬底102可以是p+掺杂的。p+掺杂的半导体衬底102的示例性掺杂浓度可以例如超过1018cm-3或5×1018cm-3，或1019cm-3。这例如可以允许抑制或劣化形成在n掺杂的第二半导体层108的与沟槽110的相对的侧壁邻接的n掺杂区段108a、108b之间的寄生衬底npn晶体管。高p掺杂的半导体衬底还可以促进半导体衬底和导电填充物116之间的电接触。通过示例的方式，高p掺杂的半导体衬底可以例如取代例如在沟槽110的底部处的高p掺杂的层或硅化物处的可选的接触促进层118。在一些其它的实施例中，p掺杂的半导体衬底102可以具有低的或中等的p掺杂，例如小于1016cm-3或小于1015cm-3或甚至小于1014cm-3的掺杂浓度。这可以允许通过将半导体衬底的低的或中等的p掺杂的部分利用于吸收反向阻断电压的一部分来增加衬底击穿电压的电压阻断能力。在一些其它的实施例中，p掺杂的半导体衬底可以包括高掺杂的、即p+掺杂的第一半导体衬底部分和在第一半导体衬底部分上的低地或中等地p掺杂的第二半导体衬底部分以用于将如上面描述那样的半导体衬底的高的和中等的/低的掺杂的益处进行组合。
在一个或多个实施例中，在n+掺杂的掩埋半导体层106的掺杂浓度分布的最大值与n掺杂的第一半导体层104和p掺杂的半导体衬底102之间的pn结120之间的竖向距离在10μm至30μm的范围内。这例如可以允许设置形成在n掺杂的第二半导体层108的n掺杂区段108a、108b中的电路元件的想要的衬底击穿电压。
在一个或多个实施例中，n掺杂的第一半导体层104的对于深度的（例如沿着竖向方向y的）掺杂浓度分布是原位掺杂浓度分布。除了可以类似于扩散加宽的类高斯深度分布或由扩散加宽的类高斯深度分布近似的特征扩散加宽离子注入掺杂分布，原位掺杂例如允许设置不同于扩散加宽的类高斯深度分布的多种多样的掺杂分布，诸如例如可能有益于设置形成在n掺杂的第二半导体层108 的n掺杂区段108a、108b中的电路元件的想要的衬底击穿电压的恒定的、阶梯状的、不断增加或不断降低的掺杂浓度分布。
在一个或多个实施例中，n掺杂的第一半导体层104的沿着n掺杂的第一半导体层104的从对于n+掺杂的掩埋半导体层106的过渡起到在n掺杂的第一半导体层104和p掺杂的半导体衬底102之间的pn结120的竖向延伸d1的掺杂剂量在从1011cm-2至1013cm-2的范围内。可以例如通过沿着竖向延伸对n型掺杂剂积分来确定掺杂剂量。在一个或多个实施例中，可以调整掺杂剂量以把在n掺杂的第一半导体层104和p掺杂的半导体衬底102之间的pn结120的击穿电压设置在从120V到200V的范围内。这可以允许应对牵涉48V板网的现代车辆中的增加的电功率需求。该电压水平要求功率半导体，例如与12V板网相比具有更高额定电压的电动涡轮加载器。
在一个或多个实施例中，n+掺杂的掩埋半导体层106的对于深度的掺杂浓度分布是由离子注入分布确定的。离子注入分布可以包括一个或多个重叠的和扩散加宽的类高斯深度分布（其包括峰值或最大掺杂浓度）。掩埋半导体层的最大掺杂浓度例如可以在从5×1018cm-3 到5×1020cm-3的范围内。在一个或多个实施例中，n+掺杂的掩埋半导体层包括多于一种的掺杂剂类别，例如磷掺杂剂和砷掺杂剂。当组合砷掺杂剂和磷掺杂剂时，例如，砷掺杂剂可以允许实现可能有益于横向电导率以及寄生衬底pnp晶体管的抑制或劣化的大的峰值浓度，而磷掺杂剂可以允许实现可能有益于增加n掺杂的第一半导体层104和p掺杂的半导体衬底102之间的pn结120的击穿电压的朝向p掺杂的半导体衬底102的更柔和的向外扩散分布。
在一个或多个实施例中，掺杂浓度分布包括在n+掺杂的掩埋半导体层106和n掺杂的第一半导体层104之间的边界处的转折点。在转折点与n掺杂的第一半导体层104和p掺杂的半导体衬底102之间的pn结120之间的第一半导体层的竖向延伸d1可以被设置在从5μm至25μm的范围内。这可以允许例如基于在从1014cm-3至5×1016cm-3、或者从5×1014cm-3至1×1016m-3的范围内的掺杂浓度而把在n掺杂的第一半导体层104和p掺杂的半导体衬底102之间的pn结120的击穿电压调整在如上面所指定的范围内。在n+掺杂的掩埋半导体层106与n掺杂的第一半导体层104之间的边界处的转折点可能例如是由n+掺杂的掩埋半导体层的掺杂剂的离子注入分布的掺杂浓度分布与原位n掺杂的第一半导体层104的掺杂浓度分布的掺杂剂的重叠引起的。
在一个或多个实施例中，p掺杂的半导体衬底102的p型掺杂剂的掺杂浓度分布沿着从p掺杂的半导体衬底102朝向n+掺杂的掩埋半导体层106的竖向方向降低。这可能是例如由在半导体器件的处理期间的热预算（例如由（多个）退火处理、（多个）氧化处理或（多个）层沉积处理引起的热预算）引起的。在掩埋半导体层的最大掺杂浓度的深度处p掺杂的半导体衬底102的掺杂剂的p型掺杂浓度可以小于1014cm-3。在一个或多个实施例中，p掺杂的半导体衬底102的掺杂剂的向外扩散可以甚至在n+掺杂的掩埋半导体层106的最大值之前——例如在n掺杂的第一半导体层104内——结束。提供n掺杂的第一半导体层104因此对在n+掺杂的掩埋半导体层106的掺杂浓度分布和p掺杂的半导体衬底102的掺杂浓度分布之间的抵消有影响。用于掩埋半导体层的掺杂剂进入到p掺杂的半导体衬底中的离子注入可能使n+掺杂的掩埋半导体层的峰值或最大掺杂浓度定位到半导体衬底的其中半导体衬底的p型掺杂被通过反掺杂转为掩埋层的n型掺杂的部分中，而用于掩埋半导体层的掺杂剂进入到第一半导体层中的离子注入则可能使n+掺杂的掩埋半导体层的峰值或最大掺杂浓度定位到第一半导体层的与来自半导体衬底的掺杂剂的扩散分布尾端端部间隔开或略微重叠的部分中。
在一个或多个实施例中，n掺杂的第一半导体层104的掺杂浓度沿着n掺杂的第一半导体层104的从对于n+掺杂的掩埋半导体层106的过渡起到在n掺杂的第一半导体层104和p掺杂的半导体衬底102之间的pn结120的竖向延伸d1的至少50％而恒定。在一个或多个实施例中，n掺杂的第一半导体层104的沿着竖向方向y的掺杂浓度分布包括至少两个平稳段，例如两个或三个平稳段。这可以允许进一步增加n掺杂的第一半导体层104和p掺杂的半导体衬底102之间的pn结120的击穿电压。在一个或多个实施例中，n掺杂的第一半导体层104的第一平稳段被设置为与n掺杂的第一半导体层104的第二平稳段相比更靠近p掺杂的半导体衬底102，并且第一平稳段处的掺杂浓度被设置为小于第二平稳段处的掺杂浓度。
在一个或多个实施例中，衬垫沟槽110的壁114的绝缘结构112可以包括一种或多种堆叠的绝缘材料，例如如作为热氧化物的SiO2那样的氧化物、通过化学气相沉积（CVD）处理沉积的氧化物（诸如低压（LP）CVD氧化物）的一种或组合、例如硼磷硅玻璃（BPSG）、磷硅酸盐玻璃（PSG）、硼硅酸盐玻璃（BSG）、（多种）氮化物、低电介质和高电介质、以及这些或其它绝缘材料的任何组合。
在一个或多个实施例中，半导体主体部分100 包括多个沟槽110和形成在n掺杂的第二半导体层108的不同区段中（例如在n掺杂的区段108a、108b中）的多个半导体电路元件。多个沟槽被配置为将第二半导体层的由多个沟槽中的一个分离开的相邻的区段电隔离，例如图1中图示的沟槽110将n掺杂的区段108a、108b电隔离。电路元件例如可以包括双极电路元件的组合，例如横向或竖向的npn和pnp晶体管，中等电压（MV）和高电压（HV）场效应晶体管（FET），诸如n沟道或p沟道金属氧化物半导体FET（MV和HV-MOSFET），互补MOS（CMOS）电路元件，例如n沟道和p沟道LV-MOSFET，以及双扩散MOS（DMOS）电路元件，例如横向和竖向的DMOS晶体管，二极管，无源组件，诸如电阻器，电容器。
图2A的示意性线图图示沿着图1的线 A-A'的掺杂浓度分布的一个示例。
n+掺杂的掩埋半导体层的n型掺杂剂的掺杂浓度分布c106在转折点K处转为n掺杂的第一半导体层104的n型掺杂剂的恒定的掺杂浓度分布c104。n掺杂的第一半导体层104沿着竖向方向y延伸直到n掺杂的第一半导体层104和p掺杂的半导体衬底102之间的pn结120。p掺杂的半导体衬底102的p型掺杂剂的掺杂浓度分布由c102表示。图2中图示的n掺杂的第一半导体层104的竖向延伸在层生长之后由于来自p掺杂的半导体衬底102的掺杂剂扩散进入到n掺杂的第一半导体层104中并且由于用于制备n+掺杂的掩埋半导体层106的掺杂剂的离子注入而比初始厚度更小。这可能导致n掺杂的第一半导体层104的收缩。在转折点K处，n+掺杂的掩埋半导体层106 的n型掺杂剂的数量从大于n掺杂的第一半导体层104的n型掺杂剂的数量转变成小于n掺杂的第一半导体层104的n型掺杂剂的数量，即在n+掺杂的掩埋半导体层中保持c106>c104，并且在n掺杂的第一半导体层104中保持c106<c104。类似地，在pn结120处，n掺杂的第一半导体层104的n型掺杂剂的数量从大于p掺杂的半导体衬底102的p型掺杂剂的数量转变成小于p掺杂的半导体衬底102的p型掺杂剂的数量，即在n掺杂的第一半导体层104中保持c104>c102，并且在p掺杂的半导体衬底102中保持c104<c102。
图2A中图示的线图是沿着图1的线A-A'的掺杂浓度分布的一个示例。在图2B至图2E中图示一些其它示例。
参照图2B中图示的线图，n掺杂的第一半导体层104的沿着竖向方向y的掺杂浓度分布c104包括至少两个平稳段P1、P2。n掺杂的第一半导体层104的第一平稳段P1被设置为与n掺杂的第一半导体层104的第二平稳段相比更靠近p掺杂的半导体衬底102，并且在第一平稳段P1处的掺杂浓度被设置为小于在第二平稳段P2处的掺杂浓度，由此允许进一步增加n掺杂的第一半导体层104和p掺杂的半导体衬底102之间的pn结120的击穿电压。
参照图2C中图示的线图，n掺杂的第一半导体层104的沿着竖向方向y的掺杂浓度分布c104从转折点K朝向pn结120不断降低，由此允许进一步增加n掺杂的第一半导体层104和p掺杂的半导体衬底102之间的pn结的击穿电压。
参照图2D中图示的线图，n+掺杂的掩埋半导体层106的掺杂浓度分布c106例如是两个扩散加宽分布的叠加，该两个扩散加宽分布例如为确定可能有益于横向电导率以及衬底pnp晶体管的抑制或劣化的峰值浓度的砷掺杂剂分布，以及确定分布的尾端的磷掺杂剂分布，该分布的尾端可以允许实现可能有益于增加n掺杂的第一半导体层104和p掺杂的半导体衬底102之间的pn结120的击穿电压的朝向p掺杂的半导体衬底102的更柔和的向外扩散分布。
参照图2E中图示的线图，p掺杂的半导体衬底的掺杂浓度分布c102可以包括高掺杂的即p+掺杂的第一半导体衬底部分S1和在第一半导体衬底部分上的低地或者中等地p掺杂的第二半导体衬底部分S2，以用于将如参照图1描述那样的半导体衬底102的高的和中等的/低的掺杂的益处进行组合。
进一步的示例可以基于例如在图2A到图2D中图示的任何的分布c106、c104、c102的组合。
图3中图示的半导体主体部分100包括多个沟槽110和形成在n掺杂的第二半导体层108的不同区段中的多个半导体电路元件，例如在第一n掺杂的区段108a中的包括主体（B）、源极（S）、漏极（D）和栅极（G）的LV n沟道MOSFET（LV NMOSFET），和在第二n掺杂的区段108b中的包括源极（S'）、漏极（D'）和栅极（G'）的高电压（HV）p沟道MOSFET（HV PMOSFET）。在第一和第二n掺杂的区段108a、108b中图示的电路元件是用于说明目的的示例性电路元件。可以例如包括其它的或附加的电路元件，诸如双极电路元件，例如横向或竖向的npn和pnp晶体管，中等电压（MV）和高电压（HV）场效应晶体管（FET），诸如n沟道和p沟道金属氧化物半导体FET（MV和HV-NMOSFET或PMOSFET），互补MOS（CMOS）电路元件，例如n沟道和p沟道LV-MOSFET以及双扩散MOS（DMOS）电路元件，例如横向和竖向的DMOS晶体管，二极管，无源组件，诸如电阻器、电容器。
图4A到图4F是用于图示制造半导体器件的方法的半导体主体部分200的示意性横截面视图 。
参照图4A的示意性横截面视图，例如n型的第二导电类型的第一半导体层204形成在例如p型的第一导电类型的半导体衬底202上。第一半导体层 204可以是通过层沉积处理（例如CVD，诸如在硅衬底上的硅的LPCVD或APCVD）形成的。第一半导体层204可以被原位掺杂。关于上面参照图1至图3描述的p掺杂的半导体衬底102的参数提供的细节（例如掺杂浓度值和分布），以及关于上面参照图1至图3描述的n掺杂的第一半导体层104的参数提供的细节同样对于图4A到图4F中图示的实施例适用。
参照图4B的示意性横截面视图，将第二导电类型的掺杂剂205注入到第一半导体层 204中。掺杂剂可以包括一种或多种掺杂剂类别，例如砷、磷、锑中的一种或多种。第二导电类型的掺杂剂可以通过无掩模离子注入处理注入到第一半导体层中。由此，用于制备掩埋半导体层的平版印刷掩模处理将变得不合时宜。在一些其它的实施例中，可以通过掩模离子注入处理来注入掺杂剂，由此实现掩埋半导体层的彼此间隔开的各区段。
参照图4C的示意性横截面视图，第二导电类型的第二半导体层 208形成在第一半导体层204上，其中注入的掺杂剂205构成布置在第一和第二半导体层204、208之间的掩埋半导体层206。可以通过热力加热来激活注入的掺杂剂205。在半导体器件的处理期间的热预算可以确定注入的掺杂剂205的竖向向外扩散分布，或者换句话说，确定掩埋半导体层的竖向延伸。关于上面参照图1至图3描述的n+掺杂的掩埋半导体层106和n掺杂的第二半导体层108的参数提供的细节（例如掺杂浓度值和分布）同样对于在图4A到图4F中图示的实施例适用。
参照图4D的示意性横截面视图，例如通过掩模蚀刻处理（诸如反应离子蚀刻（RIE））形成沟槽210，并且沟槽210延伸通过第二半导体层208、通过掩埋半导体层206、通过第一半导体层204并且进入到半导体衬底202中。
参照图4E的示意性横截面视图，绝缘结构212形成在沟槽210中并且衬垫沟槽210的壁214。绝缘结构212的形成可以包括层沉积处理和/或热氧化处理，随后有蚀刻处理，例如用于从第二半导体层208的顶部侧和从沟槽210的底部移除绝缘结构的材料的各向异性蚀刻处理，由此在沟槽210的底部处暴露出半导体衬底202。关于上面参照图1至图3描述的绝缘结构112的参数提供的细节（例如，材料和材料组合）同样对于图4A到图4F中图示的实施例适用。
参照图4F的示意性横截面视图，例如，导电填充物216被填充在沟槽中，并且例如通过与半导体衬底202的直接接触或经由如在图1中图示的接触促进层在沟槽的底部处电耦合到半导体衬底。导电填充物216的形成可以包括层沉积处理（例如高掺杂多晶硅的CVD和/或金属沉积）以及用于从第二半导体层208的顶部侧移除导电填充物216的材料的蚀刻处理。关于上面参照图1至图3描述的导电填充物116的参数提供的细节（例如材料和材料组合）同样对于图4A到图4F中图示的实施例适用。
例如，随后可以进行进一步的处理，例如用以将电路元件集成在第二半导体层208中的处理。
将领会的是，虽然方法1000被图示并在下面描述为一系列的动作或事件，但是不应在进行限制的意义上解释所图示的这样的动作或事件的顺序。例如，一些动作可能以不同的顺序发生和/或与除了在此图示和/或描述的那些以外的其它动作或事件同时地发生。此外，并非所有图示的动作都可能被要求以实现在此的公开的实施例的一个或多个方面。另外，可以在一个或多个分离的动作和/或阶段中执行在此描绘的动作中的一个或多个。
虽然已经在此图示并描述了特定的实施例，但是本领域普通技术人员将领会的是，在不脱离本发明的范围的情况下，各种各样的替换的和/或等同的实现可以代替所示出和描述的特定的实施例。本申请意图覆盖在此讨论的特定的实施例的任何适配或变化。因此，意图的是本发明仅受权利要求及其等同物限制。

Claims (24)

1.一种半导体器件，包括：
第一导电类型的半导体衬底；
在半导体衬底上的第二导电类型的第一半导体层；
在第一半导体层上的第二导电类型的掩埋半导体层；
在掩埋半导体层上的第二导电类型的第二半导体层；
延伸通过第二半导体层、掩埋半导体层以及第一半导体层的每个进入到半导体衬底中的沟槽；
铺衬沟槽的壁的绝缘结构；以及
在沟槽中的导电填充物，所述导电填充物在沟槽的底部处电耦合到半导体衬底，
其中半导体衬底的第一导电类型的掺杂剂的浓度分布沿着从半导体衬底到掩埋半导体层的竖向方向降低，并且在掩埋半导体层的最大掺杂浓度的深度处的半导体衬底的第一导电类型的掺杂剂的掺杂浓度小于1014cm-3。
2.根据权利要求1所述的半导体器件，其中掩埋半导体层对于深度的掺杂浓度分布是离子注入分布。
3.根据前述权利要求1-2中的任何一项所述的半导体器件，其中掩埋半导体层的掺杂浓度分布的最大值与在第一半导体层和半导体衬底之间的pn结之间的竖向距离在10μm至30μm的范围内。
4.根据前述权利要求1-2中的任何一项所述的半导体器件，其中掩埋半导体层的最大掺杂浓度在从5×1018cm-3到5×1020cm-3的范围内。
5.根据前述权利要求1-2中的任何一项所述的半导体器件，进一步包括在掩埋半导体层和第一半导体层之间的边界处的掺杂浓度分布中的转折点，其中在转折点与在第一半导体层和半导体衬底之间的pn结之间的第一半导体层的竖向延伸在从5μm至25μm的范围内。
6.根据前述权利要求1-2中的任何一项所述的半导体器件，其中掩埋半导体层包括磷掺杂剂和砷掺杂剂。
7.根据前述权利要求1-2中的任何一项所述的半导体器件，其中第一半导体层对于深度的掺杂浓度分布是原位掺杂浓度分布。
8.根据前述权利要求1-2中的任何一项所述的半导体器件，其中沿着从掩埋半导体层到在第一半导体层和半导体衬底之间的pn结的竖向延伸，第一半导体层具有在从1011cm-2至1013cm-2的范围内的掺杂剂量。
9.根据权利要求8所述的半导体器件，其中掺杂剂量被配置成将第一半导体层和半导体衬底之间的pn结的击穿电压设置在120V到200V的范围内。
10.根据前述权利要求1-2中的任何一项所述的半导体器件，其中第一半导体层的掺杂浓度沿着从掩埋半导体层到在第一半导体层和半导体衬底之间的pn结的竖向延伸的至少50％而恒定。
11.根据前述权利要求1-2中的任何一项所述的半导体器件，其中第一半导体层的掺杂浓度分布包括至少两个平稳段。
12.根据权利要求11所述的半导体器件，其中第一平稳段比第二平稳段更靠近半导体衬底，并且第一平稳段处的掺杂浓度比第二平稳段处的掺杂浓度小。
13.根据前述权利要求1-2中的任何一项所述的半导体器件，进一步包括多个沟槽和形成在第二半导体层的不同区段中的多个半导体电路元件，其中所述多个沟槽被配置为将第二半导体层的由所述多个沟槽中的一个分离开的相邻的区段电隔离。
14.根据权利要求13所述的半导体器件，其中电路元件包括双极电路元件、CMOS电路元件和DMOS电路元件的组合。
15.一种制造半导体器件的方法，包括：
在第一导电类型的半导体衬底上形成第二导电类型的第一半导体层；
将第二导电类型的掺杂剂注入到第一半导体层中；
在第一半导体层上形成第二导电类型的第二半导体层，其中所注入的掺杂剂构成布置在第一和第二半导体层之间的掩埋半导体层；
形成延伸通过第二半导体层、通过掩埋半导体层、通过第一半导体层并且进入到半导体衬底中的沟槽；
形成铺衬沟槽的壁的绝缘结构；以及
形成在沟槽的底部处电耦合到半导体衬底的、在沟槽中的导电填充物，
其中半导体衬底的第一导电类型的掺杂剂的浓度分布沿着从半导体衬底到掩埋半导体层的竖向方向降低，并且在掩埋半导体层的最大掺杂浓度的深度处的半导体衬底的第一导电类型的掺杂剂的掺杂浓度小于1014cm-3。
16.根据权利要求15所述的方法，其中第一半导体层的厚度被设置在从5μm至25μm的范围内。
17.根据权利要求15至16中的任何一项所述的方法，其中形成第一半导体层包括使第一半导体层原位掺杂有在从1011cm-2至1013cm-2的范围内的第二导电类型的掺杂剂。
18.根据权利要求15至16中的任何一项所述的方法，其中通过无掩模离子注入处理来将第二导电类型的掺杂剂注入到第一半导体层中。
19.根据权利要求15至16中的任何一项所述的方法，其中第一半导体层的掺杂浓度被设置成沿着第一半导体层的沿厚度方向的竖向延伸的至少50％而恒定。
20.根据权利要求15至16中的任何一项所述的方法，其中第一半导体层的掺杂浓度分布被设置成包括至少两个平稳段。
21.一种半导体器件，包括：
第一导电类型的半导体衬底；
在半导体衬底上的第二导电类型的第一半导体层；
在第一半导体层上的第二导电类型的掩埋半导体层；
在掩埋半导体层上的第二导电类型的第二半导体层；
延伸通过第二半导体层、掩埋半导体层以及第一半导体层的每个进入到半导体衬底中的沟槽；
铺衬沟槽的壁的绝缘结构；以及
在沟槽中的导电填充物，所述导电填充物在沟槽的底部处电耦合到半导体衬底，
其中沿着从掩埋半导体层到在第一半导体层和半导体衬底之间的pn结的竖向延伸，第一半导体层具有在从1011cm-2至1013cm-2的范围内的掺杂剂量，
其中掺杂剂量被配置成将第一半导体层和半导体衬底之间的pn结的击穿电压设置在120V到200V的范围内。
22.一种半导体器件，包括：
第一导电类型的半导体衬底；
在半导体衬底上的第二导电类型的第一半导体层；
在第一半导体层上的第二导电类型的掩埋半导体层；
在掩埋半导体层上的第二导电类型的第二半导体层；
延伸通过第二半导体层、掩埋半导体层以及第一半导体层的每个进入到半导体衬底中的沟槽；
铺衬沟槽的壁的绝缘结构；以及
在沟槽中的导电填充物，所述导电填充物在沟槽的底部处电耦合到半导体衬底，
其中第一半导体层的掺杂浓度分布包括至少两个平稳段。
23.根据权利要求22所述的半导体器件，其中第一平稳段比第二平稳段更靠近半导体衬底，并且第一平稳段处的掺杂浓度比第二平稳段处的掺杂浓度小。
24.一种制造半导体器件的方法，包括：
在第一导电类型的半导体衬底上形成第二导电类型的第一半导体层；
将第二导电类型的掺杂剂注入到第一半导体层中；
在第一半导体层上形成第二导电类型的第二半导体层，其中所注入的掺杂剂构成布置在第一和第二半导体层之间的掩埋半导体层；
形成延伸通过第二半导体层、通过掩埋半导体层、通过第一半导体层并且进入到半导体衬底中的沟槽；
形成铺衬沟槽的壁的绝缘结构；以及
形成在沟槽的底部处电耦合到半导体衬底的、在沟槽中的导电填充物，
其中第一半导体层的掺杂浓度分布被设置成包括至少两个平稳段。
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