CN114884313A - Self-adaptive dead time control circuit for current type DC-DC converter - Google Patents
Self-adaptive dead time control circuit for current type DC-DC converter Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention belongs to the technical field of integrated circuit design, and particularly relates to a self-adaptive dead time control circuit for a current type DC-DC converter; the circuit includes: the error operational amplifier output voltage sampling conversion circuit is used for sampling the DC-DC output voltage and the output current in real time; the dead time control circuit is used for realizing the control of the DC-DC output voltage and the output current on the dead time; the output end of the error operational amplifier output voltage sampling conversion circuit is connected with the input end of the dead time control circuit; according to the invention, through real-time sampling of the output voltage of the error operational amplifier, the dead time is dynamically changed along with the output voltage and the output current by the voltage sampling conversion circuit and the dead time control circuit, so that the optimal dead time control is achieved; compared with the traditional fixed dead time design, the method has higher intelligence, can cope with complex output environments under various conditions, and has wide application prospect.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design, and particularly relates to a self-adaptive dead time control circuit for a current type DC-DC converter.
Background
A DC-DC (direct current-direct current) converter is a voltage converter that converts a direct current input voltage into an effective output fixed direct current voltage. In the field of power management, a DC-DC converter realizes a direct current-to-direct current voltage conversion function, and in high-power voltage conversion, the DC-DC converter becomes a first choice of an engineering scheme by virtue of the advantages of high efficiency and high power density. In the traditional DC-DC structure, a MOS switch power tube and a freewheeling diode are adopted to realize power transmission, and in the freewheeling stage, the conduction loss is too large due to the conduction voltage of the freewheeling diode, so that the working efficiency is reduced. At present, the main flow structure is a synchronous DC-DC topological structure, and an MOS follow current power tube with low conduction voltage drop is adopted to replace a diode, so that the conduction loss is reduced, and the efficiency is improved.
In an ideal stable state, the power MOS switch power tube and the power MOS follow current power tube are switched on alternately, and the complementary square wave signal converted from the PWM signal controls the on and off of the two power tubes. In this state, the input to the ground is directly short-circuited to generate a large current, which may not only reduce the efficiency of DC-DC but also cause chip damage in severe cases. To avoid the similar situation, a certain time delay is artificially introduced between the turning off of one power tube and the turning on of the other power tube, and the time delay is called the "dead time" of the DC-DC converter. In the dead time, the follow current always flows through the parasitic diode of the follow current MOS tube, so that diode conduction loss also exists, and therefore if the dead time is designed to be too long, the conduction loss is increased, and if the dead time is too short, a conjugated conduction state also occurs.
The traditional dead-zone control of the DC-DC converter is a fixed dead zone, and in order to meet all possible application conditions of the DC-DC converter, such as changes of input and output voltages, changes of load current, and the like, the dead zone time is generally set to be relatively large, so that the efficiency cannot be optimized.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides an adaptive dead time control circuit for a current type DC-DC converter, which comprises: .
The error operational amplifier output voltage sampling conversion circuit is used for sampling the DC-DC output voltage and the output current in real time;
the dead time control circuit is used for realizing the control of the DC-DC output voltage and the output current on the dead time;
the output end of the error operational amplifier output voltage sampling conversion circuit is connected with the input end of the dead time control circuit.
Preferably, the error operational amplifier output voltage sampling conversion circuit includes: the transistor comprises a first PMOS (P-channel metal oxide semiconductor) transistor (PM1), a second PMOS transistor (PM2), a third PMOS transistor (PM3), a fourth PMOS transistor (PM4), a fifth PMOS transistor (PM5), a first NMOS (NM1), a second NMOS transistor (NM2), a third NMOS transistor (NM3), a first resistor (R1), a third PMOS transistor (PM3) and a first capacitor (C1);
the source electrode of the first PMOS tube (PM1) is connected with a power supply, the grid electrode of the first PMOS tube (PM1) is connected with a first bias voltage (REF1), and the drain electrode of the first PMOS tube (PM1) is connected with the source electrode of the second PMOS tube (PM2) and the source electrode of the third PMOS tube (PM 3);
the source electrode of the second PMOS tube (PM2) is connected with the source electrode of the third PMOS tube (PM3), the grid electrode of the second PMOS tube (PM2) is connected with the error operational amplifier output (EAOUT), and the drain electrode of the second PMOS tube (PM2) is connected with the drain electrode of the first NMOS tube (NM1), the grid electrode of the third NMOS tube (NM3) and the negative end of the first capacitor (C1);
the grid electrode of the third PMOS tube (PM3) is connected with the drain electrode of the fourth PMOS tube (PM4), the drain electrode of the third NMOS tube (NM3), the positive end of the first resistor (R1) and the positive end of the second resistor (R2);
the drain electrode of the first NMOS tube (NM1) is connected with the grid electrode of the third NMOS tube (NM3) and the negative end of the first capacitor (C1), the grid electrode of the first NMOS tube (NM1) is connected with the grid electrode of the second NMOS tube (NM2), the drain electrode of the second NMOS tube (NM2) and the drain electrode of the third PMOS tube (PM3), and the source electrode of the first NMOS tube (NM1) is connected with the ground;
the grid electrode of the second NMOS tube (NM2) is connected with the drain electrode of the second NMOS tube (NM2) and the drain electrode of the third PMOS tube (PM3), the drain electrode of the second NMOS tube (NM2) is connected with the grid electrode of the first NMOS tube (NM1) and the drain electrode of the third PMOS tube (PM3), and the source electrode of the second NMOS tube (NM2) is connected with the ground;
the source electrode of the third NMOS tube (NM3) is connected with the ground, and the drain electrode of the third NMOS tube (NM3) is connected with the drain electrode of the fourth PMOS tube (PM4), the positive end of the first resistor (R1) and the positive end of the second resistor (R2);
the gate of the fourth PMOS tube (PM4) is connected with the second bias voltage (REF2), the drain of the fourth PMOS tube (PM4) is connected with the positive end of the first resistor (R1) and the positive end of the second resistor (R2), and the source of the fourth PMOS tube (PM4) is connected with the drain of the fifth PMOS tube (PM5), the gate of the fifth PMOS tube (PM5), the gate of the sixth PMOS tube (PM6) and the gate of the seventh PMOS tube (PM 7);
the grid electrode of the fifth PMOS tube (PM5) is connected with the drain electrode of the fifth PMOS tube (PM5), and the source electrode of the fifth PMOS tube (PM5) is connected with a power supply;
the positive terminal of the first capacitor (C1) is connected to the negative terminal of the first resistor (R1), the positive terminal of the second resistor (R2) is connected to the positive terminal of the first resistor (R1), and the negative terminal of the second resistor (R2) is connected to ground.
Preferably, the dead time control circuit includes: a sixth PMOS (PM6), a seventh PMOS (PM7), a fourth NMOS (NM4), a fifth NMOS (NM5), a second capacitor (C2), a third capacitor (C3), a first comparator (COMP1) and a second comparator (COMP 2);
the grid electrode of the sixth PMOS tube (PM6) is connected with the grid electrode of the seventh PMOS tube (PM7), the source electrode of the sixth PMOS tube (PM6) is connected with a power supply, and the drain electrode of the sixth PMOS tube (PM6) is connected with the drain electrode of the fourth NMOS tube (NM4), the positive end of the second capacitor (C2) and the positive end of the first comparator (COMP 1);
the source electrode of the seventh PMOS tube (PM7) is connected with a power supply, and the drain electrode of the seventh PMOS tube (PM7) is connected with the drain electrode of the fifth NMOS tube (NM5), the positive end of the third capacitor (C3) and the positive end of the second comparator (COMP 2);
the grid electrode of the fourth NMOS tube (NM4) is connected with the first input signal (PWM-), the source electrode of the fourth NMOS tube (NM4) is connected with the ground, and the drain electrode of the fourth NMOS tube (NM4) is connected with the positive end of the second capacitor (C2) and the positive end of the first comparator (COMP 1);
the grid electrode of the fifth NMOS tube (NM5) is connected with the second input signal (PWM +), the source electrode of the fifth NMOS tube (NM5) is connected with the ground, and the drain electrode of the fifth NMOS tube (NM5) is connected with the positive end of the third capacitor (C3) and the positive end of the second comparator (COMP 2);
the negative end of the second capacitor (C2) and the negative end of the third capacitor (C3) are both connected with the ground, the positive end of the first comparator (COMP1) is connected with the positive end of the second capacitor (C2), the negative end of the first comparator (COMP1) is connected with the negative end of the second comparator (COMP2) and the reference voltage (REF3), and the positive end of the second comparator (COMP2) is connected with the positive end of the third capacitor (C3);
preferably, the output end of the error operational amplifier output voltage sampling conversion circuit is connected with the input end of the dead time control circuit, and the error operational amplifier output voltage sampling conversion circuit comprises: the grid electrode of a fifth PMOS (PM5) in the error operational amplifier output voltage sampling conversion circuit is connected with the grid electrode of a sixth PMOS (PM6) in the dead time control circuit and the grid electrode of a seventh PMOS (PM7) in the dead time control circuit, and the drain electrode of the fifth PMOS (PM5) is connected with the grid electrode of the sixth PMOS (PM6) and the grid electrode of the seventh PMOS (PM 7).
Preferably, the process of sampling the DC-DC output voltage and the output current in real time by the error operational amplifier output voltage sampling conversion circuit includes: sampling the grid electrode of the second PMOS tube (PM2) to obtain error operational amplifier output voltage and mirroring the error operational amplifier output voltage to the grid electrode of a third PMOS tube (PM 3); the grid voltage of the third PMOS pipe (PM3) is applied to a second resistor (R2), and the second resistor (R2) generates current; the current generated by the second resistor (R2) is mirrored into the dead time control circuit through a fifth PMOS transistor (PM 5).
Preferably, the dead time control circuit controls the dead time by: the first input signal (PWM-) and the second input signal (PWM +) are respectively input into a fourth NMOS transistor (NM4) and a fifth NMOS transistor (NM5) to control the second capacitor (C2) and the third capacitor (C3) to be rapidly turned off; the sixth PMOS tube (PM6) and the seventh PMOS tube (PM7) mirror the current of the fifth PMOS tube (PM5), and the current charges the second capacitor (C2) and the third capacitor (C3); the first comparator (COMP1) and the second comparator (COMP2) jointly control the second capacitor (C2) and the third capacitor (C3), and dead time control is achieved.
The invention has the beneficial effects that: the method comprises the steps of sampling the output voltage of the DC-DC error operational amplifier by utilizing the characteristic that the error operational amplifier (EA) is directly related to the output voltage and the output current when the current type DC-DC converter works in a closed loop mode, converting the sampled voltage into the current through a resistor, and realizing the real-time sampling of the DC-DC output voltage and the current by utilizing the change of the current; the dead time control circuit is utilized to control the rising time of the capacitor through the magnitude of the charging current, the rising edge delay is generated, then the rising edge delay is sent to the comparator and is compared with a fixed threshold to form the dead time of two paths of signals, and therefore the control of DC-DC output voltage and current on the dead time is realized; according to the invention, through real-time sampling of the output voltage of the error operational amplifier, the dead time is dynamically changed along with the output voltage and the output current by the voltage sampling conversion circuit and the dead time control circuit, so that the optimal dead time control is achieved, and the regulation range can be more flexibly controlled in a mode of externally connecting the voltage sampling conversion circuit with the resistor; compared with the traditional fixed dead time design, the method has higher intelligence, can cope with complex output environments under various conditions, and has wide application prospect.
Drawings
FIG. 1 is a schematic diagram of an adaptive dead-time control circuit for a current mode DC-DC converter according to the present invention;
fig. 2 is a graph of input voltage versus dead time for an adaptive dead time control circuit for a current mode DC-DC converter of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The present invention proposes an adaptive dead time control circuit for a current mode DC-DC converter, as shown in fig. 1, the circuit comprising:
the error operational amplifier output voltage sampling conversion circuit is used for sampling the DC-DC output voltage and the output current in real time;
the dead time control circuit is used for realizing the control of the DC-DC output voltage and the output current on the dead time;
the output end of the error operational amplifier output voltage sampling conversion circuit is connected with the input end of the dead time control circuit.
Preferably, the error operational amplifier output voltage sampling conversion circuit includes: a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a first resistor R1, a third PMOS transistor PM3 and a first capacitor C1;
the source electrode of the first PMOS tube PM1 is connected with a power supply, the gate electrode of the first PMOS tube PM1 is connected with a first bias voltage REF1, and the drain electrode of the first PMOS tube PM1 is connected with the source electrode of the second PMOS tube PM2 and the source electrode of the third PMOS tube PM 3;
the source electrode of the second PMOS tube PM2 is connected with the source electrode of the third PMOS tube PM3, the grid electrode of the second PMOS tube PM2 is connected with the error operational amplifier output EAOUT, and the drain electrode of the second PMOS tube PM2 is connected with the drain electrode of the first NMOS tube NM1, the grid electrode of the third NMOS tube NM3 and the negative end of the first capacitor C1;
the gate of the third PMOS transistor PM3 is connected to the drain of the fourth PMOS transistor PM4, the drain of the third NMOS transistor NM3, the positive terminal of the first resistor R1 and the positive terminal of the second resistor R2;
the drain of the first NMOS transistor NM1 is connected to the gate of the third NMOS transistor NM3 and the negative terminal of the first capacitor C1, the gate of the first NMOS transistor NM1 is connected to the gate of the second NMOS transistor NM2, the drain of the second NMOS transistor NM2 and the drain of the third PMOS transistor PM3, and the source of the first NMOS transistor NM1 is connected to ground;
the grid electrode of the second NMOS tube NM2 is connected with the drain electrode of the second NMOS tube NM2 and the drain electrode of the third PMOS tube PM3, the drain electrode of the second NMOS tube NM2 is connected with the grid electrode of the first NMOS tube NM1 and the drain electrode of the third PMOS tube PM3, and the source electrode of the second NMOS tube NM2 is connected with the ground;
the source of the third NMOS transistor NM3 is connected to ground, and the drain of the third NMOS transistor NM3 is connected to the drain of the fourth PMOS transistor PM4, the positive terminal of the first resistor R1, and the positive terminal of the second resistor R2;
the gate of the fourth PMOS tube PM4 is connected with a second bias voltage REF2, the drain of the fourth PMOS tube PM4 is connected with the positive end of the first resistor R1 and the positive end of the second resistor R2, and the source of the fourth PMOS tube PM4 is connected with the drain of the fifth PMOS tube PM5, the gate of the fifth PMOS tube PM5, the gate of the sixth PMOS tube PM6 and the gate of the seventh PMOS tube PM 7;
the grid electrode of the fifth PMOS pipe PM5 is connected with the drain electrode of the fifth PMOS pipe PM5, and the source electrode of the fifth PMOS pipe PM5 is connected with a power supply;
the positive terminal of the first capacitor C1 is connected to the negative terminal of the first resistor R1, the positive terminal of the second resistor R2 is connected to the positive terminal of the first resistor R1, and the negative terminal of the second resistor R2 is connected to ground.
Preferably, the dead time control circuit includes: a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a second capacitor C2, a third capacitor C3, a first comparator COMP1, and a second comparator COMP 2;
the grid electrode of the sixth PMOS tube PM6 is connected with the grid electrode of the seventh PMOS tube PM7, the source electrode of the sixth PMOS tube PM6 is connected with the power supply, and the drain electrode of the sixth PMOS tube PM6 is connected with the drain electrode of the fourth NMOS tube NM4, the positive end of the second capacitor C2 and the positive end of the first comparator COMP 1;
the source electrode of the seventh PMOS transistor PM7 is connected to the power supply, and the drain electrode of the seventh PMOS transistor PM7 is connected to the drain electrode of the fifth NMOS transistor NM5, the positive terminal of the third capacitor C3 and the positive terminal of the second comparator COMP 2;
the gate of the fourth NMOS transistor NM4 is connected to the first input signal PWM-, the source of the fourth NMOS transistor NM4 is connected to ground, and the drain of the fourth NMOS transistor NM4 is connected to the positive terminal of the second capacitor C2 and the positive terminal of the first comparator COMP 1;
the gate of the fifth NMOS transistor NM5 is connected to the second input signal PWM +, the source of the fifth NMOS transistor NM5 is connected to ground, and the drain of the fifth NMOS transistor NM5 is connected to the positive terminal of the third capacitor C3 and the positive terminal of the second comparator COMP 2;
the negative terminal of the second capacitor C2 and the negative terminal of the third capacitor C3 are both connected to ground, the positive terminal of the first comparator COMP1 is connected to the positive terminal of the second capacitor C2, the negative terminal of the first comparator COMP1 is connected to the negative terminal of the second comparator COMP2 and to the reference voltage REF3, and the positive terminal of the second comparator COMP2 is connected to the positive terminal of the third capacitor C3.
Preferably, the output end of the error operational amplifier output voltage sampling conversion circuit is connected with the input end of the dead time control circuit, and the error operational amplifier output voltage sampling conversion circuit comprises: the grid electrode of a fifth PMOS (PM5) in the error operational amplifier output voltage sampling conversion circuit is connected with the grid electrode of a sixth PMOS (PM6) in the dead time control circuit and the grid electrode of a seventh PMOS (PM7) in the dead time control circuit, and the drain electrode of the fifth PMOS (PM5) is connected with the grid electrode of the sixth PMOS (PM6) and the grid electrode of the seventh PMOS (PM 7).
The working principle of the adaptive dead time control circuit for the current mode DC-DC converter is as follows:
the process of sampling the DC-DC output voltage and the output current in real time by the error operational amplifier output voltage sampling conversion circuit comprises the following steps:
the error operational amplifier (EA) output voltage sampling conversion circuit adopts an operational amplifier following mode, the grid electrode of the second PMOS tube PM2 is sampled to obtain the error operational amplifier output voltage, the output voltage is mirrored to the grid electrode of the third PMOS tube PM3, namely:
V EAOUT ＝V SGPM2 ＝V SGPM3
wherein, V EAOUT Indicating the error operational amplifier output voltage, V SGPM2 Represents the gate voltage, V, of the second PMOS transistor PM2 SGPM3 Which represents the gate voltage of the third PMOS transistor PM 3.
The gate voltage of the third PMOS transistor PM3 is applied to the second resistor R2, the second resistor R2 generates a current, the current generated by the second resistor R2 is mirrored into the dead time control circuit through the fifth PMOS transistor PM5, and the magnitude of the current is:
wherein, I SENSE Indicating the value of the current generated by the second resistor R2.
The dead time control circuit controls the dead time as follows:
the dead time control is mainly realized by a second capacitor C2, a third capacitor C3, a first comparator COMP1 and a second comparator COMP2, and complementary PWM control signals, namely a first input signal PWM-and a second input signal (PWM +) pass through a fourth NMOSThe input of the NM4 and the NM5 of the fifth NMOS transistor further control the quick turn-off of the second capacitor C2 and the third capacitor C3, and the current I of the fifth PMOS transistor PM5 is mirrored by the sixth PMOS transistor (PM6) and the PM7 of the seventh PMOS transistor PM7 SENSE Through a current I SENSE The second capacitor C2 and the third capacitor C3 are charged, the rising time of the capacitors can be controlled, and the formula for calculating the rising time is as follows:
wherein, C represents the capacitance value of the capacitor for controlling the rising time of the capacitor, and Delta U represents the voltage required by the capacitor to rise to the flip threshold of the comparator at the later stage.
The capacitor generates rising edge delay, the first comparator (COMP1) and the second comparator (COMP2) jointly control the second capacitor (C2) and the third capacitor (C3), dead time of two signals is formed by comparing with a fixed threshold of the comparator, and therefore control of the DC-DC output voltage and the output current on the dead time is achieved, and the control dead time is as follows:
wherein, C 2/3 Representing the capacitance value of the second capacitance C2 or the third capacitance C3.
Because:
then:
from the above formula, when the error operational amplifier outputs the voltage V EAOUT When the load voltage and the load current change, the self-adaptive adjustment of the dead time can be timely realized, and optionally, the resistor R2 can also realize more flexible control of the adjustment range in an external mode.
As shown in figure 2 of the drawings, in which,error operational amplifier output voltage V EAOUT The higher the voltage, the greater the output dead time. In the actual use process, the voltage of the second capacitor C2, the voltage of the third capacitor C3 and the voltage of the reference voltage REF3 can be adjusted according to specific use conditions to adjust the dead time change range, and the second resistor R2 can also be externally arranged to further improve the flexibility of adjustment.
The method comprises the steps of sampling the output voltage of the DC-DC error operational amplifier by utilizing the characteristic that the error operational amplifier (EA) is directly related to the output voltage and the output current when the current type DC-DC converter works in a closed loop mode, converting the sampled voltage into the current through a resistor, and realizing the real-time sampling of the DC-DC output voltage and the current by utilizing the change of the current; the dead time control circuit is utilized to control the rising time of the capacitor through the magnitude of the charging current, the rising edge delay is generated, then the rising edge delay is sent to the comparator and is compared with a fixed threshold to form the dead time of two paths of signals, and therefore the control of DC-DC output voltage and current on the dead time is realized; according to the invention, through real-time sampling of the output voltage of the error operational amplifier, the dead time is dynamically changed along with the output voltage and the output current by the voltage sampling conversion circuit and the dead time control circuit, so that the optimal dead time control is achieved, and the regulation range can be more flexibly controlled in a mode of externally connecting the voltage sampling conversion circuit with the resistor; compared with the traditional fixed dead time design, the method has higher intelligence, can cope with complex output environments under various conditions, and has wide application prospect.
The above-mentioned embodiments, which further illustrate the objects, technical solutions and advantages of the present invention, should be understood that the above-mentioned embodiments are only preferred embodiments of the present invention, and should not be construed as limiting the present invention, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. An adaptive dead-time control circuit for a current mode DC-DC converter, comprising:
the error operational amplifier output voltage sampling conversion circuit is used for sampling the DC-DC output voltage and the output current in real time;
the dead time control circuit is used for realizing the control of the DC-DC output voltage and the output current on the dead time;
the output end of the error operational amplifier output voltage sampling conversion circuit is connected with the input end of the dead time control circuit.
2. The adaptive dead-time control circuit for a current mode DC-DC converter according to claim 1, wherein the error op-amp output voltage sampling conversion circuit comprises: the transistor comprises a first PMOS (P-channel metal oxide semiconductor) transistor (PM1), a second PMOS transistor (PM2), a third PMOS transistor (PM3), a fourth PMOS transistor (PM4), a fifth PMOS transistor (PM5), a first NMOS (NM1), a second NMOS transistor (NM2), a third NMOS transistor (NM3), a first resistor (R1), a third PMOS transistor (PM3) and a first capacitor (C1);
the source electrode of the first PMOS tube (PM1) is connected with a power supply, the grid electrode of the first PMOS tube (PM1) is connected with a first bias voltage (REF1), and the drain electrode of the first PMOS tube (PM1) is connected with the source electrode of the second PMOS tube (PM2) and the source electrode of the third PMOS tube (PM 3);
the source electrode of the second PMOS tube (PM2) is connected with the source electrode of the third PMOS tube (PM3), the grid electrode of the second PMOS tube (PM2) is connected with the error operational amplifier output (EAOUT), and the drain electrode of the second PMOS tube (PM2) is connected with the drain electrode of the first NMOS tube (NM1), the grid electrode of the third NMOS tube (NM3) and the negative end of the first capacitor (C1);
the gate of the third PMOS tube (PM3) is connected with the drain of the fourth PMOS tube (PM4), the drain of the third NMOS tube (NM3), the positive end of the first resistor (R1) and the positive end of the second resistor (R2);
the drain electrode of the first NMOS tube (NM1) is connected with the grid electrode of the third NMOS tube (NM3) and the negative end of the first capacitor (C1), the grid electrode of the first NMOS tube (NM1) is connected with the grid electrode of the second NMOS tube (NM2), the drain electrode of the second NMOS tube (NM2) and the drain electrode of the third PMOS tube (PM3), and the source electrode of the first NMOS tube (NM1) is connected with the ground;
the grid electrode of the second NMOS tube (NM2) is connected with the drain electrode of the second NMOS tube (NM2) and the drain electrode of the third PMOS tube (PM3), the drain electrode of the second NMOS tube (NM2) is connected with the grid electrode of the first NMOS tube (NM1) and the drain electrode of the third PMOS tube (PM3), and the source electrode of the second NMOS tube (NM2) is connected with the ground;
the source electrode of the third NMOS tube (NM3) is connected with the ground, and the drain electrode of the third NMOS tube (NM3) is connected with the drain electrode of the fourth PMOS tube (PM4), the positive end of the first resistor (R1) and the positive end of the second resistor (R2);
the gate of the fourth PMOS tube (PM4) is connected with the second bias voltage (REF2), the drain of the fourth PMOS tube (PM4) is connected with the positive end of the first resistor (R1) and the positive end of the second resistor (R2), and the source of the fourth PMOS tube (PM4) is connected with the drain of the fifth PMOS tube (PM5), the gate of the fifth PMOS tube (PM5), the gate of the sixth PMOS tube (PM6) and the gate of the seventh PMOS tube (PM 7);
the grid electrode of the fifth PMOS tube (PM5) is connected with the drain electrode of the fifth PMOS tube (PM5), and the source electrode of the fifth PMOS tube (PM5) is connected with a power supply;
the positive terminal of the first capacitor (C1) is connected to the negative terminal of the first resistor (R1), the positive terminal of the second resistor (R2) is connected to the positive terminal of the first resistor (R1), and the negative terminal of the second resistor (R2) is connected to ground.
3. An adaptive dead-time control circuit for a current mode DC-DC converter according to claim 1, wherein the dead-time control circuit comprises: a sixth PMOS (PM6), a seventh PMOS (PM7), a fourth NMOS (NM4), a fifth NMOS (NM5), a second capacitor (C2), a third capacitor (C3), a first comparator (COMP1) and a second comparator (COMP 2);
the grid electrode of the sixth PMOS tube (PM6) is connected with the grid electrode of the seventh PMOS tube (PM7), the source electrode of the sixth PMOS tube (PM6) is connected with a power supply, and the drain electrode of the sixth PMOS tube (PM6) is connected with the drain electrode of the fourth NMOS tube (NM4), the positive end of the second capacitor (C2) and the positive end of the first comparator (COMP 1);
the source electrode of the seventh PMOS tube (PM7) is connected with a power supply, and the drain electrode of the seventh PMOS tube (PM7) is connected with the drain electrode of the fifth NMOS tube (NM5), the positive end of the third capacitor (C3) and the positive end of the second comparator (COMP 2);
the grid electrode of the fourth NMOS tube (NM4) is connected with the first input signal (PWM-), the source electrode of the fourth NMOS tube (NM4) is connected with the ground, and the drain electrode of the fourth NMOS tube (NM4) is connected with the positive end of the second capacitor (C2) and the positive end of the first comparator (COMP 1);
the grid electrode of the fifth NMOS tube (NM5) is connected with the second input signal (PWM +), the source electrode of the fifth NMOS tube (NM5) is connected with the ground, and the drain electrode of the fifth NMOS tube (NM5) is connected with the positive end of the third capacitor (C3) and the positive end of the second comparator (COMP 2);
the negative terminal of the second capacitor (C2) and the negative terminal of the third capacitor (C3) are both connected to ground, the positive terminal of the first comparator (COMP1) is connected to the positive terminal of the second capacitor (C2), the negative terminal of the first comparator (COMP1) is connected to the negative terminal of the second comparator (COMP2) and the reference voltage (REF3), and the positive terminal of the second comparator (COMP2) is connected to the positive terminal of the third capacitor (C3).
4. The adaptive dead-time control circuit for a current mode DC-DC converter of claim 1, wherein the connecting of the output of the error op-amp output voltage sampling conversion circuit to the input of the dead-time control circuit comprises: the grid electrode of a fifth PMOS (PM5) in the error operational amplifier output voltage sampling conversion circuit is connected with the grid electrode of a sixth PMOS (PM6) in the dead time control circuit and the grid electrode of a seventh PMOS (PM7) in the dead time control circuit, and the drain electrode of the fifth PMOS (PM5) is connected with the grid electrode of the sixth PMOS (PM6) and the grid electrode of the seventh PMOS (PM 7).
5. The adaptive dead-time control circuit for a current-mode DC-DC converter according to claim 1, wherein the real-time sampling of the DC-DC output voltage and the output current by the error op-amp output voltage sampling conversion circuit comprises: sampling the grid electrode of the second PMOS tube (PM2) to obtain an error operational amplifier output voltage and mirroring the error operational amplifier output voltage to the grid electrode of the third PMOS tube (PM 3); the grid voltage of the third PMOS pipe (PM3) is applied to a second resistor (R2), and the second resistor (R2) generates current; the current generated by the second resistor (R2) is mirrored into the dead time control circuit through a fifth PMOS transistor (PM 5).
6. An adaptive dead-time control circuit for a current mode DC-DC converter according to claim 1, wherein the dead-time control circuit controls the dead-time by: the first input signal (PWM-) and the second input signal (PWM +) are respectively input into a fourth NMOS transistor (NM4) and a fifth NMOS transistor (NM5) to control the second capacitor (C2) and the third capacitor (C3) to be rapidly turned off; the sixth PMOS tube (PM6) and the seventh PMOS tube (PM7) mirror the current of the fifth PMOS tube (PM5), and the current charges the second capacitor (C2) and the third capacitor (C3); the first comparator (COMP1) and the second comparator (COMP2) jointly control the second capacitor (C2) and the third capacitor (C3), and dead time control is achieved.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210299302.8A CN114884313A (en) | 2022-03-25 | 2022-03-25 | Self-adaptive dead time control circuit for current type DC-DC converter |
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| CN202210299302.8A CN114884313A (en) | 2022-03-25 | 2022-03-25 | Self-adaptive dead time control circuit for current type DC-DC converter |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117424442A (en) * | 2023-12-06 | 2024-01-19 | 苏州炬仁半导体有限公司 | Dead time control circuit of driving signal |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117424442A (en) * | 2023-12-06 | 2024-01-19 | 苏州炬仁半导体有限公司 | Dead time control circuit of driving signal |
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