CN101976949B - Anti-interference rapid current sampling circuit based on difference structure - Google Patents

Abstract

The invention provides an anti-interference rapid current sampling circuit based on a difference structure, comprising a difference sampling main body circuit and a bias voltage generating circuit, wherein two different voltages are generated by the bias voltage for a common gate transistor in the sampling main body circuit, and the differentially sampled main body circuit output signal is an anti-interference sampling signal controlling the overall loop circuit or a current foldback circuit. By the invention, the interference resulted from a power supply or actions of a multipath DC-DC switch is effectively eliminated, and the anti-interference structure can be used for realizing precious control of the current foldback circuit, and can be used for realizing stable loop circuit control for a DC-DC loop circuit in a current mode.

Description

Quick anti-interference current sample circuit based on differential configuration

Technical field

The present invention relates to field of switch power; Be applied in the current foldback circuit and current-mode DC-DC converter current control loop of voltage-mode dc dc converter (DC-DC), particularly in the integrated circuit based on the quick anti-interference current sample circuit of differential configuration.

Background technology

Power management chip is an important component part of electronic product, and the power management chip quality has directly influenced the performance of electronic equipment.Along with the variation day by day of portable set functions such as mobile phone, PDA, digital camera and MP3 player, research and develop the main flow direction that high efficiency microminiaturized DC-DC converter becomes this field.Current sample not only can be used as in the middle of the voltage-mode DC-DC current foldback circuit, also is the important component part in the current-mode DC-DC loop, affects the performance of current-mode DC-DC.Also there is interference in the signal that on the one hand when other way switch pipe switch motions among the multichannel DC-DC (for example during the switching tube switch motion or) samples out when having interference on the power line; When interference volume is comparatively remarkable, can cause the mistake upset of comparator, and then make the chaotic thermal-shutdown circuit mistake that perhaps makes of control logic turn-off chip; On the other hand, the speed limit of sample circuit the DC-DC operating frequency.

Also fewer to the research of sampling anti-interference problem at present, though the traditional current sampling circuit that relates in the document 1 is simple in structure, speed ratio is very fast, and antijamming capability is poor, is not suitable for being applied among the multichannel DC-DC.

[document 1] Kuo-Hsing Cheng; Chia-Wei Su; Hsin-Hsin Ko.AHigh-Accuracy and High-Efficiency on-Chip Current Sensing for Current-ModeControl CMOS DC-DC Buck Converter; Electronics; Circuits and Systems, 2008.ICECS 2008.15th IEEE International Conference on

Summary of the invention

The present invention is in order to overcome the deficiency of above-mentioned prior art; A kind of quick, anti-interference current sample circuit based on differential configuration is provided, and this circuit structure is simple, and antijamming capability is strong; Sample rate is fast, and the variation of different temperatures, technology and supply voltage is less to its influence.

Technical scheme of the present invention is achieved in that

Quick anti-interference current sample circuit based on differential configuration; It is characterized in that: described sample circuit comprises difference sampling main body circuit and bias-voltage generating circuit; Produce two different voltages with different through bias-voltage generating circuit and to the common gate transistor in the sampling main body circuit grid voltage biasing is provided, the main body circuit output signal of difference sampling promptly is the anti-interference sampled signal that can be used to control whole loop or current foldback circuit.

Described difference sampling main body circuit connects the source electrode that PMOS manages Mp by the high potential of importing power supply, and the drain electrode of PMOS pipe Mp is connected the drain electrode of NMOS pipe Mn, and the source electrode that NMOS manages Mn is connected on the input power supply electronegative potential; Be connected filter circuit again on the tie point of PMOS pipe Mp and NMOS pipe Mn, filter circuit connects load resistance R; The source electrode of PMOS pipe Mp connects PMOS pipe M8; The grid of PMOS pipe M8 connects the power supply electronegative potential; The drain electrode of PMOS pipe M8 connects the source end of PMOS pipe M1; The drain electrode of PMOS pipe M1 connects the source electrode of PMOS pipe M3, and PMOS pipe M3 adopts the diode method of attachment, and grid is connected on the power supply electronegative potential with drain electrode jointly; The drain electrode of PMOS pipe Mp connects PMOS pipe M9; The grid of PMOS pipe M9 connects first control signal, and the drain electrode of M9 connects the source electrode of PMOS pipe M2, and the drain electrode of PMOS pipe M2 connects the source electrode of PMOS pipe M4; PMOS pipe M4 adopts the diode method of attachment, and grid is connected on the power supply electronegative potential with drain electrode jointly; The grid of PMOS pipe MP connects second control signal, and the grid of NMOS pipe Mn connects the 3rd control signal; The source electrode of PMOS pipe Mpx1 connects input power supply high potential, and the drain electrode of PMOS pipe Mpx1 connects the drain electrode of PMOS pipe M2, and the grid of PMOS pipe Mpx1 connects the 4th control signal, and the grid of PMOS pipe M1 and M2 is connected respectively to bias voltage V _B1And V _B2Sampled signal is from the source electrode difference output of PMOS pipe M3 and M4; Described filter circuit is to be connected and composed by inductance L and capacitor C, and wherein ESR is the equivalent series resistance of capacitor C.

Described bias-voltage generating circuit; Manage the high potential of the source electrode connection input power supply of M7 by the PMOS of series connection; Grid connects the power supply electronegative potential; Drain electrode connects the source end of PMOS pipe M5, and PMOS pipe M5 adopts the diode method of attachment, and the grid of the grid of PMOS pipe M5 and PMOS pipe M1 is connected to PMOS pipe M1 bias voltage V is provided _B1, between the tie point of the grid of PMOS pipe M5 and drain electrode and power supply electronegative potential, connect bias current sources I _B1The source electrode of the PMOS pipe M10 of series connection connects the high potential of input power supply; Grid connects the power supply electronegative potential; Drain electrode connects the source electrode of PMOS pipe M6, and PMOS pipe M6 adopts the diode method of attachment, and the grid of the grid of PMOS pipe M6 and PMOS pipe M2 is connected to PMOS pipe M2 bias voltage V is provided _B2, between the tie point of the grid of PMOS pipe M6 and drain electrode and power supply electronegative potential, connect bias current sources I _B2Between the source electrode of PMOS pipe M6 and power supply electronegative potential, be connected a current source I _C1

The sequential of described four control signals is different, and the rising edge of second control signal is slightly early than the 3rd control signal, and the trailing edge of second control signal is later than the 3rd control signal slightly; First control signal is the delayed somewhat signal of second control signal; The 4th control signal is the inversion signal of first control signal and has delay slightly.

The present invention compared with prior art provides an antijamming capability strong, and sample rate is fast, and current sampling circuit simple in structure, and the scheme of this circuit application in voltage-mode DC-DC current foldback circuit and current-mode DC-DC loop is provided.Anti-interference and fast characteristic the operating frequency of current-mode DC-DC can further be improved.

Description of drawings

Fig. 1 is the quick anti-interference current sample circuit schematic diagram based on differential configuration;

Fig. 2 is applied in the circuit theory diagrams in the overcurrent protection function for the quick anti-interference current sample circuit based on differential configuration;

Fig. 3 is applied in the circuit theory diagrams in the current-mode DC-DC loop for the quick anti-interference current sample circuit based on differential configuration;

Embodiment

Below in conjunction with accompanying drawing content of the present invention is described further.

With reference to shown in Figure 1; Based on the basic principle of the quick anti-interference current sample circuit of differential configuration is the control signal Q_p step-down at first of PMOS pipe Mp grid when beginning to sample; The control signal Q_p_2 of PMOS pipe M9 grid is slightly later to the Q_p step-down to avoid the sampled signal overshoot; The control signal Q_z of PMOS pipe Mpx grid uprises, and Mpx turn-offs; This moment, PMOS pipe M8 and M9 were in linear zone, and the resistance of M8 is R_M8, and the resistance of M9 is R_M9; Put aside that the channel length modulation effect can obtain following relation:

$\frac{1}{2}{K}_p^{\&prime;}{(W/L)}_2{(V_x-{\mathrm{<figure-callout\; id="2"\; label="I\; d"\; filenames="HDA0000029926880000012.png"\; state="\{\{state\}\}">I</figure-callout>}}_d\&times;R_{M8}-V_b-|V_{\mathrm{THP}}\left|\right)}^2=\frac{1}{2}{K}_p^{\&prime;}{(W/L)}_3{(V_M-|V_{\mathrm{THP}}\left|\right)}^2$

(1)

$\frac{1}{2}{K}_p^{\&prime;}{(W/L)}_2{(V_y-{\mathrm{<figure-callout\; id="2"\; label="I\; d"\; filenames="HDA0000029926880000012.png"\; state="\{\{state\}\}">I</figure-callout>}}_d\&times;R_{M9}-V_b-|V_{\mathrm{THP}}\left|\right)}^2=\frac{1}{2}{K}_p^{\&prime;}{(W/L)}_4{(V_N-|V_{\mathrm{THP}}\left|\right)}^2$

(2)

Because I _D1And I _D2Very little so can above equality be approximately:

$\frac{1}{2}{K}_p^{\&prime;}{(W/L)}_2{(V_x-V_b-|V_{\mathrm{THP}}\left|\right)}^2=\frac{1}{2}{K}_p^{\&prime;}{(W/L)}_3{(V_M-|V_{\mathrm{THP}}\left|\right)}^2$

(3)

$\frac{1}{2}{K}_p^{\&prime;}{(W/L)}_2{(V_y-V_b-|V_{\mathrm{THP}}\left|\right)}^2=\frac{1}{2}{K_p^{\&prime;}(W/L)}_4{(V_N-|V_{\mathrm{THP}}\left|\right)}^2$

(4)

Subtracted each other simultaneously at two ends after two formulas were opened radical sign respectively, and get

(W/L) ₁＝(W/L) ₂，(W/L) ₂＝(W/L) ₄

Can get:

V _M-V _N＝K(V _x-V _y)

(5)

Wherein $K=\sqrt{{(W/L)}_{\mathrm{1,2}}/{(W/L)}_{\mathrm{3,4}}}$

The source-drain electrode of Mp all exists bigger parasitic capacitance, and there is stray inductance in the power supply high potential to the line of Mp, and has resistance to exist on the line; When the Mp switch motion, the signal on the power supply high potential can present damped vibration, because the size of Mp is very big; So resistance value is less, leak two ends in the source of Mp and only have the pressure drop on the direct current, and the signal phase difference at two ends is very little; It is Δ V that the voltage difference at leakage two ends, Mp source is approximately a value of not having concussion, Δ V=R _Mp* I _L, this difference is through M1, and M2, M3, the amplification network that M4 forms be from M and 2 outputs of N, and the voltage difference that M point and N are ordered is K times of the voltage difference at leakage two ends, Mp source, and this difference promptly is the noiseless sampled signal of inductive current, that is:

V _M-V _N＝K×R _Mp×I _L

(6)

Only have two transistors at the Mp two ends to the path between the output two ends, this makes that the node on the signal path is less, and corresponding limit is less, and phase margin is sufficient; And RC is less so the speed of sampling is very fast.

With reference to shown in Figure 2, same section shown in Figure 1 is represented with prosign compare with Fig. 1, the source electrode of the PMOS pipe M7 of series connection connects the high potential of input power supply, grid connects the power supply electronegative potential, and drain electrode connects the source electrode of PMOS pipe M5, and M7 is operated in linear zone; M5 adopts the diode method of attachment, and the grid of M5 and the grid of M1 link together provides bias voltage V for M1 _B1Between the tie point of the grid of M5 and drain electrode and power supply electronegative potential, connect bias current sources I _B1The source electrode of the PMOS pipe M10 of series connection connects the high potential of input power supply, and grid connects the power supply electronegative potential, and drain electrode connects the source electrode of PMOS pipe M6, and M10 is operated in linear zone; M6 adopts the diode method of attachment, and the grid of M6 and the grid of M2 are connected to M2 bias voltage V is provided _B2, between the tie point of the grid of M6 and drain electrode and power supply electronegative potential, connect bias current sources I _B2, require I _B1=I _B2Connect the in-phase input end of comparator C P at the M point,, and between the source electrode of M6 and power supply electronegative potential, be connected a constant current source I who flows to the power supply electronegative potential at the inverting input of N point connection CP _C1, when connecting I _C1Afterwards, V _B1≠ V _B2, analogy basic structure can obtain following relation:

$\frac{1}{2}{K}_p^{\&prime;}{(W/L)}_2{(V_x-{\mathrm{<figure-callout\; id="2"\; label="I\; d"\; filenames="HDA0000029926880000012.png"\; state="\{\{state\}\}">I</figure-callout>}}_d\&times;R_{M8}-V_{b1}-|V_{\mathrm{THP}}\left|\right)}^2=\frac{1}{2}{K}_p^{\&prime;}{(W/L)}_2{(V_M-|V_{\mathrm{THP}}\left|\right)}^2$

(7)

$\frac{1}{2}{K}_p^{\&prime;}{(W/L)}_2{(V_y-{\mathrm{<figure-callout\; id="2"\; label="I\; d"\; filenames="HDA0000029926880000012.png"\; state="\{\{state\}\}">I</figure-callout>}}_d\&times;R_{M9}-V_{b2}-|V_{\mathrm{THP}}\left|\right)}^2=\frac{1}{2}{K}_p^{\&prime;}{(W/L)}_4{(V_N-|V_{\mathrm{THP}}\left|\right)}^2$

(8)

Used approximate and transistor proportionate relationship when utilizing derivation basic structure can obtain:

V _M-V _N＝K(V _x-V _y)-K(V _b1-V _b2)

(9)

V wherein _B2Compare V _B1Low I _C1* R _M10The inductive current increase reduces the voltage that N orders, and the voltage of ordering as N is low to moderate that comparator will overturn when identical with the M point, that is:

V _x-V _y＝V _b1-V _b2 (10)

I _L×R _Mp＝I _C1×R _M10

(11)

Through I is set _C1Value the threshold value of overcurrent protection is set, when inductive current increases to when making comparator toggles, thereby the comparator output control switch turn-offs the function that action realizes overcurrent protection.

With reference to shown in Figure 3, same section shown in Figure 2 is represented with prosign.Compare with Fig. 2; Fig. 3 is at the feedback resistance R1 and the R2 of the series connection of Vout place; Be connected node between R1 and the R2 as the inverting input of EA, Vref is as the in-phase input end of EA, and the output of EA is connected to the transducer v to i of a voltage to electric current after connecting compensating network; Slope compensation voltage Ramp Signal also receives a v to i simultaneously, and this two parts electric current sum provides I through current mirror _C2, I _C2Be connected the M6 source electrode between the power supply electronegative potential; The M point is connected comparator C MP with the N point; The output of CMP connects the input of pulse generation module Pulse Width Generator; The output of Pulse Width Generator is via the grid of buffer Buffer control Mp, Mn, Mpx, M9, the action that comparator toggles was exported control signal control switch pipe when the voltage of order as M point and N was equal, thereby the control action of the current loop of realization current-mode DC-DC.

Claims (2)

1. based on the quick anti-interference current sample circuit of differential configuration; It is characterized in that: described sample circuit comprises difference sampling main body circuit and bias-voltage generating circuit; Produce two different voltages with different through bias voltage and give the common gate transistor in the sampling main body circuit, the main body circuit output signal of difference sampling promptly is the anti-interference sampled signal of whole loop of control or current foldback circuit; Described difference sampling main body circuit connects the source electrode that PMOS manages Mp by the high potential of importing power supply, and the drain electrode of PMOS pipe Mp is connected the drain electrode of NMOS pipe Mn, and the source electrode that NMOS manages Mn is connected on the input power supply electronegative potential; Be connected filter circuit again on the tie point of PMOS pipe Mp and NMOS pipe Mn, filter circuit connects load resistance R; The source electrode of PMOS pipe Mp connects PMOS pipe M8; The grid of PMOS pipe M8 connects the power supply electronegative potential; The drain electrode of PMOS pipe M8 connects the source end of PMOS pipe M1; The drain electrode of PMOS pipe M1 connects the source electrode of PMOS pipe M3, and PMOS pipe M3 adopts the diode method of attachment, and grid is connected on the power supply electronegative potential with drain electrode jointly; The drain electrode of PMOS pipe Mp connects the source electrode of PMOS pipe M9; The grid of PMOS pipe M9 connects first control signal; The drain electrode of M9 connects the source electrode of PMOS pipe M2; The drain electrode of PMOS pipe M2 connects the source electrode of PMOS pipe M4, and PMOS pipe M4 adopts the diode method of attachment, and grid is connected on the power supply electronegative potential with drain electrode jointly; The grid of PMOS pipe Mp connects second control signal, and the grid of NMOS pipe Mn connects the 3rd control signal; The source electrode of PMOS pipe Mpx1 connects input power supply high potential, and the drain electrode of PMOS pipe Mpx1 connects the source electrode of PMOS pipe M2, and the grid of PMOS pipe Mpx1 connects the 4th control signal, and the grid of PMOS pipe M1 and M2 is connected respectively to bias voltage V _B1And V _B2Sampled signal is from the source electrode difference output of PMOS pipe M3 and M4; Described filter circuit is to be connected and composed by inductance L and capacitor C, and capacitor C has equivalent series resistance ESR; Described bias-voltage generating circuit; Manage the high potential of the source electrode connection input power supply of M7 by the PMOS of series connection; Grid connects the power supply electronegative potential; Drain electrode connects the source end of PMOS pipe M5, and PMOS pipe M5 adopts the diode method of attachment, and the grid of the grid of PMOS pipe M5 and PMOS pipe M1 is connected to PMOS pipe M1 bias voltage V is provided _B1, between the tie point of the grid of PMOS pipe M5 and drain electrode and power supply electronegative potential, connect bias current sources I _B1The source electrode of the PMOS pipe M10 of series connection connects the high potential of input power supply; Grid connects the power supply electronegative potential; Drain electrode connects the source electrode of PMOS pipe M6, and PMOS pipe M6 adopts the diode method of attachment, and the grid of the grid of PMOS pipe M6 and PMOS pipe M2 is connected to PMOS pipe M2 bias voltage V is provided _B2, between the tie point of the grid of PMOS pipe M6 and drain electrode and power supply electronegative potential, connect bias current sources I _B2Between the source electrode of PMOS pipe M6 and power supply electronegative potential, be connected a current source I _C1

2. the quick anti-interference current sample circuit based on differential configuration according to claim 1; It is characterized in that: the sequential of described four control signals is different; The rising edge of second control signal is slightly early than the 3rd control signal, and the trailing edge of second control signal is later than the 3rd control signal slightly; First control signal is the delayed somewhat signal of second control signal; The 4th control signal is the inversion signal of first control signal and has delay slightly.

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