CN116418206A - Adaptive foldback current limiting circuit adopting constant transconductance sampling with wide input range - Google Patents
Adaptive foldback current limiting circuit adopting constant transconductance sampling with wide input range Download PDFInfo
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- CN116418206A CN116418206A CN202111643081.3A CN202111643081A CN116418206A CN 116418206 A CN116418206 A CN 116418206A CN 202111643081 A CN202111643081 A CN 202111643081A CN 116418206 A CN116418206 A CN 116418206A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
By adopting the self-adaptive foldback current limiting circuit with the constant transconductance sampling in the wide input range, the additional current sampling node formed by the current step-by-step amplifying circuit and the constant transconductance amplifier in the wide input range is arranged on the basis of the current comparison node formed by connecting the constant current source and the lower tube current sampling end, so that foldback current Ifold can flow in the current comparison node, the peak value ics_peak=i_LIM-Ifold of the lower tube sampling current Ics allowed by the current comparison node is enabled, wherein the i_LIM is the constant current source current limiting current, and the risks of chip heating and switch tube breakdown under the condition of high output voltage are reduced.
Description
Technical Field
The invention relates to overload current limiting technology of a BOOST converter, in particular to a self-adaptive foldback current limiting circuit adopting constant transconductance sampling with a wide input range.
Background
Fig. 2 is a schematic diagram of a conventional current limiting circuit. As shown in fig. 2, the conventional current limiting circuit includes a voltage node B, a BOOST down-tube sampling current Ics (BOOST is a BOOST converter, down-tube or referred to as a down-switch tube), a constant current source i_lim, a first inverter INV1, and a second inverter INV2, the first path of the voltage node B is connected to a power supply voltage terminal through the down-tube current sampling circuit, the second path is grounded through the constant current source i_lim, the third path is connected to an input terminal of INV1, an output terminal of INV1 is connected to an input terminal of INV2, an output terminal of INV2 is connected to an overcurrent indication signal terminal (outputs an overcurrent indication signal LIM), ics flows into the voltage node B, and the i_lim flows out of the voltage node B. In fig. 2, a current comparator is formed by a constant current source i_lim and a sampling current Ics, and inverters INV1 and INV2 are used for shaping and converting a B-point analog signal into a digital signal at the LIM, where Ics is a BOOST down-tube sampling current, the constant current source i_lim is a fixed limiting value, and when the down-tube sampling current Ics increases to i_lim, the B-point becomes high, and an overcurrent indication signal LIM becomes high, which means that a BOOST inductance current peak reaches the limiting value. BOOST converters can have significant inductor current during overload applications and can burn out if the chip is not processed, thus introducing a current limiting circuit to limit the inductor current peak. The traditional current limiting circuit limits the peak inductance current to a fixed value when in overload, and is irrelevant to the degree of overload, so that the BOOST converter always works in the maximum peak current state when in overload, the heating phenomenon is serious, and the switching tube of the BOOST is in breakdown risk under the condition that the output voltage is still higher.
Disclosure of Invention
Aiming at the defects or shortcomings in the prior art, the invention provides a self-adaptive foldback current limiting circuit adopting constant transconductance sampling with a wide input range.
The technical scheme of the invention is as follows:
the self-adaptive foldback current limiting circuit adopting constant transconductance sampling with a wide input range is characterized by comprising a current comparison node formed by connecting a constant current source and a lower tube current sampling end, wherein the current comparison node is connected with an additional current sampling node through a current step-by-step amplifying circuit, and the additional current sampling node is respectively connected with a reference voltage end VREF and a feedback voltage end FB of the output voltage of the boost converter through a constant transconductance amplifier with a wide input range.
The down tube current sampling end is connected with a power supply voltage end VDD, down tube sampling current Ics flows into the current comparison node, constant current source current limiting current I_LIM flows out of the current comparison node, and the output end of the current step-by-step amplifying circuit forms foldback current Ifold when the constant transconductance amplifier with a wide input range detects overload of the boost converter and flows into the current comparison node, so that a peak value ics_peak=I_LIM-Ifold of the down tube sampling current Ics allowed by the current comparison node.
The current comparison node is connected with the input end of the first inverter, the output end of the first inverter is connected with the input end of the second inverter, and the output end of the second inverter is connected with the overcurrent indication signal end.
The current step-by-step amplifying circuit comprises a first PMOS tube and a second PMOS tube which are in common source and common gate, wherein a source electrode of the second PMOS tube is connected with a power supply voltage end VDD, a grid drain of the first PMOS tube is connected with a drain electrode of a second NMOS tube after being connected with each other, the second NMOS tube and the first NMOS tube are in common source and common gate, a source electrode of the second NMOS tube is grounded, and the grid drain of the first NMOS tube is connected with the additional current sampling node after being connected with each other.
The output end of the wide input range constant transconductance amplifier is connected with the additional current sampling node, the positive input end of the wide input range constant transconductance amplifier is connected with the reference voltage end VREF, and the negative input end of the wide input range constant transconductance amplifier is connected with the feedback voltage end FB.
The mirror ratio between the first PMOS tube and the second PMOS tube is 1:N, and the mirror ratio between the first NMOS tube and the second NMOS tube is 1:N, wherein N is an integer larger than 1.
Ifold=gm (VREF-FB) N, where gm is the transconductance value of the wide input range constant transconductance amplifier, the heavier the overload degree of the BOOST converter, the lower the feedback voltage FB of the output voltage of the BOOST converter, the greater the Ifold, and the smaller the corresponding BOOST peak current limiting value, so as to reduce the risk of heating and breakdown of the switching tube.
The invention has the following technical effects: the invention adopts the self-adaptive foldback current limiting circuit with constant transconductance sampling in a wide input range, and an additional current sampling node formed by a current step-by-step amplifying circuit and a constant transconductance amplifier in a wide input range is arranged on the basis of a current comparison node formed by connecting a constant current source and a lower tube current sampling end, so that foldback current Ifold is beneficial to flowing in the current comparison node, and the peak value ics_peak=i_LIM-Ifold of the lower tube sampling current Ics allowed by the current comparison node is enabled, wherein I_LIM is the constant current source current limiting current, thereby reducing the risk of the switch tube breakdown under the conditions of chip heating and high output voltage.
The invention can have the following characteristics: 1. the invention belongs to a self-adaptive current foldback current limiting circuit. 2. The current limiting circuit is improved on the basis of the traditional current limiting circuit, an output voltage detection circuit is introduced to reflect the overload light and heavy degree, the current limiting value is smaller as the overload degree is heavier, and the original fixed value current limiting method is changed into foldback current limiting. 3. The voltage difference between FB and VREF is sampled and amplified through a constant transconductance amplifier with a wide input range, so that the magnitude of the foldback current is controlled, and the limit value is linearly reduced along with the reduction of the output voltage.
Compared with the prior art, the invention has the advantages that: the circuit has simple structure, ingenious conception and stronger overload protection capability.
Drawings
Fig. 1 is a schematic diagram of the structural principle of an adaptive foldback current limiting circuit employing wide input range constant transconductance sampling in the practice of the present invention.
Fig. 2 is a schematic diagram of a conventional current limiting circuit.
The reference numerals are listed below: VDD-supply voltage terminal; LIM-overcurrent indication signal end; INV 1-a first inverter; INV 2-a second inverter; i_lim-current source (or constant current source); ics-down-tube current sampling terminal or BOOST down-tube sampling current (BOOST, down-tube or lower switching tube); MP 0-first PMOS tube; MP 2-second PMOS tube; MN 1-MN 2-a first NMOS tube to a second NMOS tube; ifold-foldback current; AMP-wide input range constant transconductance amplifier; FB-feedback voltage terminal; VREF-reference voltage terminal; a-an additional current sampling node; b-current comparison node; 1N-mirror ratio (N is an integer greater than 1).
Detailed Description
The invention will be described with reference to the accompanying drawings (fig. 1).
Fig. 1 is a schematic diagram of the structural principle of an adaptive foldback current limiting circuit employing wide input range constant transconductance sampling in the practice of the present invention. Referring to fig. 1, the adaptive foldback current limiting circuit adopting constant transconductance sampling with a wide input range comprises a current comparison node B formed by connecting a constant current source i_lim and a down tube current sampling end Ics, wherein the current comparison node B is connected with an additional current sampling node a through a current step-by-step amplifying circuit, and the additional current sampling node a is respectively connected with a reference voltage end VREF and a feedback voltage end FB of the output voltage of the boost converter through a constant transconductance amplifier AMP with the wide input range. The down-tube current sampling end Ics is connected with a power supply voltage end VDD, down-tube sampling current Ics flows into the current comparison node B, constant current source current limiting current i_lim flows out of the current comparison node B, and the output end of the current step-by-step amplifying circuit forms foldback current Ifold to flow into the current comparison node B when the boost converter overload is detected by the wide input range constant transconductance amplifier AMP, so that the peak value ics_peak=i_lim-Ifold of the down-tube sampling current Ics allowed by the current comparison node B.
The current comparison node B is connected with the input end of a first inverter INV1, the output end of the first inverter INV1 is connected with the input end of a second inverter INV2, and the output end of the second inverter INV2 is connected with an overcurrent indication signal end LIM. The current step-by-step amplifying circuit comprises a first PMOS tube MP0 and a second PMOS tube MP2 which are in common-source and common-gate connection, wherein a source electrode of the second PMOS tube MP2 is connected with a power supply voltage end VDD, a drain electrode of the second NMOS tube MN2 is connected after grid-drain interconnection of the first PMOS tube MP0, the second NMOS tube MN2 and the first NMOS tube MN1 are in common-source and common-gate connection, a source electrode of the second NMOS tube MN2 is grounded, and a grid-drain interconnection of the first NMOS tube MN1 is connected with the additional current sampling node A.
The output end of the wide input range constant transconductance amplifier AMP is connected with the additional current sampling node a, the positive input end (+) of the wide input range constant transconductance amplifier AMP is connected with the reference voltage end VREF, and the negative input end (-) of the wide input range constant transconductance amplifier AMP is connected with the feedback voltage end FB. The mirror ratio between the first PMOS transistor MP0 and the second PMOS transistor MP2 is 1:n, and the mirror ratio between the first NMOS transistor MN1 and the second NMOS transistor MN2 is 1:n, where n is an integer greater than 1. Ifold=gm (VREF-FB) N, where gm is the transconductance value of the wide input range constant transconductance amplifier AMP, the heavier the overload degree of the BOOST converter, the lower the feedback voltage FB of the output voltage of the BOOST converter, the greater the Ifold, and the smaller the corresponding BOOST peak current limiting value, so as to reduce the risk of heating and breakdown of the switching tube.
The invention provides a self-adaptive current foldback current limiting circuit, which is characterized in that as the overload degree becomes heavier, the corresponding current limiting value becomes smaller, so that the risk of breakdown of a switching tube under the conditions of chip heating and high output voltage is reduced.
As shown in fig. 1, fig. 1 shows an adaptive foldback current limiting circuit with a wide input range and constant transconductance sampling, and a transconductance sampling and current buffer amplifying circuit is added on the basis of a traditional current limiting circuit. FB is an output voltage sampling signal, VREF is a reference voltage, AMP is a constant transconductance amplifier with a wide input range (transconductance is a constant value in a very wide input voltage range), and all three form a transconductance sampling circuit together; and MN1, MN2, MP0, MP1 constitute a current buffer amplifying circuit.
The specific working principle is as follows: after the FB samples the BOOST output voltage, the transconductance amplifier AMP converts VREF and FB voltage difference into current, the current is sampled by the MN1 tube in a diode short circuit mode at the point A, and after the current buffer is amplified, foldback current Ifold is formed in the MP2 tube and used for modulating the magnitude of a current limiting value.
Under normal load conditions, the FB and VREF voltages are equal, the Ifold current is 0, and the limiting value I_LIM is not affected.
When overload occurs, the FB voltage becomes lower than VREF, at the moment, the AMP converts the voltage difference between the two voltages into current, and the current buffer formed by MN1, MN2, MP0 and MP2 is amplified by N times to form an Ifold current for reducing the current limiting value. The heavier the overload degree is, the lower the FB voltage is, the larger the Ifold current is, and the smaller the corresponding BOOST peak limiting value is, and the specific relation is as follows:
Ifold＝gm*(VREF-FB)*N*N
Ics_peak＝I_LIM-Ifold
therefore, peak current foldback occurs under the overload condition, and the BOOST converter is effectively protected.
The foldback current limiting circuit designed by the invention can effectively protect the BOOST high-voltage overload application condition, reduces the risks of heating and breakdown of a switching tube, and has the advantages of simple circuit structure, ingenious conception and stronger overload protection capability.
What is not described in detail in the present specification belongs to the prior art known to those skilled in the art. It is noted that the above description is helpful for a person skilled in the art to understand the present invention, but does not limit the scope of the present invention. Any and all such equivalent substitutions, modifications and/or deletions as may be made without departing from the spirit and scope of the invention.
Claims (7)
1. The self-adaptive foldback current limiting circuit adopting constant transconductance sampling with a wide input range is characterized by comprising a current comparison node formed by connecting a constant current source and a lower tube current sampling end, wherein the current comparison node is connected with an additional current sampling node through a current step-by-step amplifying circuit, and the additional current sampling node is respectively connected with a reference voltage end VREF and a feedback voltage end FB of the output voltage of the boost converter through a constant transconductance amplifier with a wide input range.
2. The adaptive foldback current limiting circuit with wide input range constant transconductance sampling according to claim 1, wherein the down-pipe current sampling end is connected to a power supply voltage end VDD, a down-pipe sampling current Ics flows into the current comparison node, a constant current source current limiting current i_lim flows out of the current comparison node, and an output end of the current step-up amplifying circuit forms foldback current Ifold to flow into the current comparison node when the wide input range constant transconductance amplifier detects overload of the boost converter, so that a peak value ics_peak=i_lim-Ifold of the down-pipe sampling current Ics allowed by the current comparison node.
3. The adaptive foldback current limiting circuit of claim 2, wherein the current comparison node is coupled to an input of a first inverter, an output of the first inverter is coupled to an input of a second inverter, and an output of the second inverter is coupled to an overcurrent indication signal.
4. The adaptive foldback current limiting circuit with wide input range constant transconductance sampling according to claim 3, wherein the current step-by-step amplifying circuit comprises a first PMOS transistor and a second PMOS transistor which are in common-source and common-gate, a source electrode of the second PMOS transistor is connected with a power supply voltage terminal VDD, a drain electrode of the second NMOS transistor is connected after grid-drain interconnection of the first PMOS transistor, the second NMOS transistor and the first NMOS transistor are in common-source and common-gate, a source electrode of the second NMOS transistor is grounded, and the gate-drain interconnection of the first NMOS transistor is connected with the additional current sampling node.
5. The adaptive foldback current limiter circuit of claim 4, wherein an output of the wide input range constant transconductance amplifier is coupled to the additional current sampling node, a positive input of the wide input range constant transconductance amplifier is coupled to the reference voltage terminal VREF, and a negative input of the wide input range constant transconductance amplifier is coupled to the feedback voltage terminal FB.
6. The adaptive foldback current limiting circuit of claim 5, wherein the mirror ratio between the first PMOS and the second PMOS is 1:n, the mirror ratio between the first NMOS and the second NMOS is 1:n, and n is an integer greater than 1.
7. The adaptive foldback current limiting circuit of claim 6, wherein ifeld = gm (VREF-FB) N, where gm is the transconductance value of the wide input range constant transconductance amplifier, the heavier the BOOST converter overload, the lower the feedback voltage FB of the BOOST converter output voltage, the greater the ifeld, and the smaller the corresponding BOOST peak current limiting value, thereby reducing the risk of heat generation and switching tube breakdown.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111643081.3A CN116418206A (en) | 2021-12-29 | 2021-12-29 | Adaptive foldback current limiting circuit adopting constant transconductance sampling with wide input range |
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| CN202111643081.3A CN116418206A (en) | 2021-12-29 | 2021-12-29 | Adaptive foldback current limiting circuit adopting constant transconductance sampling with wide input range |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117650761A (en) * | 2024-01-26 | 2024-03-05 | 杭州芯正微电子有限公司 | Inductance current sampling amplifying circuit with wide input voltage range |
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2021
- 2021-12-29 CN CN202111643081.3A patent/CN116418206A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117650761A (en) * | 2024-01-26 | 2024-03-05 | 杭州芯正微电子有限公司 | Inductance current sampling amplifying circuit with wide input voltage range |
| CN117650761B (en) * | 2024-01-26 | 2024-04-16 | 杭州芯正微电子有限公司 | Inductance current sampling amplifying circuit with wide input voltage range |
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