CN115208194A - Sectional type slope compensation circuit for voltage reduction type DCDC - Google Patents
Sectional type slope compensation circuit for voltage reduction type DCDC Download PDFInfo
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- CN115208194A CN115208194A CN202210635002.2A CN202210635002A CN115208194A CN 115208194 A CN115208194 A CN 115208194A CN 202210635002 A CN202210635002 A CN 202210635002A CN 115208194 A CN115208194 A CN 115208194A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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Abstract
The invention belongs to the technical field of integrated circuits, and particularly relates to a sectional type slope compensation circuit for a voltage reduction type DCDC, which comprises: the slope compensation capacitor control circuit and the slope compensation circuit; the slope compensation capacitor control circuit is connected with the slope compensation circuit to form a sectional slope compensation circuit, wherein the slope compensation capacitor control circuit is used for controlling the capacitance of the sectional slope compensation circuit, and the slope compensation circuit compensates the current signal according to the capacitance; according to the invention, the slope compensation capacitor is divided into 4 intervals, and the slope compensation amplitude is gradually increased in the process of gradually increasing the duty ratio, so that the load carrying capacity under the full duty ratio can be improved in a high-current DCDC and the problem of speed slowing caused by overcompensation under a low duty ratio can be solved.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a sectional type slope compensation circuit for a voltage reduction type DCDC.
Background
A switching power supply is a power supply that maintains a stable output voltage, and is generally composed of a Pulse Width Modulation (PWM) control IC and a MOSFET. With the development and innovation of power electronic technology, the technology of the switching power supply is continuously innovated. At present, a switching power supply can be divided into a BUCK (BUCK) converter, a BOOST (BOOST) converter and a BOOST-BOOST (BUCK-BOOST) converter according to a relation between an input voltage and an output voltage, wherein the BUCK converter can only realize a BUCK function, and the BOOST converter can only realize a BOOST function; in the field of power switches, the voltage model DCDC has a slow response speed, and the current model DCDC has a faster response speed than the voltage model, so the application range of the current model is more and more extensive. Because the current model DCDC has secondary slope oscillation when being applied to the field of power switches, the stability of a loop in a power circuit is reduced, and therefore a slope compensation circuit needs to be added into the power switch circuit; for a traditional slope compensation circuit, because the compensation amplitude is fixed, the compensation can be performed only for a current model under a scene, and for a low duty ratio model, an overcompensation condition occurs, so that the response speed and the loading capacity of a loop are reduced.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a segmented slope compensation circuit for a buck-type DCDC, which comprises: the slope compensation capacitor control circuit and the slope compensation circuit; the slope compensation capacitor control circuit is connected with the slope compensation circuit to form a sectional slope compensation circuit, wherein the slope compensation capacitor control circuit is used for controlling the capacitance of the sectional slope compensation circuit, and the slope compensation circuit compensates the current signal according to the capacitance;
the slope compensation capacitor control circuit comprises three comparators, seven NMOS tubes and four capacitors; the positive ends of the comparators A1, A2 and A3 are all connected with FB, and the negative ends are respectively connected with reference voltage input ends VREF1, VREF2 and VREF3; the output end of the comparator A1 is connected with the grid of the MN6, the output end of the comparator A2 is connected with the grid of the MN4, and the output end of the comparator A3 is connected with the grid of the NM 2; the source electrode of the MN1 is grounded, the grid electrode of the MN1 is connected with the input end of a reference clock signal CLK, and the drain electrodes of the MN1, the MN4 and the MN6 are respectively connected with the drain electrodes and the positive end of the capacitor C4; the source electrode of the MN2 is respectively connected with the drain electrode of the MN3 and the positive end of the capacitor C1; the grid electrode of the MN3 is connected with the input end of a clock signal CLK, and the source electrode is grounded; the negative end of the capacitor C1 is grounded; the source electrode of the MN4 is respectively connected with the drain electrode of the MN5 and the positive end of the capacitor C2; the grid electrode of the MN5 is connected with the input end of a clock signal CLK, and the source electrode is grounded; the negative end of the capacitor C2 is grounded; the source electrode of the MN6 is respectively connected with the drain electrode of the MN7 and the positive end of the capacitor C3; the grid electrode of the MN7 is connected with the input end of a clock signal CLK, and the source electrode is grounded; and the negative ends of the capacitors C3 and C4 are grounded to form a slope compensation capacitor control circuit.
Preferably, the slope compensation circuit includes: the power supply comprises four current sources, six PMOS tubes, nine PMOS tubes and a resistor; the positive end of the current source I1, the positive end of the current source IEA, the positive end of the current source I4, the source of the MP1, the source of the MP2, the source of the MP3 and the source of the MP4 are all connected with a power supply VDD; the negative end of the current source I1 is connected with the grid of the MP 5; the gate of MP1 is connected to the drain of MP1, the gate of MP2 and the gate of MP4 of MP3, respectively, and the drain of MP1 is connected to the positive terminal of the current source I2; the negative end of the current source I2 is grounded; the gate of the MP2 is connected with the gate of the MP1 and then connected with the positive end of the current source I2, the gate of the MP3 and the gate of the MP4, and the drain of the MP2 is respectively connected with the drain of the MN8, the gate of the MN8 and the gate of the MN 9; the drain electrode of the MP3 is connected with the drain electrode of the MN 9; the drain electrode of the MP4 is respectively connected with the source electrode of the MP5, the drain electrode of the MN12 and one end of the resistor R1; the negative ends of the current source IEA and the current source I4 are connected and then are respectively connected with the drain electrodes of the signal output end TO and the MN 16; the source of the MN8 is connected with the gate of the MN10, the drain of the MN10 and the gate of the MN11, and the gates are respectively connected with the drain of the MN8 and the gate of the MN 9; the source of MN9 is connected with the drain of MP5, the drain of MN11 and the gate of MN12 respectively; the source of the MN10 is grounded, and the grid of the MN10 is connected with the grid of the MN 11; the source electrode of the MN11 is grounded, and the drain electrode of the MN11 is connected with the source electrode of the MN9, the drain electrode of the MP5 and the grid electrode of the MN 12; the source electrode of the MP5 is respectively connected with the drain electrode of the MP4, the drain electrode of the MN12 and one end of the R1, and the drain electrode is respectively connected with the source electrode of the MN9, the drain electrode of the MN11 and the grid electrode of the MN 12; the source electrode of the MN12 is grounded, and the drain electrode of the MN12 is connected with the drain electrode of the MP4, the source electrode of the MP5 and one end of the resistor R1; the other end of the resistor R1 is respectively connected with the source electrode of the MP6, the drain electrode of the MN15, the grid electrode of the MN15 and the grid electrode of the MN 16; the gate of the MP6 is grounded, and the drain is connected with the drain of the MN 13; the grid electrode of the MN13 is connected with the input end of a reference clock signal CLK, and the source electrode is respectively connected with the grid electrode and the drain electrode of the MN 14; the gate of the MN14 is connected with the drain of the MN14, and the source of the MN14 is grounded; the grid electrode of the MN15 is connected with the grid electrode of the MN16, and the source electrode of the MN15 is grounded; the source electrode of the MN16 is grounded, and the drain electrode is respectively connected with the signal output end and the negative ends of the current source IEA and the current source I4 to form a slope compensation circuit.
Further, the connection of the slope compensation circuit and the slope compensation capacitance control circuit includes: the drain of the MN1, the drain of the MN2, the drain of the MN4, the drain of the MN6 and the positive end of the capacitor of the slope compensation capacitor control circuit are connected with the negative end of a current source I4 and the gate of the MP5 of the slope compensation circuit.
Preferably, the negative terminals of the comparators A1, A2 and A3 are reference level input terminals VREF1, VREF2 and VREF3; the input voltages of the reference level input terminals VREF1, VREF2, VREF3 are 0.2V, 0.4V, 0.6V, respectively.
Preferably, the frequency division ratio of the signal input at the input end of the reference clock signal CLK in the segmented slope compensation circuit is 2:4:8.
preferably, the process of controlling the capacitance size by the slope compensation capacitance control circuit includes: the voltage of the FB voltage input end can be controlled, when the voltage input by the FB voltage input end is 0-X1V, MN2, MN4 and MN6 are cut off, and the capacitance of the slope compensation capacitance control circuit is C4; when the voltage input by the FB voltage input end is X1-X2V, MN2 and MN4 are cut off, and the capacitance of the slope compensation capacitance control circuit is C3+ C4; when the voltage input by the FB voltage input end is X2-X3V and MN2 is cut off, the capacitance of the slope compensation capacitance control circuit is C2+ C3+ C4; when the voltage input by the FB voltage input end is more than X3V, the capacitance of the slope compensation capacitance control circuit is C1+ C2+ C3+ C4.
The invention has the beneficial effects that:
according to the sectional type slope compensation circuit, the slope compensation capacitor is divided into 4 sections, and the slope compensation amplitude is gradually increased in the process of gradually increasing the duty ratio, so that the load carrying capacity under the full duty ratio can be improved in a high-current DCDC, and the problem of speed slowing caused by overcompensation under the low duty ratio can be solved.
Drawings
FIG. 1 is a block diagram of a segmented slope compensation circuit for a buck DCDC according to the present invention;
wherein: a slope compensation capacitance control circuit is denoted by 101, and a slope compensation circuit is denoted by 102.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
The invention discloses a sectional type slope compensation circuit for a voltage reduction type DCDC (direct current-direct current), which adopts a novel framework, firstly outputs a sectional switching signal according to the level of a feedback voltage, and the slope compensation amplitude is gradually increased along with the gradual rise of the feedback voltage, so that the slope compensation of a full duty ratio can be realized under the condition of reducing the slope compensation current. For the high-current DCDC, the method can well solve the difficulty of slope compensation amplitude and has wide application range.
A segmented slope compensation circuit for buck DCDC, as shown in fig. 1, comprising: a slope compensation capacitance control circuit 101 and a slope compensation circuit 102; the slope compensation capacitance control circuit 101 is connected with the slope compensation circuit 102 to form a segmented slope compensation circuit, wherein the slope compensation capacitance control circuit 101 is used for controlling the capacitance of the segmented slope compensation circuit, and the slope compensation circuit 102 compensates the current signal according to the capacitance.
The slope compensation capacitance control circuit 101 comprises three comparators, seven NMOS transistors and four capacitors; the positive end of the comparator A1 is connected with FB, the negative end of the comparator A1 is connected with reference voltage VREF1, and the output end of the comparator A is connected with the gate of MN 6; the positive end of the comparator A2 is connected with FB, the negative end of the comparator A2 is connected with reference voltage VREF2, and the output end of the comparator A is connected with the gate of MN 4; the positive end of the comparator A3 is connected with FB, the negative end of the comparator A3 is connected with reference voltage VREF3, and the output end of the comparator A is connected with the gate of MN 2; the source electrode of the MN1 is grounded, the grid electrode of the MN1 is connected with a reference clock CLK, the drain electrode of the MN1 is connected with the negative end of a current source I1, the drain electrodes of the MN2, the MN4 and the MN6 are connected with the positive end of a C4 and the grid electrode of an MP 5; the source electrode of the MN2 is connected with the drain electrode of the MN3 and the positive end of the C1, the grid electrode of the MN2 is connected with the output end of the comparator A3, and the drain electrode of the MN2 is connected with the negative end of the current source I1, the drain electrodes of the MN1, the MN4 and the MN6 and the positive end of the C4 and the grid electrode of the MP 5; the source electrode of the MN3 is grounded, the grid electrode of the MN3 is connected with a reference clock CLK, and the drain electrode of the MN3 is connected with the source electrode of the MN2 and the positive end of the C1; the positive end of the C1 is connected with the source electrode of the MN2 and the drain electrode of the MN3, and the negative end is grounded; the source electrode of MN4 is connected with the drain electrode of MN5 and the positive end of C2, the grid electrode of the MN4 is connected with the output end of the comparator A2, and the drain electrode of the MN4 is connected with the negative end of the current source I1, the drain electrodes of MN1, MN2 and MN6, the positive end of C4 and the grid electrode of MP 5; the source electrode of the MN5 is grounded, the grid electrode of the MN5 is connected with a reference clock CLK, and the drain electrode of the MN5 is connected with the source electrode of the MN4 and the positive end of the C2; the positive end of the C2 is connected with the source electrode of the MN4 and the drain electrode of the MN5, and the negative end is grounded; the source electrode of the MN6 is connected with the drain electrode of the MN7 and the positive end of the C3, the grid electrode of the MN6 is connected with the output end of the comparator A1, and the drain electrode of the MN6 is connected with the negative end of the current source I1, the drain electrodes of the MN1, the MN2 and the MN4, the positive end of the C4 and the grid electrode of the MP 5; the source electrode of the MN7 is grounded, the grid electrode of the MN7 is connected with the reference clock CLK, and the drain electrode of the MN7 is connected with the source electrode of the MN6 and the positive end of the C3; the positive end of the C3 is connected with the source electrode of the MN6 and the drain electrode of the MN7, and the negative end is grounded; the positive end of the C4 is connected with the negative end of the current source I1, the drain electrodes of the MN1, the MN2, the MN4 and the MN6 and the gate electrode of the MP5, and the negative end is grounded.
The slope compensation circuit 102 includes: the power supply circuit comprises four current sources, six PMOS (P-channel metal oxide semiconductor) tubes, nine PMOS tubes and a resistor; the positive end of the current source I1 is connected with a power supply VDD, and the negative end is connected with the drains of MN1, MN2, MN4 and MN6, the C4 rectifying and MP5 grid; the source electrode of the MP1 is connected with a power supply VDD, the grid electrode of the MP1 is connected with the drain electrode of the MP1 and the grid electrodes of current sources I2, MP3 and MP4, and the drain electrode of the MP1 is connected with the positive electrode of the current source I2 and the grid electrodes of MP1, MP2, MP3 and MP 4; the positive end of the current source I2 is connected with the grids of the MP1, the MP2, the MP3 and the MP4 and the drain of the MP1, and the negative end is grounded; the source electrode of the MP2 is connected with a power supply VDD, the grid electrode of the MP2 is connected with the drain electrode of the MP1 and the positive terminal of a current source I2, the grid electrodes of the MP1, MP3 and MP4 are connected, and the drain electrode of the MP2 is connected with the drain electrode of the MN8 and the grid electrodes of the MN8 and MN 9; the source electrode of the MP3 is connected with a power supply VDD, the grid electrode of the MP3 is connected with the drain electrode of the MP1 and the positive end of a current source I2, the grid electrodes of the MP1, MP2 and MP4 are connected, and the drain electrode of the MP3 is connected with the drain electrode of the MN 9; the source electrode of the MP4 is connected with a power supply VDD, the grid electrode of the MP4 is connected with the drain electrode of the MP1 and the positive terminal of a current source I2, the grid electrodes of the MP1, the MP2 and the MP3, and the drain electrode of the MP5 is connected with the source electrode of the MP5, the drain electrode of the MN12 and the positive terminal of the R1; the source of MN8 is connected with the grids of MN10 and MN11 and the drain of MN10, the grid is connected with the grids of MP2 and MN8 and MN9, and the drain is connected with the drain of MP2 and the grids of MN8 and MN 9; the source electrode of MN9 is connected with the drain electrodes of MP5 and MN11 and the grid electrode of MN12, the grid electrode of MN8 is connected with the grid electrode of MP2 and MN8, and the drain electrode of MN 3; the source electrode of the MN10 is grounded, the grid electrode of the MN10 is connected with the grid electrode of the MN11, the source electrode of the MN8 and the drain electrode of the MN10, and the drain electrode of the MN10 is connected with the grid electrode of the MN11 and the source electrode of the MN 8; the source electrode of the MN11 is grounded, the grid electrode of the MN11 is connected with the grid electrode of the MN10, the drain electrode of the MN10 is connected with the source electrode of the MN8, and the drain electrode of the MN9 is connected with the source electrode of the MP5 and the drain electrode of the MN 12; the source electrode of the MP5 is connected with the positive terminals of the MP4 and the MN12, the drain electrodes of the MP5 and the MN1, the drain electrodes of the MN2, the MN4 and the MN6 are connected with the negative terminal of the current source I1, and the drain electrodes of the MP5 and the MN11 are connected with the grid electrodes of the MN 12; the source of the MN12 is grounded, the drains of the gates MP5 and MN11 are connected with the source of the MN9, and the drains are connected with the drain of the MP4, the source of the MP5 and the positive end of the R1; the positive end of the R1 is connected with the drain electrodes of the MP4 and the MN12 and the source electrode of the MP5, and the negative end of the R1 is connected with the source electrode of the MP6 and the drain electrode of the MN15, and the grid electrode of the MN16 and the drain electrode of the MN 15; the source electrode of the MP6 is connected with the negative end of the R1 and the drain electrodes of the MN15 and the MN16, the grid electrode is grounded, and the drain electrode is connected with the drain electrode of the MN 13; the source electrode of the MN13 is connected with the grid and the drain electrode of the MN14, the grid electrode of the MN13 is connected with the reference clock CLK, and the drain electrode of the MN13 is connected with the drain electrode of the MP 6; the source of the MN14 is grounded, the gate is connected with the source of the MN13 and the drain of the MN14, and the drain is connected with the source of the MN13 and the gate of the MN 14; the source of MN15 is grounded, the gate is connected with the gate of MN16 and the negative end of R1, the source of MP6 is connected with the drain of MN15, and the drain is connected with the gate of MN15, the gate of MN16, the negative end of R1 and the source of MP 6; the source electrode of the MN16 is grounded, the grid electrode of the MN16 is connected with the grid electrode of the MN15 and the negative terminal of the R1, the source electrode of the MP6 is connected with the drain electrode of the MN15, and the drain electrode of the MN16 is connected with the negative terminal of the current source IEA, the negative terminal of the current source I4 and the output; the positive end of the current source IEA is connected with the power supply VDD, and the negative end of the current source IEA is connected with the negative end of the current source I4 and the drain electrode and the output of the MN 16; the positive end of the current source I4 is connected with the power supply VDD, and the negative end is connected with the negative end of the current source IEA and the drain electrode of the MN16 and the output.
The negative terminals of the comparator A1, A2 and A3 are reference level input terminals VREF1, VREF2 and VREF3; the input voltages of the reference level input ends VREF1, VREF2 and VREF3 are 0.2V, 0.4V and 0.6V respectively; the frequency dividing ratio corresponding to the reference clock CLK is 2. The final slope compensation current is generated by MN16, and then the slope compensation current is subtracted from the current signal IEA converted from the output voltage of the error amplifier to obtain a final slope compensated signal, so as to implement the PWM comparison function.
The process of controlling the capacitance size by the slope compensation capacitance control circuit comprises the following steps: the voltage of the FB voltage input end can be controlled, when the voltage input by the FB voltage input end is 0V-0.2V, MN2, MN4 and MN6 are cut off, and the capacitance of the slope compensation capacitance control circuit is C4; when the voltage input by the FB voltage input end is 0.2V-0.4V, MN2 and MN4 are cut off, and the capacitance of the slope compensation capacitance control circuit is C3+ C4; when the voltage input by the FB voltage input end is 0.4V-0.6V and MN2 is cut off, the capacitance of the slope compensation capacitance control circuit is C2+ C3+ C4; when the voltage input by the FB voltage input end is more than 0.6V, the capacitance of the slope compensation capacitance control circuit is C1+ C2+ C3+ C4.
The CLK signal is a narrow pulse signal, when the CLK signal is high, the pull-down NMOS MN1, MN3, MN5 and MN7 are turned on to quickly pull down the positive terminal voltage of the C4, when the CLK signal is low, the pull-down NMOS MN1, MN3, MN5 and MN7 are turned off, the current source I1 slowly charges the capacitor, and therefore a cycle-by-cycle ramp voltage signal is generated at the positive terminal of the C4, and the magnitude of the ramp voltage signal is as follows:
wherein, I1 is a charging current, C is a capacitance of the time-division slope compensation circuit, and T is a low-level time of the clock CLK.
When the voltage of the positive terminal of C4 is high, MP5 is turned off, because (W/L) MP2 /(W/L) MP3 ＝2，(W/L) MN10 /(W/L) MN11 =1, so the MP5 drain is low at this time, and MN11 operates in the linear region. When the positive terminal voltage of the C4 is at a low level, the MP5 is turned on, the drain terminal voltage of the MP5 is at a high level, so that the MN11 operates in a saturation region, and the positive terminal voltage of the R1 is the positive terminal voltage of the C4 superimposed with a fixed level. The voltage across C4 is:
wherein, V 1 Representing a ramp voltage signal, V GSMP5 The gate-source voltage of the MP5 transistor is represented, I1 is the charging current, C is the capacitance of the time-division slope compensation circuit, T is the low level time of the clock CLK, I DMP5 Represents the leakage current, mu, of the MP5 transistor p Denotes hole mobility, C ox The unit area of gate oxide layer capacitance is shown, W represents the gate width of MP5 tube, L represents the gate length of MP5 tube, and V THMP5 Representing the threshold voltage of the MP5 tube.
The voltage of the positive end of the R1 is converted into a current signal through the resistor R1, and then the current signal is output through the MN16 tube mirror image to obtain the slope current. And then subtracting the output current signal of the error amplifier to obtain a final output signal. The final output ramp current value is:
wherein, I slope Represents the slope current value (W/L) MN16 Represents the width-length ratio of MN16 tube, (W/L) MN15 Representing the width-length ratio of MN15 tube, R1 representing the resistance value of the resistor, I DMP5 Represents the leakage current, mu, of the MP5 transistor p Denotes hole mobility, C ox The unit area of gate oxide layer capacitance is shown, W represents the gate width of MP5 tube, L represents the gate length of MP5 tube, and V THMP5 Represents the threshold voltage, I, of the MP5 tube DMN15 Represents the drain current, mu, of the MN5 tube n Denotes the electron mobility, V THMN15 Representing the threshold voltage of the MN15 tube.
The invention can satisfy the slope compensation values of different loads and different inductances DCDC by adjusting the mirror ratio of MN16 and MN15, thereby improving the application range.
The above-mentioned embodiments, which are further detailed for the purpose of illustrating the invention, technical solutions and advantages, should be understood that the above-mentioned embodiments are only preferred embodiments of the present invention, and should not be construed as limiting the present invention, and any modifications, equivalents, improvements, etc. made to the present invention within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A segmented slope compensation circuit for a buck DCDC, comprising: the slope compensation capacitor control circuit and the slope compensation circuit; the slope compensation capacitor control circuit is connected with the slope compensation circuit to form a sectional slope compensation circuit, wherein the slope compensation capacitor control circuit is used for controlling the capacitance of the sectional slope compensation circuit, and the slope compensation circuit compensates the current signal according to the capacitance;
the slope compensation capacitor control circuit comprises three comparators, seven NMOS tubes and four capacitors; the positive ends of the comparators A1, A2 and A3 are all connected with FB, and the negative ends are respectively connected with reference voltage input ends VREF1, VREF2 and VREF3; the output end of the comparator A1 is connected with the grid of the MN6, the output end of the comparator A2 is connected with the grid of the MN4, and the output end of the comparator A3 is connected with the grid of the NM 2; the source electrode of the MN1 is grounded, the grid electrode of the MN1 is connected with the input end of a reference clock signal CLK, and the drain electrodes of the MN1, the MN4 and the MN6 are respectively connected with the drain electrodes and the positive end of the capacitor C4; the source electrode of the MN2 is respectively connected with the drain electrode of the MN3 and the positive end of the capacitor C1; the grid electrode of the MN3 is connected with the input end of the clock signal CLK, and the source electrode is grounded; the negative end of the capacitor C1 is grounded; the source electrode of the MN4 is respectively connected with the drain electrode of the MN5 and the positive end of the capacitor C2; the grid electrode of the MN5 is connected with the input end of a clock signal CLK, and the source electrode is grounded; the negative end of the capacitor C2 is grounded; the source electrode of the MN6 is respectively connected with the drain electrode of the MN7 and the positive end of the capacitor C3; the grid electrode of the MN7 is connected with the input end of the clock signal CLK, and the source electrode is grounded; and the negative ends of the capacitors C3 and C4 are grounded to form a slope compensation capacitor control circuit.
2. The segmented slope compensation circuit for buck-type DCDC as claimed in claim 1, wherein the slope compensation circuit comprises: the power supply circuit comprises four current sources, six PMOS (P-channel metal oxide semiconductor) tubes, nine PMOS tubes and a resistor; the positive end of the current source I1, the positive end of the current source IEA, the positive end of the current source I4, the source of the MP1, the source of the MP2, the source of the MP3 and the source of the MP4 are all connected with a power supply VDD; the negative end of the current source I1 is connected with the grid of the MP 5; the gate of MP1 is connected to the drain of MP1, the gate of MP2 and the gate of MP4 of MP3, respectively, and the drain of MP1 is connected to the positive terminal of current source I2; the negative end of the current source I2 is grounded; the gate of the MP2 is connected with the gate of the MP1 and then connected with the positive end of the current source I2, the gate of the MP3 and the gate of the MP4, and the drain of the MP2 is respectively connected with the drain of the MN8, the gate of the MN8 and the gate of the MN 9; the drain electrode of the MP3 is connected with the drain electrode of the MN 9; the drain electrode of the MP4 is respectively connected with the source electrode of the MP5, the drain electrode of the MN12 and one end of the resistor R1; the negative ends of the current source IEA and the current source I4 are connected and then respectively connected with the drains of the signal output end TO and the MN 16; the source electrode of the MN8 is connected with the grid electrode of the MN10, the drain electrode of the MN10 and the grid electrode of the MN11, and the grid electrode of the MN8 is respectively connected with the drain electrode of the MN8 and the grid electrode of the MN 9; the source of MN9 is connected with the drain of MP5, the drain of MN11 and the gate of MN12 respectively; the source electrode of the MN10 is grounded, and the grid electrode of the MN10 is connected with the grid electrode of the MN 11; the source electrode of the MN11 is grounded, and the drain electrode of the MN11 is connected with the source electrode of the MN9, the drain electrode of the MP5 and the grid electrode of the MN 12; the source electrode of the MP5 is respectively connected with the drain electrode of the MP4, the drain electrode of the MN12 and one end of the R1, and the drain electrode is respectively connected with the source electrode of the MN9, the drain electrode of the MN11 and the grid electrode of the MN 12; the source electrode of the MN12 is grounded, and the drain electrode of the MN12 is connected with the drain electrode of the MP4, the source electrode of the MP5 and one end of the resistor R1; the other end of the resistor R1 is respectively connected with the source electrode of the MP6, the drain electrode of the MN15, the grid electrode of the MN15 and the grid electrode of the MN 16; the gate of the MP6 is grounded, and the drain is connected with the drain of the MN 13; the gate of the MN13 is connected with the input end of a reference clock signal CLK, and the source is respectively connected with the gate and the drain of the MN 14; the gate of the MN14 is connected with the drain of the MN14, and the source of the MN14 is grounded; the grid electrode of the MN15 is connected with the grid electrode of the MN16, and the source electrode of the MN15 is grounded; the source electrode of the MN16 is grounded, and the drain electrode is respectively connected with the signal output end and the negative ends of the current source IEA and the current source I4 to form a slope compensation circuit.
3. The segmented slope compensation circuit for buck-type DCDC of claim 2, wherein the connection of the slope compensation circuit to the slope compensation capacitance control circuit comprises: the drain of the MN1, the drain of the MN2, the drain of the MN4, the drain of the MN6 and the positive end of the capacitor of the slope compensation capacitor control circuit are connected with the negative end of a current source I4 and the gate of the MP5 of the slope compensation circuit.
4. The segmented slope compensation circuit for buck-type DCDC as claimed in claim 1, wherein the negative terminals of comparators A1, A2, A3 are reference level inputs VREF1, VREF2, VREF3; the input voltages of the reference level input terminals VREF1, VREF2, VREF3 are 0.2V, 0.4V, 0.6V, respectively.
5. The segmented slope compensation circuit for buck-type DCDC as claimed in claim 1, wherein the signal division ratio input to the input terminal of the reference clock signal CLK in the segmented slope compensation circuit is 2:4:8.
6. the segmented slope compensation circuit for buck-type DCDC as claimed in claim 1, wherein the process of the slope compensation capacitance control circuit controlling the capacitance magnitude comprises: the voltage of the FB voltage input end can be controlled, when the voltage input by the FB voltage input end is 0V-0.2V, MN2, MN4 and MN6 are cut off, and the capacitance of the slope compensation capacitance control circuit is C4; when the voltage input by the FB voltage input end is 0.2V-0.4V, MN2 and MN4 are cut off, and the capacitance of the slope compensation capacitance control circuit is C3+ C4; when the voltage input by the FB voltage input end is 0.4V-0.6V and MN2 is cut off, the capacitance of the slope compensation capacitance control circuit is C2+ C3+ C4; when the voltage input by the FB voltage input end is more than 0.6V, the capacitance of the slope compensation capacitance control circuit is C1+ C2+ C3+ C4.
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| CN202210635002.2A CN115208194A (en) | 2022-06-07 | 2022-06-07 | Sectional type slope compensation circuit for voltage reduction type DCDC |
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| CN202210635002.2A CN115208194A (en) | 2022-06-07 | 2022-06-07 | Sectional type slope compensation circuit for voltage reduction type DCDC |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116032256A (en) * | 2023-01-10 | 2023-04-28 | 灿芯半导体(天津)有限公司 | Triangular wave generating circuit for eliminating direct current offset of positive and negative ends of differential signal |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116032256A (en) * | 2023-01-10 | 2023-04-28 | 灿芯半导体(天津)有限公司 | Triangular wave generating circuit for eliminating direct current offset of positive and negative ends of differential signal |
| CN116032256B (en) * | 2023-01-10 | 2023-09-26 | 灿芯半导体(天津)有限公司 | Triangular wave generating circuit for eliminating direct current offset of positive and negative ends of differential signal |
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