CN112080218A

CN112080218A - Dicing tape and dicing die-bonding film

Info

Publication number: CN112080218A
Application number: CN202010496602.6A
Authority: CN
Inventors: 木村雄大; 每川英利; 武田公平; 植野大树; 中浦宏
Original assignee: Nitto Denko Corp
Current assignee: Nitto Denko Corp
Priority date: 2019-06-13
Filing date: 2020-06-03
Publication date: 2020-12-15
Also published as: TW202123325A; JP2020205415A; KR20200143259A

Abstract

The present invention relates to a dicing tape and a dicing die-bonding film. The dicing tape of the present invention has an adhesive layer laminated on a base material layer, and the dicing tape has a tensile storage modulus at-5 ℃ of 100MPa or more.

Description

Dicing tape and dicing die-bonding film

Cross reference to related applications

The present application claims priority from Japanese patent application No. 2019-110200, which is incorporated by reference into the description of the present specification.

Technical Field

The present invention relates to a dicing tape and a dicing die-bonding film.

Background

Conventionally, in the manufacture of semiconductor devices, dicing tapes and dicing die-bonding films have been used for obtaining semiconductor chips for die bonding.

The dicing tape is configured by laminating an adhesive layer on a base material layer, and the dicing die-bonding film is configured by laminating a die-bonding layer on the adhesive layer of the dicing tape so as to be peelable.

As a method for obtaining a semiconductor chip (Die) for Die bonding by using the above-described dicing Die-bonding film, a method having the following steps is known: a half-cut step of forming a groove in the semiconductor wafer and grinding the semiconductor wafer to reduce the thickness thereof in order to process the semiconductor wafer into chips (Die) by a dicing process; a back grinding step of grinding the semiconductor wafer after the half-cut step to reduce the thickness; a mounting step of attaching one surface (for example, a surface on the opposite side of the circuit surface) of the semiconductor wafer after the back grinding step to the die bonding layer to fix the semiconductor wafer to the dicing tape; an expanding step of expanding the interval between the semiconductor chips subjected to the half-cut processing; a notch maintaining step of maintaining the interval between the semiconductor chips; a pickup step of peeling off the chip bonding layer and the adhesive layer to take out the semiconductor chip in a state where the chip bonding layer is attached; and a die bonding step of bonding the semiconductor chip with the die bonding layer attached thereto to an adherend (for example, a mounting substrate).

In the notch maintaining step, the distance (notch) between the adjacent semiconductor chips to be cut is maintained by thermally shrinking the dicing tape by directing hot air (for example, 100 to 130 ℃) to the dicing tape and then cooling and solidifying the dicing tape.

In the expanding step, the die bonding layer is cut to a size corresponding to the size of the plurality of singulated semiconductor chips.

In a method for obtaining a semiconductor chip for die bonding using the dicing die bonding film as described above, patent document 1 discloses: by using a dicing tape having specific physical properties (a dicing tape having an initial elastic modulus at-10 ℃ of 200MPa or more and 380MPa or less and a Tan (loss modulus/storage modulus) at-10 ℃ of 0.080 or more and 0.3 or less) and performing the expanding step at a low temperature of-15 to 5 ℃, the cuttability (e.g., ease of cutting, uniform cuttability, etc.) from the semiconductor wafer to a plurality of semiconductor chips in the expanding step can be improved.

Documents of the prior art

Patent document

Patent document 1: japanese laid-open patent publication (JP 2015-185591)

Disclosure of Invention

Problems to be solved by the invention

As described in patent document 1, the cuttability of the semiconductor wafer is improved by using a dicing tape having specific physical properties and performing the expanding step under the low temperature condition, but when the semiconductor wafer is cut into a plurality of semiconductor chips by expanding under the low temperature condition using the dicing tape and the dicing die-bonding film, the cuttability of the semiconductor wafer needs to be further improved.

In particular, when a semiconductor wafer is cut into a plurality of small semiconductor chips (for example, semiconductor chips having a size of 12mm in length, 4mm in width, and 0.055mm in thickness), it is necessary to further improve the cutting performance of the semiconductor wafer.

Accordingly, an object of the present invention is to provide a dicing tape and a dicing die-bonding film that can further improve the cutting performance from a semiconductor wafer to a plurality of semiconductor chips by spreading under low temperature conditions.

Means for solving the problems

The dicing tape of the present invention has an adhesive layer laminated on a base material layer,

the cutting belt has a tensile storage modulus at-5 ℃ of 100MPa or more.

In the above dicing tape, preferably:

a 30% tensile stress at-5 ℃ of 5.5N/10mm or more.

In the above dicing tape, preferably:

the 30% tensile stress at room temperature is 3.2N/10mm or more.

In the above dicing tape, preferably:

a ratio of 30% tensile stress at-5 ℃ to 30% tensile stress at room temperature of 1.7 or more.

The dicing die-bonding film of the present invention comprises:

a dicing tape having a substrate layer and an adhesive layer laminated thereon, and

a die bonding layer laminated on the adhesive layer of the dicing tape,

the cut die-bonding film has a tensile storage modulus at-5 ℃ of 100MPa or more.

Drawings

FIG. 1: a cross-sectional view showing the structure of a dicing tape according to an embodiment of the present invention.

FIG. 2: a cross-sectional view showing the structure of the dicing die-bonding film according to the embodiment of the present invention.

FIG. 3A: a cross-sectional view schematically showing a state of half-cut processing in a method of manufacturing a semiconductor integrated circuit.

FIG. 3B: a cross-sectional view schematically showing a state of half-cut processing in a method of manufacturing a semiconductor integrated circuit.

FIG. 3C: a cross-sectional view schematically showing a state of back grinding processing in the method of manufacturing a semiconductor integrated circuit.

FIG. 3D: a cross-sectional view schematically showing a state of back grinding processing in the method of manufacturing a semiconductor integrated circuit.

FIG. 4A: a cross-sectional view schematically showing a state of a mounting process in a method of manufacturing a semiconductor integrated circuit.

FIG. 4B: a cross-sectional view schematically showing a state of a mounting process in a method of manufacturing a semiconductor integrated circuit.

FIG. 5A: a cross-sectional view schematically showing the state of an expanding process at a low temperature in a method for manufacturing a semiconductor integrated circuit.

FIG. 5B: a cross-sectional view schematically showing the state of an expanding process at a low temperature in a method for manufacturing a semiconductor integrated circuit.

FIG. 5C: a cross-sectional view schematically showing the state of an expanding process at a low temperature in a method for manufacturing a semiconductor integrated circuit.

FIG. 6A: a cross-sectional view schematically showing a state of an extension process at normal temperature in a method for manufacturing a semiconductor integrated circuit.

FIG. 6B: a cross-sectional view schematically showing a state of an extension process at normal temperature in a method for manufacturing a semiconductor integrated circuit.

FIG. 7: a cross-sectional view schematically showing the state of a notch maintaining step in a method for manufacturing a semiconductor integrated circuit.

FIG. 8: a cross-sectional view schematically showing a state of a pickup process in a method of manufacturing a semiconductor integrated circuit.

Description of the reference numerals

1 base material layer

2 adhesive layer

3 chip bonding layer

10 cutting belt

20-dicing die-bonding film

1a No. 1 resin layer

1b No. 2 resin layer

1c No. 3 resin layer

G back side grinding belt

H holder

J adsorbs anchor clamps

P pin component

R cutting ring

Tape for T-wafer processing

U jack-up component

W semiconductor wafer

Detailed Description

An embodiment of the present invention will be described below.

[ cutting band ]

As shown in fig. 1, the dicing tape 10 of the present embodiment has a pressure-sensitive adhesive layer 2 laminated on a base material layer 1, and has a tensile storage modulus at-5 ℃ of 100MPa or more.

The reason why the tensile storage modulus of the dicing tape 10 at-5 ℃ is 100MPa or more and the cuttability of the semiconductor wafer stuck to the dicing tape 10 is improved is considered as follows.

In order to improve the cuttability (for example, cuttability with ease and uniform cuttability) of the semiconductor wafer bonded to the dicing tape 10 and cut into a plurality of semiconductor chips by spreading, it is necessary to sufficiently apply a tensile force to the entire dicing tape 10 at the start of cutting the semiconductor wafer.

Here, it can be considered that: when the dicing tape 10 is soft at the start of cutting, that is, when the tensile storage modulus of the dicing tape 10 is small, the tensile force at the start of cutting is gradually reduced by being absorbed by the dicing tape 10 as it approaches the central portion from the outer edge portion of the dicing tape 10. Therefore, it is considered difficult to sufficiently apply the stretching force at the start of cutting to the entire dicing tape 10.

In contrast, since the dicing tape 10 of the present embodiment has a large tensile storage modulus of 100MPa or more, it is considered that the tensile force at the start of cutting is less likely to be absorbed by the dicing tape 10 as it approaches the central portion from the outer edge portion of the dicing tape 10. Therefore, the tensile force at the start of cutting can be sufficiently applied to the entire dicing tape 10, and as a result, the semiconductor wafer can be easily cut into a plurality of semiconductor chips, and the semiconductor chips that are cut relatively uniformly can be easily obtained, that is, the cutting performance from the semiconductor wafer to the plurality of semiconductor chips can be further improved.

As will be described in the examples section below, by setting the tensile storage modulus at-5 ℃ of the dicing tape 10 to 100MPa or more, the cuttability when cutting a semiconductor wafer (for example, a semiconductor wafer having a diameter of 200mm (8 inches)) into small semiconductor chips (for example, a length of 12mm × a width of 4mm × a thickness of 0.55mm) can be further improved.

The present inventors speculate that the reason is as follows.

In the case of cutting semiconductor wafers of the same size, the smaller the size of the semiconductor chips after cutting, the narrower the interval between the grooves (lines) formed in the semiconductor wafer in the half-cut step, and therefore the larger the number of grooves formed in the semiconductor wafer. As a result, the elongation of the groove in the expanding step is reduced.

Therefore, when the semiconductor wafer is cut into small semiconductor chips in the expanding process, it is necessary to generate high stress at a lower elongation in order to suppress the occurrence of the cutting failure.

Here, the elastic modulus means: since the slope of stress with respect to elongation (amount of strain) when the base material layer is stretched, it is considered that high stress can be generated at a lower elongation when the modulus of elasticity is high.

In the expanding step using the dicing tape 10, since the expanding method at a temperature of-5 ℃ is most preferable from the viewpoint that the cutting property when the semiconductor wafer is cut into a plurality of small semiconductor chips is good and the dicing tape 10 is not broken by the tensile force, it is considered that high stress can be generated at a lower elongation by setting the tensile storage modulus at-5 ℃ to a high value such as 100MPa or more.

The present inventors have surmised that the cutting property when cutting a semiconductor wafer into small semiconductor chips can be further improved.

The dicing tape 10 of the present embodiment preferably has a tensile storage modulus at-5 ℃ of 400MPa or less.

Accordingly, since a sufficient tensile force is applied to the entire dicing tape 10 and the dicing tape 10 is relatively easily elongated, it is possible to suppress breakage of the dicing tape 10 due to the tensile force when cutting the semiconductor wafer attached to the dicing tape 10 into semiconductor chips, and further improve the cutting performance from the semiconductor wafer to the plurality of semiconductor chips.

Further, by setting the tensile storage modulus at-5 ℃ to 400MPa or less, the ability to cut a plurality of small semiconductor chips from a semiconductor wafer can be further improved.

The tensile storage modulus at-5 ℃ can be determined as follows.

Specifically, the tensile storage modulus of a test piece was measured at a temperature ranging from-50 to 100 ℃ under the conditions of a frequency of 1Hz, a deformation of 0.1%, a temperature rise rate of 10 ℃/min and an inter-jig distance of 22.5mm using a solid viscoelasticity measuring apparatus (for example, model RSAIII, manufactured by Rheometric Scientific Co., Ltd.) with a dicing tape having a length of 40mm (measurement length) and a width of 10mm as a test piece. In this case, the temperature can be determined by reading the value at-5 ℃.

The measurement is performed by stretching the test piece in the MD direction (resin flow direction).

The dicing tape 10 of the present embodiment preferably has a 30% tensile stress at-5 ℃ of 5.5N/10mm or more.

The dicing tape 10 of the present embodiment preferably has a 30% tensile stress at-5 ℃ of 30N/10mm or less.

Accordingly, since a sufficient tensile force is applied to the entire dicing tape 10 during the expansion and the dicing tape 10 is relatively easily elongated, the dicing tape 10 attached to the semiconductor wafer is expanded and the semiconductor wafer is cut into semiconductor chips, and therefore, the dicing tape can be prevented from being broken due to the expansion and the cutting performance from the semiconductor wafer to the plurality of semiconductor chips can be further improved.

Further, by setting the 30% tensile stress at-5 ℃ to 30N/10mm or less, the cutting property from the semiconductor wafer to a plurality of small semiconductor chips can be further improved.

The dicing tape 10 of the present embodiment preferably has a 30% tensile stress of 3.2N/10mm or more at room temperature (23 ℃).

The 30% tensile stress at room temperature (23 ℃) is preferably 30N/10mm or less.

Further, by setting the 30% tensile stress at room temperature to 30N/10mm or less, the cutting property from the semiconductor wafer to a plurality of small semiconductor chips can be further improved.

The 30% tensile stress at-5 ℃ and room temperature can be determined as follows.

Specifically, it can be obtained as follows: a test piece was cut with a length of 100mm and a width of 10mm, and the test piece was stretched at a measurement temperature (-5 ℃ C. and room temperature (23 ℃ C. + -1 ℃ C.) at a distance of 50mm between jigs and a stretching speed of 100 mm/min using a tensile tester (Tensilon Universal testing machine, Shimadzu corporation) to measure the stress at an elongation of 30% (distance between jigs 65 mm).

The dicing tape 10 of the present embodiment preferably has a ratio of 30% tensile stress at-5 ℃ to 30% tensile stress at room temperature of 1.7 or more.

The dicing tape 10 of the present embodiment preferably has a ratio of 30% tensile stress at-5 ℃ to 30% tensile stress at room temperature of 3.0 or less.

Further, by setting the ratio of 30% tensile stress at-5 ℃ to 30% tensile stress at room temperature to 3.0 or less, the ability to cut a plurality of small semiconductor chips from a semiconductor wafer can be further improved.

The base material layer 1 supports the adhesive layer 2. The base material layer 1 contains a resin. Examples of the resin contained in the substrate layer 1 include polyolefin, polyester, polyurethane, polycarbonate, polyether ether ketone, polyimide, polyetherimide, polyamide, wholly aromatic polyamide, polyvinyl chloride, polyvinylidene chloride, polyphenylene sulfide, fluororesin, cellulose resin, silicone resin, and the like.

Examples of the polyolefin include homopolymers of α -olefins, copolymers of two or more α -olefins, block polypropylene, random polypropylene, and copolymers of one or two or more α -olefins with another vinyl monomer.

The homopolymer of an α -olefin is preferably a homopolymer of an α -olefin having 2 to 12 carbon atoms. Examples of such homopolymers include ethylene, propylene, 1-butene, and 4-methyl-1-pentene.

Examples of the copolymer of two or more kinds of α -olefins include an ethylene/propylene copolymer, an ethylene/1-butene copolymer, an ethylene/propylene/1-butene copolymer, an ethylene/α -olefin copolymer having 5 or more and 12 or less carbon atoms, a propylene/ethylene copolymer, a propylene/1-butene copolymer, and a propylene/α -olefin copolymer having 5 or more and 12 or less carbon atoms.

Examples of the copolymer of one or two or more kinds of α -olefins with another vinyl monomer include an ethylene-vinyl acetate copolymer (EVA) and the like.

The polyolefin may be a substance called an α -olefin-based thermoplastic elastomer. Examples of the α -olefin-based thermoplastic elastomer include a combination of a propylene-ethylene copolymer and a propylene homopolymer, and a propylene-ethylene- α -olefin terpolymer having 4 or more carbon atoms.

Examples of commercially available products of α -olefin-based thermoplastic elastomers include Vistamaxx3980 (manufactured by ExxonMobil Chemical company) which is a propylene-based elastomer resin.

The substrate layer 1 may contain one kind of the above resin, or may contain two or more kinds of the above resins.

When the pressure-sensitive adhesive layer 2 includes an ultraviolet-curable pressure-sensitive adhesive described later, the base layer 1 is preferably configured to have ultraviolet transparency.

The substrate layer 1 may have a single-layer structure or a laminated structure. The substrate layer 1 may be obtained by non-stretch molding or by stretch molding, and is preferably obtained by stretch molding. When the base material layer 1 has a laminated structure, the base material layer 1 preferably has a layer containing an elastomer (hereinafter referred to as an elastomer layer) and a layer containing a non-elastomer (hereinafter referred to as a non-elastomer layer).

By providing the substrate layer 1 with an elastomer layer and a non-elastomer layer, the elastomer layer can function as a stress relaxation layer for relaxing tensile stress. That is, since the tensile stress generated in the base material layer 1 can be made small, the base material layer 1 can be made to have an appropriate hardness and be easily stretched.

This can improve the cutting performance from the semiconductor wafer to the plurality of semiconductor chips.

Further, when the cutting process is extended, the base material layer 1 can be prevented from being broken and damaged.

In the present specification, the elastomer layer means: a low elastic modulus layer having a lower tensile storage modulus at room temperature than the non-elastomeric layer. The elastic layer has a tensile storage modulus at room temperature of 10MPa or more and 100MPa or less, and the non-elastic layer has a tensile storage modulus at room temperature of 200MPa or more and 500MPa or less.

The elastomer layer may contain one kind of elastomer, or may contain two or more kinds of elastomers, and preferably contains an α -olefin-based thermoplastic elastomer.

The non-elastomer layer may contain one kind of non-elastomer, or may contain two or more kinds of non-elastomers, and preferably contains the metallocene PP described later.

When the base material layer 1 includes an elastomer layer and a non-elastomer layer, the base material layer 1 is preferably formed in a three-layer structure (non-elastomer layer/non-elastomer layer) having the elastomer layer as a core layer and having the non-elastomer layer on both surfaces of the core layer facing each other (see fig. 1). In fig. 1, one non-elastic body layer is represented by a 1 st resin layer 1a, an elastic body layer is represented by a 2 nd resin layer 1b, and the other non-elastic body layer is represented by a 3 rd resin layer 3 c.

In addition, as described above, in the notch maintaining step, hot air (for example, 100 to 130 ℃) is aligned with the dicing die-bonding film maintained in the expanded state at room temperature (for example, 23 ℃) to thermally shrink the dicing die-bonding film, and then the dicing die-bonding film is cooled and solidified, so that the outermost layer of the base layer 1 preferably includes a resin having a melting point close to the temperature of the hot air aligned with the dicing tape. This enables the outermost layer melted by hot air alignment to be solidified more quickly.

As a result, the notch can be more sufficiently maintained in the notch maintaining step.

When the base material layer 1 has a laminated structure of an elastomer layer and a non-elastomer layer, the elastomer layer includes an α -olefin thermoplastic elastomer, and the non-elastomer layer includes a polyolefin such as metallocene PP described later, the elastomer layer preferably includes 50 mass% or more and 100 mass% or less of the α -olefin thermoplastic elastomer, more preferably 70 mass% or more and 100 mass% or less, further preferably 80 mass% or more and 100 mass% or less, particularly preferably 90 mass% or more and 100 mass% or less, and most preferably 95 mass% or more and 100 mass% or less, with respect to the total mass of the elastomer forming the elastomer layer. When the α -olefin thermoplastic elastomer is contained in the above range, the affinity between the elastomer layer and the non-elastomer layer is improved, and therefore the base layer 1 can be relatively easily extrusion-molded. In addition, since the elastic body layer can function as a stress relaxation layer, the semiconductor wafer bonded to the dicing tape can be cut efficiently.

When the base material layer 1 has a laminated structure of an elastomer layer and a non-elastomer layer, the base material layer 1 is preferably obtained by coextrusion molding in which an elastomer and a non-elastomer are coextruded to form a laminated structure of an elastomer layer and a non-elastomer layer. As the coextrusion molding, any suitable coextrusion molding usually performed in the production of a film, a sheet, or the like can be employed. In the coextrusion molding, the inflation method and the coextrusion T-die method are preferably used in order to obtain the base layer 1 efficiently and inexpensively.

In the case where the base layer 1 having a laminated structure is obtained by coextrusion molding, the elastomer layer and the nonelastomer layer are in contact with each other in a state of being heated and melted, and therefore, it is preferable that the difference in melting point between the elastomer and the nonelastomer is small. Since the melting point difference is made small, it is possible to suppress excessive heat from being applied to either the elastomer or the non-elastomer having a low melting point, and it is therefore possible to suppress the thermal degradation of either the elastomer or the non-elastomer having a low melting point and the generation of by-products. In addition, the following can also be suppressed: the viscosity of either the elastomer or the non-elastomer having a low melting point is excessively reduced, and a lamination failure occurs between the elastomer layer and the non-elastomer layer. The difference in melting point between the elastomer and the non-elastomer is preferably 0 ℃ or more and 70 ℃ or less, and more preferably 0 ℃ or more and 55 ℃ or less.

The melting points of the elastomer and the non-elastomer can be measured by Differential Scanning Calorimetry (DSC) analysis. For example, the peak temperature of the endothermic peak is measured by raising the temperature to 200 ℃ at a temperature raising rate of 5 ℃ per minute under a nitrogen gas flow using a differential scanning calorimeter apparatus (model DSC Q2000 manufactured by TA INSTRUMENTS Co., Ltd.).

The thickness of the base layer 1 is preferably 55 μm or more and 195 μm or less, more preferably 55 μm or more and 190 μm or less, further preferably 55 μm or more and 170 μm or less, and most preferably 60 μm or more and 160 μm or less. By setting the thickness of the base material layer 1 to the above range, the dicing tape can be efficiently manufactured, and the semiconductor wafer bonded to the dicing tape can be efficiently cut.

The thickness of the base material layer 1 can be determined, for example, as follows: the thickness was measured at any 5 randomly selected points using a direct-reading thickness meter (model R-205 manufactured by PEACOCK), and the thickness was obtained by arithmetically averaging the thicknesses.

In the base layer 1 in which the elastomer layer and the non-elastomer layer are laminated, the ratio of the thickness of the non-elastomer layer to the thickness of the elastomer layer is preferably 1/25 or more and 1/3 or less, more preferably 1/25 or more and 1/3.5 or less, further preferably 1/25 or more and 1/4 or less, particularly preferably 1/22 or more and 1/4 or less, and is most preferably 1/20 or more and 1/4 or less. By setting the ratio of the thickness of the non-elastic body layer to the thickness of the elastic body layer in the above range, the semiconductor wafer attached to the dicing tape can be cut efficiently.

The elastomer layer may have a single-layer (1-layer) structure or a laminated structure. The elastomer layer preferably has a 1-5-layer structure, more preferably a 1-3-layer structure, and even more preferably a 1-2-layer structure, and the most preferred embodiment is a 1-layer structure. When the elastomer layer has a laminated structure, all layers may contain the same elastomer, or at least 2 layers may contain different elastomers.

The non-elastic layer may have a single layer (1 layer) structure or a laminated structure. The non-elastic layer preferably has a 1-5-layer structure, more preferably a 1-3-layer structure, and still more preferably a 1-2-layer structure, and the most preferred embodiment is a 1-layer structure. When the non-elastic body layer has a laminated structure, all layers may contain the same non-elastic body, or at least 2 layers may contain different non-elastic bodies.

The non-elastomer layer preferably contains a polypropylene resin (hereinafter referred to as metallocene PP) as a polymerization product obtained by using a metallocene catalyst as a non-elastomer. As the metallocene PP, a propylene/α -olefin copolymer as a polymerization product of a metallocene catalyst can be cited. By including the metallocene PP in the non-elastic body layer, the dicing tape can be efficiently manufactured, and the semiconductor wafer bonded to the dicing tape can be efficiently cut.

Commercially available metallocene PP includes WINTEC WXK1233 and WINTEC WMX03 (both available from Japan Polypropylene corporation).

Here, the metallocene catalyst is a catalyst comprising a transition metal compound of group 4 of the periodic table (so-called metallocene compound) containing a ligand having a cyclopentadienyl skeleton and a cocatalyst which reacts with the metallocene compound to activate the metallocene compound into a stable ionic state, the metallocene catalyst containing an organoaluminum compound as necessary. The metallocene compound is a crosslinked metallocene compound capable of stereoregular polymerization of propylene.

Among the propylene/α -olefin copolymers as the polymerization product of the metallocene catalyst, a propylene/α -olefin random copolymer as the polymerization product of the metallocene catalyst is preferable, and among the propylene/α -olefin random copolymers as the polymerization product of the metallocene catalyst, a copolymer selected from the group consisting of a propylene/α -olefin random copolymer having 2 carbon atoms as the polymerization product of the metallocene catalyst, a propylene/α -olefin random copolymer having 4 carbon atoms as the polymerization product of the metallocene catalyst, and a propylene/α -olefin random copolymer having 5 carbon atoms as the polymerization product of the metallocene catalyst is preferable, and among these, a propylene/ethylene random copolymer as the polymerization product of the metallocene catalyst is more preferable.

The propylene/α -olefin random copolymer as the polymerization product of the metallocene catalyst preferably has a melting point of 80 ℃ to 140 ℃, particularly 100 ℃ to 130 ℃, from the viewpoints of coextrudability with the elastomer layer and cuttability of a semiconductor wafer attached to a dicing tape.

The melting point of the propylene/α -olefin random copolymer as the polymerization product of the metallocene catalyst can be measured by the method described above.

Here, if the elastomer layer is disposed on the outermost layer of the substrate layer 1, the elastomer layers disposed on the outermost layer tend to stick together (easily stick together) when the substrate layer 1 is formed into a roll. Therefore, it becomes difficult to unwind the base material layer 1 from the roll body. In contrast, the preferred embodiment of the substrate layer 1 having the above-described laminated structure is a non-elastic layer/an elastic layer/a non-elastic layer, that is, a non-elastic layer is disposed on the outermost layer, and therefore the substrate layer 1 in this form is excellent in blocking resistance. Thus, the production of a semiconductor device using the dicing tape 10 can be inhibited from being delayed due to sticking.

The non-elastomer layer preferably contains a resin having a melting point of 100 ℃ or higher and 130 ℃ or lower and a molecular weight dispersity (mass average molecular weight/number average molecular weight) of 5 or lower. Such a resin may be metallocene PP.

By including the resin in the non-elastic layer, the non-elastic layer can be cooled and solidified more quickly in the notch maintaining step. Therefore, the occurrence of shrinkage of the base material layer 1 after heat-shrinking the dicing tape can be more sufficiently suppressed.

This makes it possible to more sufficiently maintain the notch in the notch maintaining step.

The adhesive layer 2 contains an adhesive. The adhesive layer 2 holds the semiconductor wafer for singulation into semiconductor chips by adhesion.

As the adhesive, an adhesive whose adhesive force can be reduced by an external action during use of the dicing tape 10 (hereinafter referred to as an adhesion-reducing adhesive) can be mentioned.

When an adhesion-reducing adhesive is used as the adhesive, the adhesive layer 2 can be used separately in a state showing a high adhesive force (hereinafter referred to as a high-adhesion state) and a state showing a low adhesive force (hereinafter referred to as a low-adhesion state) during use of the dicing tape 10. For example, when a semiconductor wafer attached to the dicing tape 10 is to be cut, a high adhesion state is used in order to suppress the plurality of semiconductor chips singulated by cutting the semiconductor wafer from floating or peeling from the adhesive layer 2. In contrast, after the semiconductor wafer is cut, a low adhesion state is used to pick up the singulated plurality of semiconductor chips so that the plurality of semiconductor chips can be easily picked up from the adhesive layer 2.

Examples of the adhesion-reducing adhesive include: an adhesive that can be cured by irradiation with radiation during use of the dicing tape 10 (hereinafter referred to as a radiation-curable adhesive).

Examples of the radiation-curable pressure-sensitive adhesive include: adhesives of the type that are cured by irradiation with electron beams, ultraviolet rays, alpha rays, beta rays, gamma rays, or X rays. Among these, an adhesive that cures by irradiation with ultraviolet rays (ultraviolet-curing adhesive) is preferably used.

Examples of the radiation-curable pressure-sensitive adhesive include additive type radiation-curable pressure-sensitive adhesives containing a base polymer such as an acrylic polymer, and a radiation-polymerizable monomer component and a radiation-polymerizable oligomer component having a functional group such as a radiation-polymerizable carbon-carbon double bond.

The acrylic polymer may be an acrylic polymer containing a monomer unit derived from a (meth) acrylate ester. Examples of the (meth) acrylate include alkyl (meth) acrylate, cycloalkyl (meth) acrylate, and aryl (meth) acrylate.

The adhesive layer 2 may contain an external crosslinking agent. Any external crosslinking agent may be used as long as it can react with the acrylic polymer as the base polymer to form a crosslinked structure. Examples of such external crosslinking agents include polyisocyanate compounds, epoxy compounds, polyol compounds, aziridine compounds, and melamine crosslinking agents.

Examples of the radiation-polymerizable monomer component include: urethane (meth) acrylate, trimethylolpropane tri (meth) acrylate, pentaerythritol tetra (meth) acrylate, dipentaerythritol monohydroxypenta (meth) acrylate, dipentaerythritol hexa (meth) acrylate, 1, 4-butanediol di (meth) acrylate, and the like. Examples of the radiation-polymerizable oligomer component include various oligomers such as urethane type, polyether type, polyester type, polycarbonate type, and polybutadiene type. The content ratio of the radiation polymerizable monomer component and the radiation polymerizable oligomer component in the radiation curable pressure-sensitive adhesive may be selected within a range in which the adhesiveness of the pressure-sensitive adhesive layer 2 is appropriately reduced.

The radiation-curable adhesive preferably contains a photopolymerization initiator. Examples of the photopolymerization initiator include α -ketol compounds, acetophenone compounds, benzoin ether compounds, ketal compounds, aromatic sulfonyl chloride compounds, photoactive oxime compounds, benzophenone compounds, thioxanthone compounds, camphorquinone, halogenated ketones, acyl phosphine oxides, and acyl phosphonates.

The pressure-sensitive adhesive layer 2 may contain, in addition to the above components, a crosslinking accelerator, a tackifier, an antioxidant, a colorant such as a pigment or a dye, and the like.

The thickness of the pressure-sensitive adhesive layer 2 is preferably 1 μm or more and 50 μm or less, more preferably 2 μm or more and 30 μm or less, and further preferably 5 μm or more and 25 μm or less.

[ dicing die-bonding film ]

Next, the dicing die-bonding film 20 will be described with reference to fig. 2. In the description of dicing the die-bonding film 20, the description of the portions overlapping with the dicing tape 10 will not be repeated.

As shown in fig. 2, the dicing die-bonding film 20 of the present embodiment includes a dicing tape 10 in which a pressure-sensitive adhesive layer 2 is laminated on a base material layer 1, and a die-bonding layer 3 laminated on the pressure-sensitive adhesive layer 2 of the dicing tape 10.

In the dicing die-bonding film 20, a semiconductor wafer is attached to the die-bonding layer 3.

In the cutting of the semiconductor wafer using the dicing die-bonding film 20, the die-bonding layer 3 is also cut together with the semiconductor wafer. The die bonding layer 3 is cut into a size corresponding to the size of the plurality of singulated semiconductor chips. Thus, a semiconductor chip with the chip bonding layer 3 can be obtained.

As described above, the dicing tape 10 for dicing the die-bonding film 20 has a tensile storage modulus at-5 ℃ of 100MPa or more.

Here, in general, since the chip bonding layer 3 of the dicing die bonding film 20 often contains an acrylic resin having a glass transition temperature (Tg) of about 0 ℃, the temperature in the spreading step is set to a temperature lower than Tg of the acrylic resin, and thus cracking is likely to occur. On the other hand, if the temperature in the spreading step is excessively lowered, the elastic modulus of the chip bonding layer 3 increases to such an extent that the cuttability of the chip bonding layer 3 is impaired. Therefore, the temperature in the extension step is preferably-5 ℃ from the viewpoint of the cuttability of the chip bonding layer 3.

Therefore, in the expanding step using the dicing die-bonding film 20, it is considered that the expanding step is performed at a temperature of-5 ℃ is most preferable from the viewpoint of the good cutting property when the semiconductor wafer is cut into a plurality of small semiconductor chips and the difficulty in breaking the dicing tape 10 by a tensile force as described above and from the viewpoint of the cutting property of the die-bonding layer 3.

Therefore, it is considered that high stress can be generated at a lower elongation by setting the tensile storage modulus at-5 ℃ to a high value of 100MPa in the dicing die-bonding film 20.

As a result, it is presumed that the cutting property when cutting the semiconductor wafer into small semiconductor chips can be further improved.

As described above, the dicing tape 10 for dicing the die-bonding film 20 preferably has a tensile storage modulus at-5 ℃ of 400MPa or less.

In addition, as described above, the dicing tape 10 for dicing the die-bonding film 20 preferably has a 30% tensile stress at-5 ℃ of 5.5N/10mm or more, a 30% tensile stress at room temperature of 3.2N/10mm or more, and a ratio of the 30% tensile stress at-5 ℃ to the 30% tensile stress at room temperature of 1.7 or more.

Further, as described above, the dicing tape 10 for dicing the die-bonding film 20 preferably has a 30% tensile stress at-5 ℃ of 30N/10mm or less, and preferably has a 30% tensile stress at room temperature of 30N/10mm or less.

The die bonding layer 3 is preferably thermosetting. By including at least one of a thermosetting resin and a thermoplastic resin having a thermosetting functional group in the chip bonding layer 3, thermosetting properties can be imparted to the chip bonding layer 3.

When the chip bonding layer 3 contains a thermosetting resin, examples of such thermosetting resin include epoxy resin, phenol resin, amino resin, unsaturated polyester resin, polyurethane resin, silicone resin, and thermosetting polyimide resin. Among these, epoxy resins are preferably used.

Examples of the epoxy resin include bisphenol a type, bisphenol F type, bisphenol S type, brominated bisphenol a type, hydrogenated bisphenol a type, bisphenol AF type, biphenyl type, naphthalene type, fluorene type, phenol novolac type, o-cresol novolac type, trishydroxyphenylmethane type, tetraphenylethane type, hydantoin type, triglycidyl isocyanurate type, and glycidylamine type epoxy resins.

Examples of the phenolic resin as a curing agent for the epoxy resin include novolak type phenolic resins, resol type phenolic resins, and polyoxystyrenes such as polyoxystyrenes.

When the chip bonding layer 3 contains a thermoplastic resin having a thermosetting functional group, examples of such a thermoplastic resin include an acrylic resin containing a thermosetting functional group. As the acrylic resin in the thermosetting functional group-containing acrylic resin, an acrylic resin containing a monomer unit derived from a (meth) acrylate ester can be cited.

The curing agent can be selected for the thermosetting resin having the thermosetting functional group according to the kind of the thermosetting functional group.

The die bonding layer 3 may contain a thermosetting catalyst from the viewpoint of sufficiently advancing the curing reaction of the resin component or increasing the curing reaction rate. Examples of the thermosetting catalyst include imidazole compounds, triphenylphosphine compounds, amine compounds, and trihaloborane compounds.

The chip bonding layer 3 may contain a thermoplastic resin. The thermoplastic resin functions as a binder. Examples of the thermoplastic resin include natural rubber, butyl rubber, isoprene rubber, chloroprene rubber, an ethylene-vinyl acetate copolymer, an ethylene-acrylic acid ester copolymer, a polybutadiene resin, a polycarbonate resin, a thermoplastic polyimide resin, a polyamide resin such as polyamide 6 and polyamide 6, a phenoxy resin, an acrylic resin, a saturated polyester resin such as PET and PBT, a polyamideimide resin, and a fluororesin. The thermoplastic resin may be used alone or in combination of two or more. As the thermoplastic resin, an acrylic resin is preferable from the viewpoint that ionic impurities are small, heat resistance is high, and connection reliability by the chip bonding layer is easily ensured.

The acrylic resin is preferably a polymer containing a monomer unit derived from a (meth) acrylate ester as the largest monomer unit in mass proportion. Examples of the (meth) acrylate include alkyl (meth) acrylate, cycloalkyl (meth) acrylate, and aryl (meth) acrylate. The acrylic resin may contain a monomer unit derived from another component copolymerizable with the (meth) acrylate. Examples of the other component include a carboxyl group-containing monomer, an acid anhydride monomer, a hydroxyl group-containing monomer, a glycidyl group-containing monomer, a sulfonic acid group-containing monomer, a phosphoric acid group-containing monomer, a functional group-containing monomer such as acrylamide and acrylonitrile, and various polyfunctional monomers. From the viewpoint of achieving high cohesive force in the die attach layer, the acrylic resin is preferably a copolymer of (meth) acrylate (particularly, an alkyl (meth) acrylate in which the alkyl group has 4 or less carbon atoms) and a carboxyl group-containing monomer, a nitrogen atom-containing monomer, and a polyfunctional monomer (particularly, a polyglycidyl-based polyfunctional monomer), and more preferably a copolymer of ethyl acrylate and butyl acrylate, acrylic acid, acrylonitrile, and polyglycidyl (meth) acrylate.

The chip bonding layer 3 may contain one or two or more other components as necessary. Examples of the other components include a flame retardant, a silane coupling agent, and an ion scavenger.

The thickness of the chip bonding layer 3 is preferably 40 μm or more, more preferably 60 μm or more, and further preferably 80 μm or more. The thickness of the chip bonding layer 3 is preferably 200 μm or less, more preferably 160 μm or less, and still more preferably 120 μm or less.

The dicing die-bonding film 20 of the present embodiment can be used as an auxiliary tool for manufacturing a semiconductor integrated circuit, for example. A specific example of using the dicing die-bonding film 20 will be described below.

An example of using the dicing die-bonding film 20 having the base layer 1 as one layer will be described below.

The method for manufacturing a semiconductor integrated circuit includes the steps of: a half-cut step of forming a groove in a semiconductor wafer by processing the semiconductor wafer into chips (Die) by a dicing process, and grinding the semiconductor wafer to reduce the thickness; a back grinding step of grinding the semiconductor wafer after the half-cut step to reduce the thickness; a mounting step of attaching one surface (for example, a surface opposite to the circuit surface) of the semiconductor wafer after the back grinding step to the die bonding layer 3 to fix the semiconductor wafer to the dicing tape 10; an expanding step of expanding the interval between the semiconductor chips subjected to the half-cut processing; a notch maintaining step of maintaining the interval between the semiconductor chips; a pickup step of peeling off the chip bonding layer 3 and the adhesive layer 2 to take out the semiconductor chip (Die) in a state where the chip bonding layer 3 is attached; and a Die bonding step of bonding the semiconductor chip (Die) with the Die bonding layer 3 attached thereto to an adherend. In performing these steps, the dicing tape (dicing die-bonding film) of the present embodiment is used as a manufacturing aid.

In the half-cut step, as shown in fig. 3A and 3B, half-cut processing for cutting the semiconductor integrated circuit into chips (Die) is performed. Specifically, the wafer processing tape T is attached to the surface of the semiconductor wafer W opposite to the circuit surface (see fig. 3A). Further, the dicing ring R is attached to the wafer processing tape T (see fig. 3A). The dividing grooves are formed in a state where the wafer processing tape T is attached (see fig. 3B). In the back grinding step, as shown in fig. 3C and 3D, the semiconductor wafer is ground to be thin. Specifically, the back grinding tape G is attached to the surface on which the grooves are formed, and the wafer processing tape T attached first is peeled off (see fig. 3C). The grinding process is performed with the back grinding tape G attached until the semiconductor wafer W reaches a predetermined thickness (see fig. 3D).

In the mounting step, as shown in fig. 4A to 4B, after the dicing ring R is mounted on the adhesive layer 2 of the dicing tape 10, the semiconductor wafer W (see fig. 4A) subjected to the half-dicing process is attached to the exposed surface of the chip bonding layer 3. After that, the back grinding tape G is peeled off from the semiconductor wafer W (see fig. 4B).

In the expanding step, as shown in fig. 5A to 5C, the cutting ring R is fixed to the holder H of the expanding device. The dicing die-bonding film 20 is lifted from the lower side by using a jack member U provided in the spreading device, and the dicing die-bonding film 20 is stretched and spread in the plane direction (see fig. 5B). Thus, the semiconductor wafer W subjected to the half-cut processing is cut under a specific temperature condition. The temperature is, for example, -20 to 5 ℃, preferably-15 to 0 ℃, and more preferably-10 to-5 ℃. The expanded state is released by lowering the jack-up member U (see fig. 5C).

Further, in the expanding step, as shown in fig. 6A to 6B, the dicing tape 10 is stretched under a higher temperature condition (for example, room temperature (23 ℃)) to expand the area. Thus, the cut adjacent semiconductor chips W are separated in the plane direction of the thin film surface, and the interval is further increased.

Here, since the die-bonding film 20 of the present embodiment has a tensile storage modulus at-5 ℃ of 100MPa or more, the ability to cut a semiconductor wafer into a plurality of semiconductor chips by expansion under low temperature conditions can be further improved.

In the notch maintaining step, as shown in fig. 7, after the dicing tape 10 is thermally shrunk by directing hot air (for example, 100 to 130 ℃) to the dicing tape 10, the dicing tape is cooled and solidified, and the distance (notch) between the cut adjacent semiconductor chips W is maintained.

In the pickup step, as shown in fig. 8, the semiconductor chip W with the die bonding layer 3 attached thereto is peeled off from the adhesive layer 2 of the dicing tape 10. Specifically, the pin member P is raised to lift the semiconductor chip W to be picked up via the dicing tape 10. The semiconductor chip lifted up is held by the suction jig J.

In the die bonding step, the semiconductor chip W with the die bonding layer 3 attached thereto is bonded to an adherend.

In the above-described semiconductor integrated circuit manufacturing, the example in which the dicing die-bonding film 20 is used as the auxiliary tool has been described, but when the dicing tape 10 is used as the auxiliary tool, the semiconductor integrated circuit can be manufactured in the same manner as described above.

The matters disclosed in the present specification include the following matters.

(1)

A dicing tape comprising a substrate layer and an adhesive layer laminated thereon,

the cutting belt has a tensile storage modulus at-5 ℃ of 100MPa or more.

According to the above constitution, the dicing tape has a tensile storage modulus at-5 ℃ of 100MPa or more, and therefore can have a large hardness.

Therefore, when the dicing tape is attached to a semiconductor wafer and the semiconductor wafer is cut into a plurality of semiconductor chips by expanding the dicing tape under low temperature conditions (for example, -15 ℃ to 5 ℃), a tensile force can be sufficiently applied to the entire dicing tape at the start of expansion.

Therefore, the semiconductor wafer can be easily cut into a plurality of semiconductor chips, and the semiconductor chips can be easily cut uniformly.

That is, the cutting performance of the semiconductor wafer can be further improved.

(2)

The dicing tape according to the above (1), wherein the tensile storage modulus at-5 ℃ is 400MPa or less.

According to the above configuration, since a sufficient tensile force is applied to the entire dicing tape and the dicing tape is relatively easily elongated, it is possible to further suppress breakage of the dicing tape due to the tensile force when the semiconductor wafer bonded to the dicing tape is cut into the plurality of semiconductor chips, and to improve the cutting performance from the semiconductor wafer into the plurality of semiconductor chips.

(3)

The dicing tape according to the above (1) or (2), wherein a 30% tensile stress at-5 ℃ is 5.5N/10mm or more.

According to the above configuration, the 30% tensile stress at-5 ℃ is 5.5N/10mm or more, and therefore, when the dicing tape is attached to a semiconductor wafer and the dicing tape is expanded at a low temperature to cut a plurality of semiconductor chips from the semiconductor wafer, the dicing tape can be made to have a large hardness even during expansion.

Therefore, it becomes easier to cut the semiconductor wafer into a plurality of semiconductor chips, and it becomes easier to obtain semiconductor chips that are cut more uniformly.

That is, the cuttability of the semiconductor wafer can be further improved.

(4)

The dicing tape according to any one of the above (1) to (3), wherein a 30% tensile stress at-5 ℃ is 30N/10mm or less.

According to the above configuration, since a sufficient tensile force is applied to the entire dicing tape during expansion and the dicing tape is relatively easily elongated, the dicing tape can be further prevented from being broken due to expansion and the cutting performance from the semiconductor wafer to the plurality of semiconductor chips can be improved while the dicing tape attached to the semiconductor wafer is expanded to cut the semiconductor wafer into the plurality of semiconductor chips.

(5)

The dicing tape according to any one of the above (1) to (4), wherein a 30% tensile stress at room temperature is 3.2N/10mm or more.

According to the above configuration, since the 30% tensile stress at room temperature is 3.2N/10mm or more, when the dicing tape is attached to a semiconductor wafer and the dicing tape is expanded at a low temperature to cut a plurality of semiconductor chips from the semiconductor wafer, the cuttability of the semiconductor wafer can be further improved during expansion.

Further, the tensile stress generated by the dicing tape between the semiconductor chips that are cut can be suppressed from being transferred to the semiconductor chip side.

Therefore, it is possible to relatively suppress the outer edge portion of the semiconductor chip from being lifted from the surface of the dicing tape (chip lifting) by applying a large force to the outer edge portion of the semiconductor chip.

(6)

The dicing tape according to any one of the above (1) to (5), wherein a 30% tensile stress at room temperature is 30N/10mm or less.

(7)

The dicing tape according to any one of the above (1) to (6), wherein a ratio of 30% tensile stress at-5 ℃ to 30% tensile stress at room temperature is 1.7 or more.

According to the above configuration, since the ratio of the 30% tensile stress at-5 ℃ to the 30% tensile stress at room temperature is 1.7 or more, when the dicing tape is attached to a semiconductor wafer and the dicing tape is stretched at a low temperature to cut the semiconductor wafer into a plurality of semiconductor chips, the cutting property of the semiconductor wafer can be further improved during the stretching.

Further, chip lifting caused by transfer of tensile stress generated by the dicing tape to the semiconductor chip side can be relatively suppressed.

(8)

The dicing tape according to any one of the above (1) to (7), wherein a ratio of 30% tensile stress at-5 ℃ to 30% tensile stress at room temperature is 3.0 or less.

According to the above configuration, since a sufficient tensile force is applied to the entire dicing tape during expansion and the dicing tape is relatively easily elongated, the dicing tape can be further broken by the expansion and the cutting performance from the semiconductor wafer to the plurality of semiconductor chips can be improved while the dicing tape attached to the semiconductor wafer is expanded and the semiconductor wafer is cut into the plurality of semiconductor chips.

(9)

The dicing tape according to any one of the above (1) to (8), wherein the base material layer has a three-layer structure including an elastic layer as a core layer and having non-elastic layers on both surfaces of the core layer facing each other.

According to the above configuration, the elastic body layer can function as a stress relaxation layer for relaxing tensile stress. That is, since the tensile stress generated in the base material layer can be relatively reduced, the base material layer can be made to have an appropriate hardness and be easily stretched.

Thus, the cutting performance from the semiconductor wafer to the plurality of semiconductor chips can be improved.

Further, the base material layer can be prevented from being broken and damaged during the spreading in the cutting step.

(10)

A dicing die-bonding film comprising:

a die bonding layer laminated on the adhesive layer of the dicing tape,

According to the above configuration, when the dicing tape is attached to a semiconductor wafer and the dicing tape is spread under low temperature conditions (for example, -15 to 5 ℃) to cut the semiconductor wafer into a plurality of semiconductor chips, the tensile force can be sufficiently applied to the entire dicing tape at the start of spreading.

Thus, the cuttability of the semiconductor wafer can be further improved, and the cuttability of the chip bonding layer can be improved.

The dicing tape and the dicing die-bonding film of the present invention are not limited to the above embodiments. The dicing tape and the dicing die-bonding film of the present invention are not limited to the above-described effects. The dicing tape and the dicing die-bonding film of the present invention can be variously modified within a range not departing from the gist of the present invention.

Examples

The present invention will be described in more detail with reference to examples. The following examples are intended to illustrate the present invention in further detail, and are not intended to limit the scope of the present invention.

[ example 1]

< formation of substrate layer >

A substrate layer having a 3-layer structure of a layer a/a layer B/a layer C (a 3-layer structure having a layer B as a center layer and a layer a and a layer C as outer layers laminated on both sides of the layer B) was molded using two types of 3-layer extrusion T-die molding machines. As the resins for the A and C layers, metallocene PP (trade name: WINTEC WXK1233, manufactured by Japan Polypropylene corporation) was used, and as the resin for the B layer, EVA (trade name: Evaflex EV250, Mitsui DuPont Polychemical Co., Ltd., manufactured by Ltd.) was used.

The above extrusion molding was carried out at a die temperature of 190 ℃. That is, the A, B, and C layers were extrusion molded at 190 ℃. The thickness of the substrate layer obtained by extrusion molding was 100 μm. The thickness ratio (layer thickness ratio) of the a layer, the B layer, and the C layer is the a layer: layer B: layer C is 1: 10: 1.

after the molded substrate layer is sufficiently cured, the cured substrate layer is wound into a roll to produce a roll.

< making of dicing tape >

The adhesive composition was applied from a roll-shaped substrate layer to one surface of the substrate layer using an applicator so as to have a thickness of 10 μm. The base layer coated with the adhesive composition was dried by heating at 110 ℃ for 3 minutes to form an adhesive layer, thereby obtaining a dicing tape.

The above adhesive composition was prepared as follows.

First, 173 parts by mass of INA (isononyl acrylate), 54.5 parts by mass of HEA (hydroxyethyl acrylate), 0.46 part by mass of AIBN (2, 2' -azobisisobutyronitrile), and 372 parts by mass of ethyl acetate were mixed to obtain a 1 st resin composition.

Then, the resin composition 1 was charged into a separable round-bottom flask (capacity: 1L), equipped with a separable round-bottom flask, a thermometer, a nitrogen gas inlet tube, and a stirring blade, in a polymerization experimental apparatus, and the liquid temperature of the resin composition 1 was brought to normal temperature (23 ℃ C.) while stirring the resin composition 1, and the inside of the separable round-bottom flask was replaced with nitrogen gas for 6 hours.

Then, while nitrogen gas was introduced into the separable round-bottomed flask, the liquid temperature of the first resin composition 1 was maintained at 62 ℃ for 3 hours while stirring the first resin composition 1, and thereafter, the liquid temperature was maintained at 75 ℃ for 2 hours, whereby the INA, the HEA, and the AIBN were polymerized to obtain a second resin composition 2. Thereafter, the inflow of nitrogen gas into the round-bottomed separable flask was stopped.

After the resin composition No. 2 was cooled to a liquid temperature of room temperature, 52.5 parts by mass of 2-isocyanatoethyl methacrylate (product name "Karenz MOI (registered trademark)") as a compound having a polymerizable carbon-carbon double bond and 0.26 part by mass of dibutyltin dilaurate IV (Wako pure chemical industries, Ltd.) were added to the resin composition No. 2 to obtain a resin composition No. 3, and the resin composition No. 3 thus obtained was stirred at a liquid temperature of 50 ℃ for 24 hours in an atmospheric atmosphere.

Then, after adding 0.75 parts by mass of CORONATE L (isocyanate compound) and 2 parts by mass of Omnirad127 (photopolymerization initiator) to 100 parts by mass of the solid polymer component, the 3 rd resin composition was diluted with ethyl acetate until the solid content concentration reached 20% by mass, to prepare an adhesive composition.

< making of dicing die-bonding film >

100 parts by mass of an acrylic resin (tradename "SG-P3" manufactured by Citsubishi chemical Co., Ltd., glass transition temperature 12 ℃), 46 parts by mass of an epoxy resin (tradename "JER 1001" manufactured by Mitsubishi chemical Co., Ltd.), 51 parts by mass of a phenol resin (tradename "MEH-7851 ss" manufactured by Ming and Kasei Co., Ltd.), 191 parts by mass of spherical silica (tradename "SO-25R" manufactured by Admatech Co., Ltd.), and 0.6 part by mass of a curing catalyst (tradename "CURIZOL PHZ" manufactured by Sitsubishi chemical industries Co., Ltd.) were added to methyl ethyl ketone and mixed to obtain a die-bonding composition having a solid content of 20 mass%.

Then, the die-bonding composition was applied to the silicone-treated surface of a PET-based separator (thickness 50 μm) as a release liner using an applicator so as to have a thickness of 10 μm, and dried at 130 ℃ for 2 minutes to remove the solvent from the die-bonding composition, thereby obtaining a die-bonding sheet in which a die-bonding layer was laminated on the release liner.

Then, one side of the die bonding sheet on which the release sheet is not laminated is bonded to the adhesive layer of the dicing tape, and then the release liner is peeled from the die bonding layer, thereby obtaining a dicing die bonding film having a die bonding layer.

For the dicing tape obtained as above, the tensile storage modulus at-5 ℃ and the 30% tensile stress at-5 ℃ and 23 ℃ were measured as described below. Further, the chip lifting from the dicing die-bonding film during spreading (hereinafter referred to as chip lifting) and the cuttability of the chip and the chip-bonding layer (hereinafter referred to as cuttability) were evaluated.

(-tensile storage modulus at 5 ℃ C.)

A test piece having a length of 40mm (measurement length). times.a width of 10mm was cut out from the dicing tape of example 1, and the tensile storage modulus at-5 ℃ was determined by reading the value of the tensile elastic modulus at-5 ℃ in the case of measuring the tensile storage modulus of the test piece at-50 to 100 ℃ under the conditions of a frequency of 1Hz, a deformation of 0.1%, a temperature rise rate of 10 ℃/min and an inter-jig distance of 22.5mm using a solid viscoelasticity measuring apparatus (model RSAIII, manufactured by Rheometric Scientific Co., Ltd.).

(-5 ℃ C. and 30% tensile stress at room temperature)

A test piece 100mm in length × 10mm in width was cut from the dicing tape of example 1, and the test piece was stretched at a measurement temperature (-5 ℃ C. and room temperature) under a condition of an inter-jig distance of 50mm and a stretching speed of 100 mm/min using a tensile tester (Tensilon Universal testing machine, Shimadzu corporation), and the stress at an elongation of 30% (inter-jig distance of 65mm) was measured.

(evaluation of chip lifting)

A bare wafer (300 mm in diameter) and a dicing ring were attached to the dicing die-bonding film of example 1. Thereafter, the semiconductor wafer and the chip bonding layer were cut using a chip separating apparatus DDS230 (manufactured by DISCO corporation), and the chip lift after cutting was evaluated. The bare wafer was cut into bare chips having a size of 12mm in length, 4mm in width, and 0.055mm in thickness.

As the bare wafer, a warped wafer is used.

Warped wafers were fabricated as follows.

First, the following (a) to (f) were dissolved in methyl ethyl ketone to obtain a warpage-adjusting composition having a solid content concentration of 20 mass%.

(a) Acrylic resin (tradename "SG-70L", tradename of tradename, tradename: 5 parts by mass

(b) Epoxy resin (product name "JER 828" manufactured by Mitsubishi chemical corporation): 5 parts by mass

(c) Phenol resin (product name "LDR 8210" manufactured by minko chemical industries, Ltd.): 14 parts by mass

(d) Epoxy resin (trade name "MEH-8005", manufactured by Mitsubishi chemical corporation): 2 parts by mass

(e) Spherical silica (product name "SO-25R" manufactured by Admatechs Co.): 53 parts by mass

(f) Phosphorus-based catalyst (TPP-K): 1 part by mass

Then, the warpage-adjusting composition was applied to the silicone-treated surface of a PET-based separator (thickness 50 μm) as a release liner with a thickness of 25 μm using an applicator, and dried at 130 ℃ for 2 minutes to remove the solvent from the warpage-adjusting composition, thereby obtaining a warpage-adjusting sheet in which a warpage-adjusting layer was laminated on the release liner.

Then, a bare wafer was attached to the side of the warpage-adjusting sheet on which the release liner was not laminated by using a laminator (model MRK-600, manufactured by MCK) under conditions of 60 ℃, 0.1MPa and 10mm/s, and the resultant was placed in an oven and heated at 175 ℃ for 1 hour to thermally cure the resin of the warpage-adjusting layer, whereby the warpage-adjusting layer was shrunk to obtain a warped bare wafer.

After shrinking the warpage-adjusting layer, a tape for wafer processing (product name "V-12 SR 2" manufactured by hitto electrical corporation) was attached to the warped bare wafer on the side where the warpage-adjusting layer was not laminated, and then the dicing ring was fixed to the warped bare wafer via the tape for wafer processing. Then, the warpage adjusting layer is removed from the warped bare wafer.

Grooves having a depth of 100 μm from the entire surface (hereinafter referred to as one surface) of the warped bare wafer from which the warpage adjusting layer has been removed are formed in a lattice shape (width 20 μm) using a dicing apparatus (model 6361, manufactured by DISCO corporation).

Then, a back-grinding tape is attached to one surface of the warped bare wafer, and the wafer-processing tape is removed from the other surface (the surface opposite to the one surface) of the warped bare wafer.

Then, the warped bare wafer was ground from the other surface side by using a back grinder (model DGP8760, manufactured by DISCO corporation) until the thickness of the warped bare wafer reached 55 μm (0.055mm), and the obtained wafer was regarded as a warped wafer.

In detail, the chip lifting was evaluated as follows.

First, the bare wafer and the die bonding layer were cut by a cold expanding unit under conditions of an expansion temperature of-5 ℃, an expansion rate of 100 mm/sec, and an expansion amount of 12mm, to obtain a semiconductor chip with a die bonding layer.

Then, the film was stretched at room temperature at a stretching speed of 1 mm/sec and a stretching amount of 5 mm. Then, the dicing die bonding film at the boundary portion with the outer edge of the bare wafer was thermally shrunk under the conditions of a heating temperature of 200 ℃, a heating distance of 18mm, and a rotation speed of 5 °/second while maintaining the expanded state.

Then, the floating state of the semiconductor chip with the die bond layer was photographed by microscopic observation on the surface of the base layer of the dicing die bond film, and binarized, thereby calculating the floating area. Then, the floating area was evaluated as good when it was less than 4%, and evaluated as poor when it was 4% or more.

(evaluation of cuttability)

A bare wafer (300 mm in diameter) and a dicing ring were attached to the dicing die-bonding film of example 1. Thereafter, the bare wafer and the die bonding layer were cut using a die detaching apparatus DDS230 (manufactured by DISCO corporation).

The bare wafer is cut into bare chips having a size of 3.2mm in length, 1.4mm in width, and 0.025mm in thickness.

Specifically, the cuttability was evaluated as follows.

First, the bare wafer and the die bonding layer were cut by a cold expanding unit under conditions of an expansion temperature of-5 ℃, an expansion rate of 100 mm/sec, and an expansion amount of 14mm, to obtain a semiconductor chip with a die bonding layer.

Then, the film was stretched at room temperature at a stretching speed of 1 mm/sec and a stretching amount of 10 mm. Then, while maintaining the expanded state, the dicing die bonding film at the boundary portion with the outer edge of the bare wafer was thermally shrunk at a heating temperature of 200 ℃, a heating distance of 18mm, and a rotation speed of 5 °/second.

Then, the cut portion of the semiconductor chip with the chip bonding layer was observed by microscope observation, and the cutting rate was calculated. Thereafter, the evaluation was evaluated as good when the cut rate was 90% or more, and the evaluation was evaluated as poor when the cut rate was less than 90%.

[ example 2]

A dicing tape and a dicing die-bonding film of example 2 were obtained in the same manner as in example 1 except that the base material layer was 80 μm.

Further, the dicing tape of example 2 was measured for the tensile storage modulus at-5 ℃ and the 30% tensile stress at-5 ℃ and 23 ℃ in the same manner as in example 1.

Further, the dicing die-bonding film of example 2 was evaluated for chip lifting and cutting properties.

[ example 3]

The dicing tape and the dicing die-bonding film of example 3 were obtained in the same manner as in example 1 except that EVA constituting the B layer (center layer) of the base layer was made into Evaflex EV550 (manufactured by Mitsui DuPont polymeric co., ltd.) and the base layer was made into 80 μm.

Further, the dicing tape of example 3 was measured for the tensile storage modulus at-5 ℃ and the 30% tensile stress at-5 ℃ and 23 ℃ in the same manner as in example 1.

Further, the dicing die-bonding film of example 3 was evaluated for chip lifting and cutting properties.

[ example 4]

The dicing tape and the dicing die-bonding film of example 4 were obtained in the same manner as in example 1 except that the resin of the layer B was an acrylic elastomer (trade name: Vistamaxx3980, product of ExxonMobil Chemical company).

Further, the dicing tape of example 4 was measured for the tensile storage modulus at-5 ℃ and the 30% tensile stress at-5 ℃ and 23 ℃ in the same manner as in example 1.

Further, the dicing die-bonding film of example 4 was evaluated for chip lifting and cutting properties.

[ example 5]

The thickness of the base material layer was set to 80 μm, and the layer thickness ratio of the base material layer was set to layer a: layer B: layer C is 1: 4: 1, a dicing tape and a dicing die-bonding film of example 5 were obtained in the same manner as in example 1 except for the above.

Further, the dicing tape of example 5 was measured for the tensile storage modulus at-5 ℃ and the 30% tensile stress at-5 ℃ and 23 ℃ in the same manner as in example 1.

Further, the dicing die-bonding film of example 5 was evaluated for chip lifting and cutting properties.

[ example 6]

The dicing tape and the dicing die-bonding film of example 6 were obtained in the same manner as in example 1 except that the metallocene PP constituting the a layer and the C layer (outer layer) of the base material layer was WINTEC WMX03 (manufactured by japan polypropylene co.

Further, the dicing tape of example 6 was measured for the tensile storage modulus at-5 ℃ and the 30% tensile stress at-5 ℃ and 23 ℃ in the same manner as in example 1.

Further, the dicing die-bonding film of example 6 was evaluated for chip lifting and cutting properties.

[ example 7]

A dicing tape and a dicing die-bonding film of example 7 were obtained in the same manner as in example 1, except that the EVA resin of the layer B constituting the base layer was changed to Ultrathene651 (manufactured by tokyo corporation).

Further, the dicing tape of example 7 was measured for the tensile storage modulus at-5 ℃ and the 30% tensile stress at-5 ℃ and 23 ℃ in the same manner as in example 1.

Further, the dicing die-bonding film of example 7 was evaluated for chip lifting and cutting properties.

[ example 8]

A dicing tape and a dicing die-bonding film of example 8 were obtained in the same manner as in example 1, except that the base material layer had a single-layer structure and the thickness of the base material layer was 125 μm.

The substrate layer was molded using a single layer extrusion T-die molding machine. As the resin of the base layer, a propylene elastomer (trade name: Vistamaxx3980, product of ExxonMobil Chemical company) was used.

Further, the dicing tape of example 8 was measured for the tensile storage modulus at-5 ℃ and the 30% tensile stress at-5 ℃ and 23 ℃ in the same manner as in example 1.

Further, the dicing die-bonding film of example 8 was evaluated for chip lifting and cutting properties.

[ example 9]

A dicing tape and a dicing die-bonding film of example 9 were obtained in the same manner as in example 8, except that the thickness of the base material layer was set to 100 μm.

Further, the dicing tape of example 9 was measured for the tensile storage modulus at-5 ℃ and the 30% tensile stress at-5 ℃ and 23 ℃ in the same manner as in example 1.

Further, the dicing die-bonding film of example 9 was evaluated for chip lifting and cutting properties.

Comparative example 1

A dicing tape and a dicing die-bonding film of comparative example 1 were obtained in the same manner as in example 8 except that the resin of the base layer was Evaflex EV250(Mitsui DuPont polymeric co., ltd.).

Further, the dicing tape of comparative example 1 was measured for the tensile storage modulus at-5 ℃ and the 30% tensile stress at-5 ℃ and 23 ℃ in the same manner as in example 1.

Further, the dicing die-bonding film of comparative example 1 was evaluated for chip lifting and cuttability.

Comparative example 2

A dicing tape and a dicing die-bonding film of comparative example 2 were obtained in the same manner as in comparative example 1 except that the thickness of the base material layer was set to 100 μm.

Further, the dicing tape of comparative example 2 was measured for the tensile storage modulus at-5 ℃ and the 30% tensile stress at-5 ℃ and 23 ℃ in the same manner as in example 1.

Further, the dicing die-bonding film of comparative example 2 was evaluated for chip lifting and cuttability.

The measurement results of the tensile storage modulus at-5 ℃, the tensile stress at-5 ℃ and the tensile stress at 23 ℃ of the dicing tape of each example, and the evaluation results of the chip lifting and the cutting properties of the dicing die-bonding film of each example are shown in table 1 below.

[ TABLE 1]

As is clear from Table 1, the dicing tapes of examples 1 to 9 all showed values of tensile storage modulus at-5 ℃ of 100MPa or more, and the dicing die-bonding films of examples 1 to 9 were excellent in cuttability.

As is clear from table 1, the dicing die-bonding films of examples 1 to 7 each including the dicing tape of examples 1 to 7, that is, the dicing tape having the substrate layer having the 3-layer structure, can suppress chip lifting.

In contrast, it is known that: the dicing tapes of comparative examples 1 and 2 both had a tensile storage modulus value at-5 ℃ of less than 100MPa, and the dicing die-bonding films of comparative examples 1 and 2 had poor cuttability and could not suppress chip lifting.

Although the results shown in table 1 relate to dicing the die-bonding film, it is expected that the dicing tape included in the dicing die-bonding film can also obtain the same results as those shown in table 1.

Claims

1. A dicing tape comprising a substrate layer and an adhesive layer laminated thereon,

the cutting belt has a tensile storage modulus at-5 ℃ of 100MPa or more.

2. The dicing tape according to claim 1, wherein the 30% tensile stress at-5 ℃ is 5.5N/10mm or more.

3. The dicing tape according to claim 1 or 2, wherein the 30% tensile stress at room temperature is 3.2N/10mm or more.

4. The dicing tape according to claim 1, wherein a ratio of 30% tensile stress at-5 ℃ to 30% tensile stress at room temperature is 1.7 or more.

5. The dicing tape according to claim 2, wherein a ratio of 30% tensile stress at-5 ℃ to 30% tensile stress at room temperature is 1.7 or more.

6. The dicing tape according to claim 3, wherein a ratio of 30% tensile stress at-5 ℃ to 30% tensile stress at room temperature is 1.7 or more.

7. A dicing die-bonding film comprising:

a chip bonding layer laminated on the adhesive layer of the dicing tape,