TW202123325A - Dicing tape and dicing die-bonding film - Google Patents

Abstract

A dicing tape according to the present invention includes a base layer and an adhesive layer laminated on the base layer, and has a tensile storage elastic modulus at -5 °C of 100 MPa or more.

Description

切晶帶及切晶黏晶膜Slicing tape and slicing chip mucosal film

本發明係關於一種切晶帶及切晶黏晶膜。The invention relates to a dicing tape and a dicing crystal sticking film.

已知先前於在半導體裝置之製造中，為了獲得黏晶用之半導體晶片而使用切晶帶、切晶黏晶膜。 上述切晶帶係於基材層上積層黏著劑層而構成，上述切晶黏晶膜係於上述切晶帶之黏著劑層上可剝離地積層黏晶層而構成。It is known that in the manufacture of semiconductor devices, dicing tape and dicing die bonding film are used in order to obtain semiconductor wafers for die bonding. The dicing tape is formed by laminating an adhesive layer on a substrate layer, and the dicing die-bonding film is formed by laminating a die-bonding layer on the adhesive layer of the dicing tape so as to be peelable.

並且已知，作為使用上述切晶黏晶膜獲得黏晶用半導體晶片(Die)之方法，採用具有下述步驟之方法：半切割步驟，其為了藉由切斷處理將半導體晶圓加工成晶片(Die)而在半導體晶圓上形成槽，進而對半導體晶圓進行研削而使厚度變薄；背面研磨步驟，其對半切割步驟後之半導體晶圓進行研削而使厚度變薄；安裝步驟，其將背面研磨步驟後之半導體晶圓之一面(例如與電路面相反側之面)貼附於黏晶層而將半導體晶圓固定於切晶帶；擴開步驟，其將經半切割加工之半導體晶片彼此之間隔擴大；切口維持步驟，其維持半導體晶片彼此之間隔；拾取步驟，其於黏晶層與黏著劑層之間進行剝離，以貼附有黏晶層之狀態取出半導體晶片；及黏晶步驟，其使貼附有黏晶層之狀態之半導體晶片接著於被接著體(例如安裝基板等)。 再者，於上述切口維持步驟中，使熱風(例如100〜130℃)對準切晶帶以使切晶帶熱收縮後進行冷卻固化，而維持被切斷之相鄰之半導體晶片間之距離(切口)。 又，於上述擴開步驟中，上述黏晶層被切斷為與單片化之複數個半導體晶片之尺寸相當之大小。It is also known that as a method of obtaining a semiconductor wafer (Die) for die bonding using the above-mentioned die-cutting die-bonding film, a method having the following steps is adopted: a half-cutting step, which is used to process the semiconductor wafer into a wafer through a cutting process (Die) To form a groove on the semiconductor wafer, and then grind the semiconductor wafer to make the thickness thin; the back grinding step, which grinds the semiconductor wafer after the half-cut step to make the thickness thin; the mounting step, It attaches one side of the semiconductor wafer (for example, the side opposite to the circuit surface) after the back grinding step to the die-bonding layer to fix the semiconductor wafer on the dicing tape; in the expansion step, it will be processed by half-cutting. The gap between the semiconductor chips is enlarged; the incision maintaining step is to maintain the gap between the semiconductor chips; the picking step is to peel off between the die bond layer and the adhesive layer, and take out the semiconductor die with the die bond layer attached; and In the die bonding step, the semiconductor chip in the state where the die bonding layer is attached is attached to the adherend (such as a mounting substrate, etc.). Furthermore, in the above-mentioned notch maintaining step, hot air (for example, 100~130°C) is aligned with the dicing tape so that the dicing tape is thermally contracted and then cooled and solidified, so as to maintain the distance between the cut adjacent semiconductor wafers (incision). In addition, in the expansion step, the die-bonding layer is cut into a size equivalent to the size of a plurality of singulated semiconductor wafers.

於使用如上述之切晶黏晶膜獲得黏晶用半導體晶片之方法中，專利文獻1中揭示有：藉由使用具有特定物性之切晶帶(-10℃下之初始彈性模數為200MPa以上且380MPa以下且-10℃下之Tanδ(損失彈性模數/儲存模數)為0.080以上0.3以下之切晶帶)，且於-15〜5℃之低溫條件下進行上述擴開步驟，於上述擴開步驟中可提高自上述半導體晶圓向複數個半導體晶片之切斷性(例如切斷容易性、或均勻切斷性等)。 [先前技術文獻] [專利文獻]In the method of obtaining semiconductor wafers for die bonding using the above-mentioned die-cut die-bonding film, Patent Document 1 discloses: by using a die-cut tape with specific physical properties (the initial elastic modulus at -10°C is 200 MPa or more) And below 380MPa and Tanδ (loss modulus of elasticity/storage modulus) at -10℃ is above 0.080 and below 0.3), and carry out the above expansion step under the low temperature condition of -15~5℃, in the above In the expanding step, the cutting performance from the semiconductor wafer to a plurality of semiconductor wafers can be improved (for example, the ease of cutting, or the uniform cutting performance, etc.). [Prior Technical Literature] [Patent Literature]

[專利文獻1]日本專利特開2015-185591號公報[Patent Document 1] Japanese Patent Laid-Open No. 2015-185591

[發明所欲解決之問題][The problem to be solved by the invention]

如專利文獻1所記載，藉由使用具有特定物性之切晶帶且於上述低溫條件下進行上述擴開步驟，上述半導體晶圓之切斷性提高，但於使用切晶帶及切晶黏晶膜於低溫條件下藉由擴開將半導體晶圓切斷為複數個半導體晶片之情形時，迫切期望更進一步提高上述半導體晶圓之切斷性。 尤其是於將半導體晶圓切斷為複數個小型半導體晶片(例如大小為長度12 mm×寬度4 mm×厚度0.055 mm之半導體晶片)之情形時，迫切期望更進一步提高上述半導體晶圓之切斷性。As described in Patent Document 1, by using a dicing tape with specific physical properties and performing the expansion step under the above-mentioned low temperature conditions, the cutting performance of the semiconductor wafer is improved, but when the dicing tape and the dicing die are used When the film is expanded to cut the semiconductor wafer into a plurality of semiconductor wafers under low temperature conditions, it is strongly desired to further improve the cutting performance of the semiconductor wafer. Especially when cutting a semiconductor wafer into a plurality of small semiconductor wafers (for example, a semiconductor wafer with a size of 12 mm in length × 4 mm in width × 0.055 mm in thickness), there is an urgent desire to further improve the cutting of the semiconductor wafer. Sex.

因此，本發明之課題在於提供一種可更進一步提高於低溫條件下基於擴開之自半導體晶圓向複數個半導體晶片之切斷性之切晶帶及切晶黏晶膜。 [解決問題之技術手段]Therefore, the subject of the present invention is to provide a dicing tape and a dicing die-attach film that can further improve the cutting performance from a semiconductor wafer to a plurality of semiconductor wafers based on expansion under low temperature conditions. [Technical means to solve the problem]

本發明之切晶帶係 於基材層上積層黏著劑層而成者，且 該切晶帶之-5℃下之拉伸儲存模數為100 MPa以上。The slicing tape system of the present invention It is formed by laminating an adhesive layer on the substrate layer, and The tensile storage modulus at -5°C of the dicing tape is more than 100 MPa.

於上述切晶帶中，較佳為 -5℃下之30%拉伸應力為5.5 N/10 mm以上。Among the above-mentioned dicing tapes, preferably The 30% tensile stress at -5℃ is 5.5 N/10 mm or more.

於上述切晶帶中，較佳為 室溫下之30%拉伸應力為3.2 N/10 mm以上。Among the above-mentioned dicing tapes, preferably The 30% tensile stress at room temperature is 3.2 N/10 mm or more.

於上述切晶帶中，較佳為 -5℃下之30%拉伸應力相對於室溫下之30%拉伸應力之比為1.7以上。Among the above-mentioned dicing tapes, preferably The ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 1.7 or more.

本發明之切晶黏晶膜具備： 於基材層上積層黏著劑層而成之切晶帶、及 積層於上述切晶帶之黏著劑層上之黏晶層，且 該切晶黏晶膜之-5℃下之拉伸儲存模數為100 MPa以上。The diced chip adhesive film of the present invention has: Die-cutting tape formed by laminating an adhesive layer on the substrate layer, and A die-bonding layer laminated on the adhesive layer of the above-mentioned die-cutting tape, and The tensile storage modulus at -5°C of the diced sticky film is more than 100 MPa.

以下對本發明之一實施方式進行說明。Hereinafter, an embodiment of the present invention will be described.

[切晶帶] 如圖1所示，本實施方式之切晶帶10係於基材層1上積層黏著劑層2而成者，且-5℃下之拉伸儲存模數為100 MPa以上。[Cut Crystal Strip] As shown in FIG. 1, the dicing tape 10 of this embodiment is formed by laminating an adhesive layer 2 on a substrate layer 1, and the tensile storage modulus at -5° C. is 100 MPa or more.

關於藉由使-5℃下之切晶帶10之拉伸儲存模數為100 MPa以上而貼附於切晶帶10之半導體晶圓之切斷性提高之原因，認為如下。 為了提高貼附於切晶帶10之半導體晶圓之藉由擴開而切斷為複數個半導體晶片之切斷性(例如切斷容易性或均勻切斷性等)，需要於開始切斷半導體晶圓時對切晶帶10整體充分地施加拉伸力。 此處，認為於切斷開始時切晶帶10相對較軟之情形時，即切晶帶10之拉伸儲存模數相對較小之情形時，切斷開始時之拉伸力會隨著自切晶帶10之外周緣部分向中央部分靠近而被切晶帶10吸收從而逐漸變小。因此認為，難以將切斷開始時之拉伸力充分地施加於切晶帶10整體。 與此相對，本實施方式之切晶帶10具有100 MPa以上之相對較大之拉伸儲存模數，因此認為，切斷開始時之拉伸力不易隨著自切晶帶10之外周緣部分向中央部分靠近而被切晶帶10吸收。因此，切斷開始時之拉伸力充分地施加於切晶帶10整體，其結果為，認為容易將半導體晶圓切斷為複數個半導體晶片，並且容易獲得相對均勻地被切斷之半導體晶片，即，可更進一步提高自半導體晶圓向複數個半導體晶片之切斷性。The reason for the improvement in the cutting performance of the semiconductor wafer attached to the dicing tape 10 by setting the tensile storage modulus of the dicing tape 10 at -5° C. to 100 MPa or more is considered as follows. In order to improve the cutting performance of the semiconductor wafer attached to the dicing tape 10 and cut into a plurality of semiconductor wafers by expanding it (for example, the ease of cutting or uniform cutting), it is necessary to cut the semiconductor at the beginning A sufficient tensile force is applied to the entire dicing tape 10 during wafering. Here, it is considered that when the dicing tape 10 is relatively soft at the beginning of cutting, that is, when the tensile storage modulus of the dicing tape 10 is relatively small, the tensile force at the beginning of the cutting will increase with the self The outer peripheral part of the dicing band 10 approaches the central part and is absorbed by the dicing band 10 and gradually becomes smaller. Therefore, it is considered that it is difficult to sufficiently apply the tensile force at the start of cutting to the entire dicing tape 10. In contrast, the crystal cutting tape 10 of the present embodiment has a relatively large tensile storage modulus of 100 MPa or more. Therefore, it is considered that the tensile force at the beginning of cutting is unlikely to follow the outer peripheral portion of the crystal cutting tape 10 It approaches the central part and is absorbed by the dicing tape 10. Therefore, the tensile force at the start of cutting is sufficiently applied to the entire dicing tape 10, as a result, it is considered that the semiconductor wafer is easily cut into a plurality of semiconductor wafers, and it is easy to obtain a relatively uniformly cut semiconductor wafer That is, the cutting performance from the semiconductor wafer to a plurality of semiconductor wafers can be further improved.

再者，如後述實施例之項中所說明，藉由使切晶帶10之-5℃下之拉伸儲存模數為100 MPa以上，尤其是可更進一步提高將半導體晶圓(例如直徑200 mm(8英吋)之半導體晶圓)切斷為小型半導體晶片(例如長度12 mm×寬度4 mm×厚度0.55 mm)時之切斷性。 關於其原因，本發明人等推測如下。 於切斷大小相同之半導體晶圓之情形時，切斷後之半導體晶片之尺寸越小，則半切割步驟中形成於半導體晶圓之槽(線)之間隔變得越窄，因此於半導體晶圓上所形成之槽之數量變多。其結果為，擴開步驟中之槽之伸長率降低。 因此，於擴開步驟中，將半導體晶圓切斷為小型半導體晶片時，為了抑制發生切斷不良而需要以更低之伸長率來產生高應力。 此處，彈性模數意指拉伸基材層時之應力相對於伸長率(應變量)之斜率，因此認為，彈性模數較高時，可以更低之伸長率來產生高應力。 並且，就於使用切晶帶10之擴開步驟中，將半導體晶圓切斷為複數個小型半導體晶片時之切斷性良好，且切晶帶10不易因拉伸力而發生破裂之觀點而言，最佳為採用-5℃之溫度來進行擴開，因此認為，藉由將-5℃下之拉伸儲存模數設為100 MPa以上之相對較高之值，可以更低之伸長率來產生高應力。 關於其結果，本發明人等推測可更進一步提高將半導體晶圓切斷為小型半導體晶片時之切斷性。Furthermore, as explained in the following embodiments, by making the tensile storage modulus of the dicing tape 10 at -5°C to be 100 MPa or more, in particular, the semiconductor wafer (for example, the diameter of 200 mm (8-inch) semiconductor wafers) are cut into small semiconductor wafers (for example, 12 mm in length × 4 mm in width × 0.55 mm in thickness). As for the reason, the inventors of the present invention speculate as follows. In the case of cutting semiconductor wafers of the same size, the smaller the size of the semiconductor wafer after cutting, the narrower the spacing of the grooves (lines) formed in the semiconductor wafer in the half-cutting step. Therefore, the semiconductor wafer The number of grooves formed on the upper surface increases. As a result, the elongation of the groove in the expanding step decreases. Therefore, when cutting the semiconductor wafer into small semiconductor wafers in the expanding step, it is necessary to generate high stress with a lower elongation in order to suppress the occurrence of cutting failure. Here, the elastic modulus refers to the slope of the stress relative to the elongation (strain amount) when the substrate layer is stretched. Therefore, it is believed that when the elastic modulus is higher, a lower elongation can be used to generate high stress. In addition, in the expanding step using the dicing tape 10, the cutting performance when the semiconductor wafer is cut into a plurality of small semiconductor wafers is good, and the dicing tape 10 is not easily broken due to tensile force. In other words, it is best to use a temperature of -5°C for expansion. Therefore, it is believed that by setting the tensile storage modulus at -5°C to a relatively high value above 100 MPa, lower elongation can be achieved. To generate high stress. Regarding the results, the inventors of the present invention speculate that the cutting performance when cutting a semiconductor wafer into a small semiconductor wafer can be further improved.

本實施方式之切晶帶10較佳為-5℃下之拉伸儲存模數為400 MPa以下。 藉此，對切晶帶10整體施加充分之拉伸力，並且使切晶帶10變得相對容易伸長，因此可抑制將貼附於切晶帶10之半導體晶圓切斷為半導體晶片時由拉伸力導致之切晶帶10之破裂，並且更進一步提高自半導體晶圓向複數個半導體晶片之切斷性。 又，藉由使-5℃下之拉伸儲存模數為400 MPa以下，尤其是可更進一步提高自半導體晶圓向複數個小型半導體晶片之切斷性。The dicing tape 10 of this embodiment preferably has a tensile storage modulus at -5°C of 400 MPa or less. By this, a sufficient tensile force is applied to the entire dicing tape 10, and the dicing tape 10 becomes relatively easy to elongate, so it is possible to prevent the semiconductor wafer attached to the dicing tape 10 from being cut into semiconductor wafers. The tensile force causes the breakage of the dicing tape 10, and further improves the cutting performance from the semiconductor wafer to a plurality of semiconductor wafers. In addition, by making the tensile storage modulus at -5°C below 400 MPa, in particular, the cutting performance from a semiconductor wafer to a plurality of small semiconductor wafers can be further improved.

-5℃下之拉伸儲存模數可以如下方式求出。 詳細而言，將長度40 mm(測定長度)、寬度10 mm之切晶帶作為試驗片，使用固體黏彈性測定裝置(例如型號RSAIII、Rheometric Scientific股份有限公司製)，於頻率1 Hz、應變量0.1%、升溫速度10℃/分鐘、治具間距離22.5 mm之條件下，在-50〜100℃之溫度範圍內測定上述試驗片之拉伸儲存模數。此時，可藉由讀取-5℃下之值而求出。 再者，上述測定係藉由於MD方向(樹脂流動方向)上拉伸上述試驗片來進行。The tensile storage modulus at -5°C can be calculated as follows. Specifically, a dicing tape with a length of 40 mm (measurement length) and a width of 10 mm is used as a test piece, and a solid viscoelasticity measuring device (for example, model RSAIII, manufactured by Rheometric Scientific Co., Ltd.) is used at a frequency of 1 Hz and a strain amount. Measure the tensile storage modulus of the above test piece in the temperature range of -50~100℃ under the conditions of 0.1%, heating rate 10℃/min, and distance between fixtures 22.5 mm. In this case, it can be obtained by reading the value at -5°C. In addition, the above-mentioned measurement was performed by stretching the above-mentioned test piece in the MD direction (resin flow direction).

本實施方式之切晶帶10較佳為-5℃下之30%拉伸應力為5.5 N/10 mm以上。The dicing tape 10 of this embodiment preferably has a 30% tensile stress at -5° C. of 5.5 N/10 mm or more.

本實施方式之切晶帶10較佳為-5℃下之30%拉伸應力為30 N/10 mm以下。 由此，於擴開中對切晶帶10整體施加充分之拉伸力，並且使切晶帶10變得相對容易伸長，因此，於對貼附於半導體晶圓之切晶帶10進行擴開而將上述半導體晶圓切斷為半導體晶片之期間，可抑制由擴開導致之切晶帶破裂，並且更進一步提高自半導體晶圓向複數個半導體晶片之切斷性。 又，藉由使-5℃下之30%拉伸應力為30 N/10 mm以下，尤其是可更進一步提高自半導體晶圓向複數個小型之半導體晶片之切斷性。The dicing tape 10 of this embodiment preferably has a 30% tensile stress at -5°C of 30 N/10 mm or less. As a result, sufficient tensile force is applied to the entire dicing tape 10 during expansion, and the dicing tape 10 becomes relatively easy to elongate. Therefore, the dicing tape 10 attached to the semiconductor wafer is expanded. During the cutting of the above-mentioned semiconductor wafer into semiconductor wafers, it is possible to suppress the breakage of the dicing band caused by the expansion, and to further improve the cutting performance from the semiconductor wafer to a plurality of semiconductor wafers. In addition, by setting the 30% tensile stress at -5°C to 30 N/10 mm or less, it is possible to further improve the cutting performance from a semiconductor wafer to a plurality of small semiconductor wafers.

本實施方式之切晶帶10較佳為室溫(23℃)下之30%拉伸應力為3.2 N/10 mm以上。The dicing tape 10 of this embodiment preferably has a 30% tensile stress at room temperature (23° C.) of 3.2 N/10 mm or more.

室溫(23℃)下之30%拉伸應力較佳為30 N/10 mm以下。 由此，於擴開中對切晶帶10整體施加充分之拉伸力，並且使切晶帶10變得相對容易伸長，因此，於對貼附於半導體晶圓之切晶帶10進行擴開而將上述半導體晶圓切斷為半導體晶片之期間，可抑制由擴開導致之切晶帶破裂，並且更進一步提高自半導體晶圓向複數個半導體晶片之切斷性。 又，藉由將室溫下之30%拉伸應力設為30 N/10 mm以下，尤其是可更進一步提高自半導體晶圓向複數個小型半導體晶片之切斷性。The 30% tensile stress at room temperature (23°C) is preferably 30 N/10 mm or less. As a result, sufficient tensile force is applied to the entire dicing tape 10 during expansion, and the dicing tape 10 becomes relatively easy to elongate. Therefore, the dicing tape 10 attached to the semiconductor wafer is expanded. During the cutting of the above-mentioned semiconductor wafer into semiconductor wafers, it is possible to suppress the breakage of the dicing band caused by the expansion, and to further improve the cutting performance from the semiconductor wafer to a plurality of semiconductor wafers. In addition, by setting the 30% tensile stress at room temperature to 30 N/10 mm or less, in particular, the cutting performance from the semiconductor wafer to a plurality of small semiconductor wafers can be further improved.

-5℃及室溫下之30%拉伸應力可以如下方式求出。 詳細而言，可藉由如下方式求出：將長度100 mm、寬度10 mm之切晶帶作為試驗片，使用拉伸試驗機(Tensilon萬能試驗機、島津製作所製)，於測定溫度(-5℃及室溫(23℃±1℃)下，在治具間距離50 mm及拉伸速度100 mm/分鐘之條件下拉伸上述試驗片，測定伸長率達到30%時(治具間距離65 mm)之應力。 再者，上述測定係藉由於MD方向(樹脂流動方向)上拉伸上述試驗片來進行。The 30% tensile stress at -5°C and room temperature can be calculated as follows. In detail, it can be determined by the following method: using a slicing tape with a length of 100 mm and a width of 10 mm as a test piece, using a tensile testing machine (Tensilon universal testing machine, manufactured by Shimadzu Corporation), and measuring the temperature (-5 ℃ and room temperature (23℃±1℃), stretch the above test piece under the conditions of 50 mm distance between jigs and 100 mm/min tensile speed, and measure the elongation when it reaches 30% (distance between jigs 65 mm) stress. In addition, the above-mentioned measurement was performed by stretching the above-mentioned test piece in the MD direction (resin flow direction).

本實施方式之切晶帶10較佳為-5℃下之30%拉伸應力相對於室溫下之30%拉伸應力之比為1.7以上。The dicing tape 10 of the present embodiment preferably has a ratio of 30% tensile stress at -5° C. to 30% tensile stress at room temperature of 1.7 or more.

本實施方式之切晶帶10較佳為-5℃下之30%拉伸應力相對於室溫下之30%拉伸應力之比為3.0以下。 由此，於擴開中對切晶帶10整體施加充分之拉伸力，並且使切晶帶10變得相對容易伸長，因此，於對貼附於半導體晶圓之切晶帶10進行擴開而將上述半導體晶圓切斷為半導體晶片之期間，可抑制由擴開導致之切晶帶破裂，並且更進一步地提高自半導體晶圓向複數個半導體晶片之切斷性。 又，藉由使-5℃下之30%拉伸應力相對於室溫下之30%拉伸應力之比為3.0以下，尤其是可更進一步地提高自半導體晶圓向複數個小型半導體晶片之切斷性。The dicing tape 10 of the present embodiment preferably has a ratio of 30% tensile stress at -5° C. to 30% tensile stress at room temperature of 3.0 or less. As a result, sufficient tensile force is applied to the entire dicing tape 10 during expansion, and the dicing tape 10 becomes relatively easy to elongate. Therefore, the dicing tape 10 attached to the semiconductor wafer is expanded. During the cutting of the above-mentioned semiconductor wafer into semiconductor wafers, it is possible to suppress the breakage of the dicing band caused by the expansion, and to further improve the cutting performance from the semiconductor wafer to a plurality of semiconductor wafers. In addition, by setting the ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature to be 3.0 or less, in particular, it is possible to further increase the transfer rate from a semiconductor wafer to a plurality of small semiconductor wafers. Cut off.

基材層1支持黏著劑層2。基材層1包含樹脂。作為基材層1中所含之樹脂，可列舉聚烯烴、聚酯、聚胺酯、聚碳酸酯、聚醚醚酮、聚醯亞胺、聚醚醯亞胺、聚醯胺、全芳香族聚醯胺、聚氯乙烯、聚偏二氯乙烯、聚苯硫醚、氟樹脂、纖維素系樹脂及聚矽氧樹脂等。The base layer 1 supports the adhesive layer 2. The base material layer 1 contains resin. Examples of the resin contained in the base layer 1 include polyolefin, polyester, polyurethane, polycarbonate, polyether ether ketone, polyimide, polyetherimide, polyamide, and wholly aromatic polyamide. Amine, polyvinyl chloride, polyvinylidene chloride, polyphenylene sulfide, fluororesin, cellulose resin, polysiloxane resin, etc.

作為聚烯烴，例如可列舉α-烯烴之均聚物、兩種以上之α-烯烴之共聚物、嵌段聚丙烯、無規聚丙烯、一種或兩種以上之α-烯烴與其他乙烯基單體之共聚物等。Examples of polyolefins include homopolymers of α-olefins, copolymers of two or more kinds of α-olefins, block polypropylene, random polypropylene, one or more kinds of α-olefins, and other vinyl monomers. Body copolymers, etc.

作為α-烯烴之均聚物，較佳為碳數2以上且12以下之α-烯烴之均聚物。作為此種均聚物，可列舉乙烯、丙烯、1-丁烯、4-甲基-1-戊烯等。As the homopolymer of α-olefin, a homopolymer of α-olefin having a carbon number of 2 or more and 12 or less is preferable. As such a homopolymer, ethylene, propylene, 1-butene, 4-methyl-1-pentene, etc. are mentioned.

作為兩種以上之α-烯烴之共聚物，可列舉：乙烯/丙烯共聚物、乙烯/1-丁烯共聚物、乙烯/丙烯/1-丁烯共聚物、乙烯/碳數5以上且12以下之α-烯烴共聚物、丙烯/乙烯共聚物、丙烯/1-丁烯共聚物、丙烯/碳數5以上且12以下之α-烯烴共聚物等。Examples of copolymers of two or more α-olefins include: ethylene/propylene copolymer, ethylene/1-butene copolymer, ethylene/propylene/1-butene copolymer, ethylene/carbon number 5 to 12 Α-olefin copolymers, propylene/ethylene copolymers, propylene/1-butene copolymers, propylene/α-olefin copolymers with 5 to 12 carbon atoms, etc.

作為一種或兩種以上之α-烯烴與其他乙烯基單體之共聚物，可列舉乙烯-乙酸乙烯酯共聚物(EVA)等。As a copolymer of one or two or more α-olefins and other vinyl monomers, ethylene-vinyl acetate copolymer (EVA) and the like can be cited.

聚烯烴亦可為被稱為α-烯烴系熱塑性彈性體者。作為α-烯烴系熱塑性彈性體，可列舉：組合丙烯-乙烯共聚物與丙烯均聚物而成者、或丙烯-乙烯-碳數4以上之α-烯烴三元共聚物。 作為α-烯烴系熱塑性彈性體之市售品，例如可列舉作為丙烯系彈性體樹脂之Vistamaxx3980(ExxonMobil Chemical公司製)。The polyolefin may also be what is called an α-olefin-based thermoplastic elastomer. Examples of the α-olefin-based thermoplastic elastomer include a combination of a propylene-ethylene copolymer and a propylene homopolymer, or a propylene-ethylene-α-olefin terpolymer having a carbon number of 4 or more. Examples of commercially available products of α-olefin-based thermoplastic elastomers include Vistamaxx 3980 (manufactured by ExxonMobil Chemical Co., Ltd.) which is a propylene-based elastomer resin.

基材層1可包含一種上述樹脂，亦可包含兩種以上之上述樹脂。 再者，於黏著劑層2包含後述之紫外線硬化黏著劑之情形時，基材層1較佳為以具有紫外線透過性之方式構成。The base material layer 1 may contain one kind of the above-mentioned resin, or two or more kinds of the above-mentioned resin. Furthermore, when the adhesive layer 2 contains an ultraviolet curable adhesive described later, the base layer 1 is preferably configured to have ultraviolet light permeability.

基材層1可為單層構造，亦可為積層構造。基材層1可藉由非拉伸成形而獲得，亦可藉由拉伸成形而獲得，較佳為藉由拉伸成形而獲得。於基材層1為積層構造之情形時，基材層1較佳為具有包含彈性體之層(以下稱為彈性體層)及包含非彈性體之層(以下稱為非彈性體層)。 藉由將基材層1設為具有彈性體層及非彈性體層者，可使彈性體層作為緩和拉伸應力之應力緩和層發揮功能。即， 可相對減小基材層1中所產生之拉伸應力，因此可使基材層1具有適度硬度並且相對容易伸長。 藉此，可提高自半導體晶圓向複數個半導體晶片之切斷性。 又，於切斷步驟中之擴開時，可抑制基材層1破裂而發生破損。 再者，於本說明書中，彈性體層意指室溫下之拉伸儲存模數低於非彈性體層之低彈性模數層。作為彈性體層，可列舉室溫下之拉伸儲存模數為10 MPa以上且100 MPa以下者，作為非彈性體層，可列舉室溫下之拉伸儲存模數為200 MPa以上且500 MPa以下者。The base material layer 1 may have a single-layer structure or a multilayer structure. The base material layer 1 may be obtained by non-stretch forming, or may be obtained by stretch forming, and is preferably obtained by stretch forming. When the base material layer 1 has a laminated structure, the base material layer 1 preferably has a layer containing an elastomer (hereinafter referred to as an elastomer layer) and a layer containing a non-elastomeric body (hereinafter referred to as a non-elastomeric layer). By setting the base material layer 1 to have an elastomer layer and a non-elastomeric layer, the elastomer layer can function as a stress relaxation layer that relaxes tensile stress. That is, the tensile stress generated in the base layer 1 can be relatively reduced, so the base layer 1 can be made to have moderate hardness and relatively easy to elongate. Thereby, the cutting performance from the semiconductor wafer to a plurality of semiconductor wafers can be improved. In addition, at the time of spreading in the cutting step, it is possible to prevent the base layer 1 from cracking and breaking. Furthermore, in this specification, the elastomer layer means a low elastic modulus layer whose tensile storage modulus at room temperature is lower than that of the non-elastomeric layer. As the elastomer layer, one with a tensile storage modulus of 10 MPa or more and 100 MPa or less at room temperature can be mentioned, and as a non-elastomeric layer, one having a tensile storage modulus of 200 MPa or more and 500 MPa or less at room temperature can be mentioned. .

彈性體層可包含一種彈性體，亦可包含兩種以上之彈性體，較佳為包含α-烯烴系熱塑性彈性體。 非彈性體層可包含一種非彈性體，亦可包含兩種以上之非彈性體，較佳為包含後述之茂金屬PP。 於基材層1具有彈性體層及非彈性體層之情形時，基材層1較佳為形成為以彈性體層為中心層且於該中心層之相互對向之兩面具有非彈性體層的三層構造(非彈性體層/彈性體層/非彈性體層)(參照圖1)。再者，於圖1中，將一個非彈性體層表示為第1樹脂層1a、將彈性體層表示為第2樹脂層1b、將另一個非彈性體層表示為第3樹脂層3c。The elastomer layer may include one type of elastomer or two or more types of elastomers, and preferably includes an α-olefin-based thermoplastic elastomer. The non-elastomeric layer may include one type of non-elastomeric body or two or more types of non-elastomeric body, and preferably contains the metallocene PP described later. When the base layer 1 has an elastomer layer and a non-elastomeric layer, the base layer 1 is preferably formed in a three-layer structure with the elastomer layer as the center layer and non-elastomeric layers on opposite sides of the center layer. (Non-elastomeric layer/elastomeric layer/non-elastomeric layer) (refer to Fig. 1). In addition, in FIG. 1, one non-elastomeric layer is shown as the 1st resin layer 1a, the elastomer layer is shown as the 2nd resin layer 1b, and the other non-elastomeric layer is shown as the 3rd resin layer 3c.

又，由於如上所述，於切口維持步驟中，使熱風(例如100〜130℃)對準室溫(例如23℃)下維持在擴開狀態之上述切晶黏晶膜以使上述切晶黏晶膜熱收縮後進行冷卻固化，故基材層1之最外層較佳為包含具有接近於對準切晶帶之熱風溫度之熔點之樹脂。藉此，可使因對著熱風而熔融之最外層更迅速地固化。 其結果為，於切口維持步驟中，可更充分地維持切口。In addition, as described above, in the incision maintaining step, the hot air (for example, 100~130°C) is aligned with the room temperature (for example, 23°C) to maintain the diced chip sticking film in an expanded state to make the sliced chip sticky. The crystal film is heat-shrinked and then cooled and solidified. Therefore, the outermost layer of the substrate layer 1 preferably contains a resin having a melting point close to the temperature of the hot air aligned with the dicing belt. Thereby, the outermost layer melted by facing the hot air can be solidified more quickly. As a result, in the incision maintaining step, the incision can be maintained more sufficiently.

於基材層1為彈性體層與非彈性體層之積層構造並且彈性體層包含α-烯烴系熱塑性彈性體且非彈性體層包含後述之茂金屬PP等聚烯烴的情形時，較佳為彈性體層相對於形成該彈性體層之彈性體之總質量，包含50質量%以上且100質量%以下之α-烯烴系熱塑性彈性體，更佳為包含70質量%以上且100質量%以下，進而較佳為包含80質量%以上且100質量%以下，尤佳為包含90質量%以上且100質量%以下，最佳為包含95質量%以上且100質量%以下。藉由以上述範圍包含α-烯烴系熱塑性彈性體，彈性體層與非彈性體層之親和性提高，因此可相對容易地將基材層1擠出成形。又，可使彈性體層作為應力緩和層發揮作用，因此可將貼附於切晶帶之半導體晶圓高效率地切斷。When the base material layer 1 has a laminated structure of an elastomer layer and a non-elastomeric layer, the elastomer layer contains an α-olefin-based thermoplastic elastomer and the non-elastomeric layer contains polyolefins such as metallocene PP, which will be described later, the elastomer layer is preferably relative to The total mass of the elastomer forming the elastomer layer includes 50% by mass or more and 100% by mass or less of α-olefin-based thermoplastic elastomer, more preferably 70% by mass or more and 100% by mass or less, and more preferably 80% by mass. Mass% or more and 100 mass% or less, more preferably 90 mass% or more and 100 mass% or less, and most preferably 95 mass% or more and 100 mass% or less. By including the α-olefin-based thermoplastic elastomer in the above-mentioned range, the affinity between the elastomer layer and the non-elastomeric layer is improved, so that the substrate layer 1 can be extrusion-molded relatively easily. In addition, the elastomer layer can function as a stress relaxation layer, so that the semiconductor wafer attached to the dicing tape can be cut efficiently.

於基材層1為彈性體層與非彈性體層之積層構造之情形時，基材層1較佳為藉由共擠出成形而獲得，上述共擠出成形係將彈性體與非彈性體共擠出而製成彈性體層與非彈性體層之積層構造。作為共擠出成形，可採用於製造膜或片等時通常進行之任意適當之共擠出成形。於共擠出成形中，就可高效率且廉價地獲得基材層1之方面而言，較佳為採用吹脹法或共擠出T模法。When the base material layer 1 has a laminated structure of an elastomer layer and a non-elastomeric layer, the base material layer 1 is preferably obtained by co-extrusion molding. The aforementioned co-extrusion molding system co-extrudes the elastomer and the non-elastomeric layer. It is made into a laminated structure of elastomer layer and non-elastomeric layer. As the co-extrusion molding, any appropriate co-extrusion molding that is usually performed in the production of films, sheets, etc. can be adopted. In the co-extrusion molding, it is preferable to use an inflation method or a co-extrusion T-die method in terms of obtaining the base material layer 1 efficiently and inexpensively.

於藉由共擠出成形獲得呈積層構造之基材層1之情形時，上述彈性體層與上述非彈性體層於被加熱而熔融之狀態下相接觸，因此較佳為上述彈性體與上述非彈性體之熔點差較小。藉由使熔點差較小，可抑制對成為低熔點之上述彈性體或上述非彈性體之任一者施加過度之熱，因此可抑制因成為低熔點之上述彈性體或上述非彈性體之任一者發生熱劣化而生成副產物。又，亦可抑制因成為低熔點之上述彈性體或上述非彈性體之任一者之黏度過度下降而於上述彈性體層與上述非彈性體層之間產生積層不良。上述彈性體與上述非彈性體之熔點差較佳為0℃以上且70℃以下，更佳為0℃以上且55℃以下。 上述彈性體及上述非彈性體之熔點可藉由示差掃描熱量(DSC)分析來測定。例如可藉由如下方式進行測定：使用示差掃描熱量計裝置(TAINSTRUMENTS公司製之型號DSC Q2000)，於氮氣氣流下以升溫速度5℃/分鐘升溫至200℃，求出吸熱峰之峰值溫度。When the base material layer 1 having a laminated structure is obtained by coextrusion, the elastomer layer and the non-elastomeric layer are in contact with each other while being heated and melted. Therefore, it is preferable that the elastomer and the non-elastomeric layer are in contact with each other while being heated and melted. The melting point difference of the body is relatively small. By making the difference in melting point small, it is possible to prevent excessive heat from being applied to any one of the elastomer or non-elastomer which has a low melting point. Therefore, it is possible to suppress any of the elastomer or non-elastomer which has a low melting point. One is thermally degraded to produce by-products. In addition, it is also possible to suppress the occurrence of build-up defects between the elastomer layer and the non-elastomeric layer due to an excessive decrease in the viscosity of either the elastomer or the non-elastomeric body, which has a low melting point. The difference in melting point between the elastomer and the non-elastomeric body is preferably 0°C or more and 70°C or less, more preferably 0°C or more and 55°C or less. The melting point of the above-mentioned elastomer and the above-mentioned non-elastomeric body can be determined by differential scanning calorimetry (DSC) analysis. For example, the measurement can be performed by using a differential scanning calorimeter device (Model DSC Q2000 manufactured by TAINSTRUMENTS) under nitrogen gas flow at a heating rate of 5°C/min to 200°C to obtain the peak temperature of the endothermic peak.

基材層1之厚度較佳為55 μm以上且195 μm以下，更佳為55 μm以上且190 μm以下，進而較佳為55 μm以上且170 μm以下，最佳為60 μm以上且160 μm以下。藉由將基材層1之厚度設為上述範圍，可高效率地製造切晶帶，且可高效率地切斷貼附於切晶帶之半導體晶圓。 基材層1之厚度例如可藉由如下方式求出：使用度盤規(PEACOCK公司製之型號R-205)測定隨機選擇之任意5處之厚度，並對該等厚度進行算術平均。The thickness of the substrate layer 1 is preferably 55 μm or more and 195 μm or less, more preferably 55 μm or more and 190 μm or less, still more preferably 55 μm or more and 170 μm or less, most preferably 60 μm or more and 160 μm or less . By setting the thickness of the base material layer 1 in the above-mentioned range, the dicing tape can be manufactured efficiently, and the semiconductor wafer attached to the dicing tape can be cut efficiently. The thickness of the base material layer 1 can be obtained, for example, by measuring the thickness at any five randomly selected locations using a dial gauge (model R-205 manufactured by PEACOCK), and arithmetically averaged these thicknesses.

於將彈性體層與非彈性體層積層而成之基材層1中，非彈性體層之厚度相對於彈性體層之厚度之比較佳為1/25以上且1/3以下，更佳為1/25以上且1/3.5以下，進而較佳為1/25以上且1/4，尤佳為1/22以上且1/4以下，最佳為1/20以上且1/4以下。藉由將非彈性體層之厚度相對於彈性體層之厚度之比設為上述範圍，可更高效率地切斷貼附於切晶帶之半導體晶圓。In the base material layer 1 formed by laminating an elastomer layer and a non-elastomeric layer, the thickness of the non-elastomeric layer relative to the thickness of the elastomer layer is preferably 1/25 or more and 1/3 or less, more preferably 1/25 or more And 1/3.5 or less, more preferably 1/25 or more and 1/4, particularly preferably 1/22 or more and 1/4 or less, most preferably 1/20 or more and 1/4 or less. By setting the ratio of the thickness of the non-elastomeric layer to the thickness of the elastomeric layer in the above range, the semiconductor wafer attached to the dicing tape can be cut more efficiently.

彈性體層可為單層(1層)構造，亦可為積層構造。彈性體層較佳為1層〜5層構造，更佳為1層〜3層構造，進而較佳為1層〜2層構造，最佳為1層構造。於彈性體層為積層構造之情形時，可所有層包含相同之彈性體，亦可至少2層包含不同之彈性體。The elastomer layer may have a single-layer (one-layer) structure or a multilayer structure. The elastomer layer preferably has a 1-layer to 5-layer structure, more preferably a 1-layer to 3-layer structure, further preferably a 1-layer to 2-layer structure, and most preferably a 1-layer structure. When the elastomer layer has a laminated structure, all layers may contain the same elastomer, or at least two layers may contain different elastomers.

非彈性體層可為單層(1層)構造，亦可為積層構造。非彈性體層較佳為1層〜5層構造，更佳為1層〜3層構造，進而較佳為1層〜2層構造，最佳為1層構造。於非彈性體層為積層構造之情形時，可所有層包含相同之非彈性體，亦可至少2層包含不同之非彈性體。The non-elastomeric layer may have a single-layer (one-layer) structure or a multilayer structure. The non-elastomeric layer preferably has a 1-layer to 5-layer structure, more preferably a 1-layer to 3-layer structure, further preferably a 1-layer to 2-layer structure, and most preferably a 1-layer structure. When the non-elastomeric layer has a laminated structure, all layers may contain the same non-elastomeric body, or at least two layers may contain different non-elastomeric bodies.

非彈性體層較佳為包含作為利用茂金屬觸媒所得之聚合產物之聚丙烯樹脂(以下稱為茂金屬PP)來作為非彈性體。作為茂金屬PP，可列舉作為茂金屬觸媒之聚合產物之丙烯/α-烯烴共聚物。藉由使非彈性體層包含茂金屬PP，可高效率地製造切晶帶，且可高效率地切斷貼附於切晶帶之半導體晶圓。 再者，作為市售之茂金屬PP，可列舉WINTEC WXK1233、 WINTEC WMX03(均為日本聚丙烯公司製)。The non-elastomeric layer preferably contains as a non-elastomeric polypropylene resin (hereinafter referred to as metallocene PP) as a polymerization product obtained by using a metallocene catalyst. As the metallocene PP, a propylene/α-olefin copolymer which is a polymerization product of a metallocene catalyst can be cited. By including the metallocene PP in the non-elastomeric layer, the dicing tape can be manufactured efficiently, and the semiconductor wafer attached to the dicing tape can be cut efficiently. In addition, as commercially available metallocene PP, WINTEC WXK1233 and WINTEC WMX03 (all manufactured by Nippon Polypropylene Co., Ltd.) can be cited.

此處，茂金屬觸媒係包含週期表第4族之過渡金屬化合物(所謂茂金屬化合物)及輔觸媒之觸媒，上述週期表第4族之過渡金屬化合物包含具有環戊二烯基骨架之配位基，上述輔觸媒可與茂金屬化合物反應而將該茂金屬化合物活化為穩定之離子狀態，且視需要，上述茂金屬觸媒包含有機鋁化合物。茂金屬化合物係可實現丙烯之立體規則性聚合之交聯型茂金屬化合物。Here, the metallocene catalyst includes a transition metal compound (so-called metallocene compound) and co-catalyst of Group 4 of the Periodic Table. The transition metal compound of Group 4 of the Periodic Table includes a catalyst having a cyclopentadienyl skeleton. The co-catalyst can react with the metallocene compound to activate the metallocene compound into a stable ionic state, and if necessary, the metallocene catalyst includes an organoaluminum compound. The metallocene compound is a cross-linked metallocene compound that can realize the stereoregular polymerization of propylene.

於上述作為茂金屬觸媒之聚合產物之丙烯/α-烯烴共聚物中，較佳為作為茂金屬觸媒之聚合產物之丙烯/α-烯烴無規共聚物，於上述作為茂金屬觸媒之聚合產物之丙烯/α-烯烴無規共聚物中，較佳為選自作為茂金屬觸媒之聚合產物之丙烯/碳數2之α-烯烴無規共聚物、作為茂金屬觸媒之聚合產物之丙烯/碳數4之α-烯烴無規共聚物、及作為茂金屬觸媒之聚合產物之丙烯/碳數5之α-烯烴無規共聚物中者，其等之中，最佳為作為茂金屬觸媒之聚合產物之丙烯/乙烯無規共聚物。Among the above-mentioned propylene/α-olefin copolymers as the polymerization product of the metallocene catalyst, the propylene/α-olefin random copolymer as the polymerization product of the metallocene catalyst is preferred, and the above-mentioned as the metallocene catalyst Among the propylene/α-olefin random copolymers of the polymerization product, it is preferably selected from the propylene/α-olefin random copolymer with a carbon number of 2 as the polymerization product of the metallocene catalyst, and the polymerization product as the metallocene catalyst Of the propylene/α-olefin random copolymer with 4 carbons, and the propylene/α-olefin random copolymer with 5 carbons as the polymerization product of the metallocene catalyst, the best one is The propylene/ethylene random copolymer is the polymerization product of the metallocene catalyst.

關於上述作為茂金屬觸媒之聚合產物之丙烯/α-烯烴無規共聚物，就與上述彈性體層之共擠出成膜性及貼附於切晶帶之半導體晶圓之切斷性之觀點而言，較佳為熔點為80℃以上且140℃以下、尤其是100℃以上且130℃以下者。 上述作為茂金屬觸媒之聚合產物之丙烯/α-烯烴無規共聚物之熔點可藉由上述方法來測定。Regarding the above-mentioned propylene/α-olefin random copolymer as the polymerization product of the metallocene catalyst, the viewpoint of the co-extrusion film-forming property with the above-mentioned elastomer layer and the cutting property of the semiconductor wafer attached to the dicing tape In particular, those having a melting point of 80°C or more and 140°C or less, especially 100°C or more and 130°C or less are preferred. The melting point of the above-mentioned propylene/α-olefin random copolymer as a polymerization product of the metallocene catalyst can be determined by the above-mentioned method.

此處，若將上述彈性體層配置於基材層1之最外層，則於將基材層1製成卷狀體之情形時，配置於最外層之上述彈性體層彼此變得容易黏連(容易黏在一起)。因此，變得難以將基材層1自卷狀體回捲。與此相對，上述積層構造之基材層1之較佳態樣為非彈性體層/彈性體層/非彈性體層，即於最外層配置有非彈性體層，因此此種態樣之基材層1之耐黏連性變得優異。藉此，可抑制使用切晶帶10之半導體裝置之製造因黏連而產生延遲。Here, if the above-mentioned elastomer layer is arranged on the outermost layer of the base material layer 1, when the base material layer 1 is made into a roll, the above-mentioned elastomer layers arranged on the outermost layer become easy to adhere to each other (easy Stick together). Therefore, it becomes difficult to rewind the base material layer 1 from the rolled body. In contrast, the preferred aspect of the base layer 1 of the above-mentioned laminated structure is a non-elastomeric layer/elastomeric layer/non-elastomeric layer, that is, a non-elastomeric layer is arranged on the outermost layer. The blocking resistance becomes excellent. Thereby, it is possible to suppress the delay in the manufacture of the semiconductor device using the dicing tape 10 due to adhesion.

上述非彈性體層較佳為包含具有100℃以上且130℃以下之熔點且分子量分散度(質量平均分子量/數量平均分子量)為5以下之樹脂。作為此種樹脂，可列舉茂金屬PP。 藉由使上述非彈性體層包含如上述之樹脂，可於切口維持步驟中使非彈性體層更迅速地冷卻固化。因此，可更充分地抑制於使切晶帶熱收縮後基材層1發生收縮。 藉此，於切口維持步驟中，可更充分地維持切口。The non-elastomeric layer preferably contains a resin having a melting point of 100°C or higher and 130°C or lower and a molecular weight dispersion (mass average molecular weight/number average molecular weight) of 5 or less. As such resin, metallocene PP can be mentioned. By making the non-elastomeric layer contain the resin as described above, the non-elastomeric layer can be cooled and solidified more quickly in the incision maintaining step. Therefore, it is possible to more sufficiently suppress the shrinkage of the base material layer 1 after thermally shrinking the dicing tape. Thereby, in the incision maintaining step, the incision can be maintained more fully.

黏著劑層2含有黏著劑。黏著劑層2係藉由黏著來保持用於單片化為半導體晶片之半導體晶圓。The adhesive layer 2 contains an adhesive. The adhesive layer 2 holds the semiconductor wafer for singulation into semiconductor wafers by adhesion.

作為上述黏著劑，可列舉於切晶帶10之使用過程中可藉由源自外部之作用而降低黏著力者(以下稱為黏著降低型黏著劑)。Examples of the above-mentioned adhesive include those that can reduce the adhesive force by an external action during the use of the dicing tape 10 (hereinafter referred to as an adhesive reduction type adhesive).

於使用黏著降低型黏著劑作為黏著劑之情形時，於切晶帶10之使用過程中，黏著劑層2可分開使用顯示相對較高之黏著力之狀態(以下稱為高黏著狀態)與顯示相對較低之黏著力之狀態(以下稱為低黏著狀態)。例如於將貼附於切晶帶10之半導體晶圓供於切斷時，為了抑制藉由切斷半導體晶圓而單片化之複數個半導體晶片自黏著劑層2***或剝離，而利用高黏著狀態。與此相對，於切斷半導體晶圓後，為了拾取經單片化之複數個半導體晶片，利用低黏著狀態以容易自黏著劑層2拾取複數個半導體晶片。In the case of using a reduced adhesion type adhesive as the adhesive, during the use of the dicing tape 10, the adhesive layer 2 can be used separately to show a relatively high adhesion state (hereinafter referred to as a high adhesion state) and display A state of relatively low adhesion (hereinafter referred to as low adhesion state). For example, when the semiconductor wafer attached to the dicing tape 10 is used for cutting, in order to suppress the swelling or peeling of the plurality of semiconductor wafers singulated by cutting the semiconductor wafer from the adhesive layer 2, high Adhesion state. In contrast, after the semiconductor wafer is cut, in order to pick up a plurality of singulated semiconductor chips, the low adhesion state is used to easily pick up the plurality of semiconductor chips from the adhesive layer 2.

作為上述黏著降低型黏著劑，例如可列舉：可於切晶帶10之使用過程中藉由照射輻射而硬化之黏著劑(以下稱為輻射硬化黏著劑)。As the above-mentioned adhesion reduction type adhesive, for example, an adhesive that can be cured by irradiating radiation during the use of the dicing tape 10 (hereinafter referred to as a radiation curing adhesive).

作為上述輻射硬化黏著劑，例如可列舉：藉由照射電子束、紫外線、α射線、β射線、γ射線或X射線而硬化之類型之黏著劑。其等之中，較佳為使用藉由照射紫外線而硬化之黏著劑(紫外線硬化黏著劑)。Examples of the radiation curable adhesive include adhesives of the type that are cured by irradiation with electron beams, ultraviolet rays, α rays, β rays, γ rays, or X rays. Among them, it is preferable to use an adhesive that is cured by irradiating ultraviolet rays (ultraviolet curing adhesive).

作為上述輻射硬化黏著劑，例如可列舉添加型之輻射硬化黏著劑，其包含丙烯酸系聚合物等基礎聚合物、及具有輻射聚合性之碳-碳雙鍵等官能基之輻射聚合性單體成分或輻射聚合性低聚物成分。Examples of the above-mentioned radiation-curable adhesives include additive radiation-curable adhesives, which include basic polymers such as acrylic polymers, and radiation-polymerizable monomer components with functional groups such as radiation-polymerizable carbon-carbon double bonds. Or radiation polymerizable oligomer component.

作為上述丙烯酸系聚合物，可列舉包含源自(甲基)丙烯酸酯之單體單元者。作為(甲基)丙烯酸酯，例如可列舉：(甲基)丙烯酸烷基酯、(甲基)丙烯酸環烷基酯、及(甲基)丙烯酸芳基酯等。Examples of the acrylic polymer include those containing monomer units derived from (meth)acrylate. Examples of (meth)acrylates include alkyl (meth)acrylates, cycloalkyl (meth)acrylates, and aryl (meth)acrylates.

黏著劑層2亦可包含外部交聯劑。作為外部交聯劑，只要是可以與作為基礎聚合物之丙烯酸系聚合物反應而形成交聯結構之物質，則任意類型均可使用。作為此種之外部交聯劑，例如可列舉多異氰酸酯化合物、環氧化合物、多元醇化合物、氮丙啶化合物、及三聚氰胺系交聯劑等。The adhesive layer 2 may also include an external crosslinking agent. As the external crosslinking agent, any type can be used as long as it can react with the acrylic polymer as the base polymer to form a crosslinked structure. Examples of such external crosslinking agents include polyisocyanate compounds, epoxy compounds, polyol compounds, aziridine compounds, and melamine-based crosslinking agents.

作為上述輻射聚合性單體成分，例如可列舉：胺基甲酸酯(甲基)丙烯酸酯、三羥甲基丙烷三(甲基)丙烯酸酯、季戊四醇三(甲基)丙烯酸酯、季戊四醇四(甲基)丙烯酸酯、二季戊四醇單羥基五(甲基)丙烯酸酯、二季戊四醇六(甲基)丙烯酸酯、及1,4-丁二醇二(甲基)丙烯酸酯等。作為上述輻射聚合性低聚物成分，例如可列舉胺基甲酸酯系、聚醚系、聚酯系、聚碳酸酯系、聚丁二烯系等各種低聚物。上述輻射硬化黏著劑中之輻射聚合性單體成分或輻射聚合性低聚物成分之含有比例可於使黏著劑層2之黏著性適當下降之範圍內進行選擇。Examples of the radiation polymerizable monomer component include urethane (meth)acrylate, trimethylolpropane tri(meth)acrylate, pentaerythritol tri(meth)acrylate, and pentaerythritol tetra(meth)acrylate. Meth) acrylate, dipentaerythritol monohydroxy penta(meth)acrylate, dipentaerythritol hexa(meth)acrylate, 1,4-butanediol di(meth)acrylate, etc. Examples of the radiation polymerizable oligomer component include various oligomers such as urethane, polyether, polyester, polycarbonate, and polybutadiene. The content ratio of the radiation polymerizable monomer component or the radiation polymerizable oligomer component in the above-mentioned radiation curable adhesive can be selected within a range that appropriately reduces the adhesiveness of the adhesive layer 2.

上述輻射硬化黏著劑較佳為包含光聚合起始劑。作為光聚合起始劑，例如可列舉α-酮醇系化合物、苯乙酮系化合物、安息香醚系化合物、縮酮系化合物、芳香族磺醯氯系化合物、光活性肟系化合物、二苯甲酮系化合物、9-氧硫𠮿

系化合物、樟腦醌、鹵代酮、醯基膦氧化物、及醯基膦酸鹽等。The above-mentioned radiation hardening adhesive preferably contains a photopolymerization initiator. As the photopolymerization initiator, for example, α-ketol-based compounds, acetophenone-based compounds, benzoin ether-based compounds, ketal-based compounds, aromatic sulfonyl chloride-based compounds, photoactive oxime-based compounds, and benzophenone Ketone compounds, 9-oxysulfur𠮿

Series compounds, camphorquinone, halogenated ketones, phosphine oxides, and phosphonates, etc.

黏著劑層2中，除上述各成分以外，還可包含交聯促進劑、黏著賦予劑、抗老化劑、顏料或染料等著色劑等。In addition to the above-mentioned components, the adhesive layer 2 may contain a crosslinking accelerator, an adhesion imparting agent, an anti-aging agent, a coloring agent such as a pigment or a dye, and the like.

黏著劑層2之厚度較佳為1 μm以上且50 μm以下，更佳為2 μm以上且30 μm以下，進而較佳為5 μm以上且25 μm以下。The thickness of the adhesive layer 2 is preferably 1 μm or more and 50 μm or less, more preferably 2 μm or more and 30 μm or less, and still more preferably 5 μm or more and 25 μm or less.

[切晶黏晶膜] 繼而，參照圖2對切晶黏晶膜20進行說明。再者，於切晶黏晶膜20之說明中，與切晶帶10重複之部分不再重複對其進行說明。[Cut crystal stick film] Next, the dicing die sticking film 20 will be described with reference to FIG. 2. Furthermore, in the description of the chip dicing film 20, the parts that overlap with the chip dicing tape 10 will not be repeated.

如圖2所示，本實施方式之切晶黏晶膜20具備於基材層1上積層黏著劑層2而成之切晶帶10、及積層於切晶帶10之黏著劑層2上之黏晶層3。 於切晶黏晶膜20中，於黏晶層3上貼附半導體晶圓。 於使用切晶黏晶膜20之半導體晶圓之切斷中，黏晶層3亦與半導體晶圓一起被切斷。黏晶層3被切斷成與經單片化之複數個半導體晶片之尺寸相當之大小。藉此可獲得帶有黏晶層3之半導體晶片。 如上所述，切晶黏晶膜20之切晶帶10之-5℃下之拉伸儲存模數為100 MPa以上。As shown in FIG. 2, the chip dicing die film 20 of this embodiment includes a dicing tape 10 formed by laminating an adhesive layer 2 on a substrate layer 1, and a dicing tape 10 laminated on the adhesive layer 2 of the dicing tape 10 Sticky crystal layer 3. In the dicing die bonding film 20, a semiconductor wafer is attached to the die bonding layer 3. In the cutting of the semiconductor wafer using the dicing die bonding film 20, the die bonding layer 3 is also cut together with the semiconductor wafer. The die bonding layer 3 is cut into a size equivalent to the size of a plurality of singulated semiconductor chips. In this way, a semiconductor chip with a bonding layer 3 can be obtained. As described above, the tensile storage modulus of the dicing tape 10 of the dicing chip adhesive film 20 at -5° C. is more than 100 MPa.

此處，通常而言，切晶黏晶膜20之黏晶層3大多包含玻璃轉移溫度(Tg)在0℃附近之丙烯酸樹脂，因此藉由將擴開步驟之溫度設為低於丙烯酸樹脂之Tg之溫度而變得容易破裂。另一方面，若過度降低擴開步驟之溫度，則黏晶層3之彈性模數會上升到妨礙黏晶層3之切斷性之程度。因此，就黏晶層3之切斷性之觀點而言，擴開步驟之溫度較佳為設為-5℃。 因此，於使用切晶黏晶膜20之擴開步驟中，就如先前所說明般，將半導體晶圓切斷為複數個小型半導體晶片時之切斷性良好且不易發生由拉伸力導致之切晶帶10破裂之觀點、以及黏晶層3之切斷性之觀點而言，認為最佳為採用-5℃之溫度來進行擴開步驟。 因此認為，於切晶黏晶膜20中，藉由將-5℃下之拉伸儲存模數設為100 MPa之相對較高之值，亦可以更低之伸長率產生高應力。 推測其結果為，可更進一步提高將半導體晶圓切斷為小型半導體晶片時之切斷性。Here, generally speaking, the die-bonding layer 3 of the die-cut die-bonding film 20 mostly contains acrylic resin with a glass transition temperature (Tg) around 0°C. Therefore, by setting the temperature of the expansion step to be lower than that of the acrylic resin The temperature of Tg becomes easy to crack. On the other hand, if the temperature of the expansion step is excessively lowered, the elastic modulus of the die-bonding layer 3 will increase to the extent that it hinders the cutting performance of the die-bonding layer 3. Therefore, from the viewpoint of the cutting property of the die-bonding layer 3, the temperature of the expansion step is preferably set to -5°C. Therefore, in the expanding step using the dicing die bonding film 20, as previously described, the cutting performance when the semiconductor wafer is cut into a plurality of small semiconductor chips is good and the tensile force is not likely to occur. From the viewpoint of cracking of the dicing tape 10 and the viewpoint of the cutting property of the die-bonding layer 3, it is considered that the temperature of -5° C. is optimal for the expansion step. Therefore, it is believed that in the diced wafer 20, by setting the tensile storage modulus at -5°C to a relatively high value of 100 MPa, high stress can also be generated at a lower elongation. As a result, it is estimated that the cutting performance when cutting a semiconductor wafer into a small semiconductor wafer can be further improved.

如上所述，切晶黏晶膜20之切晶帶10較佳為-5℃下之拉伸儲存模數為400 MPa以下。 又，如上所述，切晶黏晶膜20之切晶帶10較佳為-5℃下之30%拉伸應力為5.5 N/10 mm以上，較佳為室溫下之30%拉伸應力為3.2 N/10 mm，較佳為-5℃下之30%拉伸應力相對於室溫下之30%拉伸應力之比為1.7以上。 進而，如上所述，切晶黏晶膜20之切晶帶10較佳為-5℃下之30%拉伸應力為30 N/10 mm以下，較佳為室溫下之30%拉伸應力為30 N/10 mm以下。As described above, the dicing tape 10 of the dicing chip adhesive film 20 preferably has a tensile storage modulus of 400 MPa or less at -5°C. In addition, as mentioned above, the dicing tape 10 of the dicing adhesive film 20 preferably has a 30% tensile stress at -5°C of 5.5 N/10 mm or more, preferably a 30% tensile stress at room temperature It is 3.2 N/10 mm, preferably the ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 1.7 or more. Furthermore, as described above, the dicing tape 10 of the dicing adhesive film 20 preferably has a 30% tensile stress at -5°C of 30 N/10 mm or less, preferably a 30% tensile stress at room temperature It is 30 N/10 mm or less.

黏晶層3較佳為具有熱硬化性。藉由使黏晶層3包含熱硬化性樹脂及具有熱硬化性官能基之熱塑性樹脂之至少一者，可對黏晶層3賦予熱硬化性。The die-bonding layer 3 preferably has thermosetting properties. By making the die-bonding layer 3 contain at least one of a thermosetting resin and a thermoplastic resin having a thermosetting functional group, the die-bonding layer 3 can be given thermosetting properties.

於黏晶層3包含熱硬化性樹脂之情形時，作為此種熱硬化性樹脂，例如可列舉環氧樹脂、酚樹脂、胺基樹脂、不飽和聚酯樹脂、聚胺酯樹脂、聚矽氧樹脂、及熱硬化性聚醯亞胺樹脂等。其等中，較佳為使用環氧樹脂。When the die-bonding layer 3 contains a thermosetting resin, examples of such thermosetting resin include epoxy resin, phenol resin, amino resin, unsaturated polyester resin, polyurethane resin, silicone resin, And thermosetting polyimide resin, etc. Among them, epoxy resin is preferably used.

作為環氧樹脂，例如可列舉：雙酚A型、雙酚F型、雙酚S型、溴化雙酚A型、氫化雙酚A型、雙酚AF型、聯苯型、萘型、茀型、酚系酚醛清漆型、鄰甲酚酚醛清漆型、三羥基苯基甲烷型、四酚基乙烷型、乙內醯脲型、異氰脲酸三縮水甘油酯型、及縮水甘油胺型之環氧樹脂。As epoxy resins, for example, bisphenol A type, bisphenol F type, bisphenol S type, brominated bisphenol A type, hydrogenated bisphenol A type, bisphenol AF type, biphenyl type, naphthalene type, and tetrafluoroethylene Type, phenolic novolac type, o-cresol novolac type, trihydroxyphenylmethane type, tetraphenol ethane type, hydantoin type, triglycidyl isocyanurate type, and glycidylamine type之epoxy.

關於作為環氧樹脂之硬化劑之酚樹脂，例如可列舉：酚醛清漆型酚樹脂、可溶酚醛型酚樹脂、及聚對羥基苯乙烯等聚氧苯乙烯。Regarding the phenol resin as the hardener of the epoxy resin, for example, novolak type phenol resin, resol type phenol resin, and polyoxystyrene such as poly(p-hydroxystyrene) can be cited.

於黏晶層3包含具有熱硬化性官能基之熱塑性樹脂之情形時，作為此種熱塑性樹脂，例如可列舉：含有熱硬化性官能基之丙烯酸樹脂。作為含有熱硬化性官能基之丙烯酸樹脂中之丙烯酸樹脂，可列舉包含源自(甲基)丙烯酸酯之單體單元者。 於具有熱硬化性官能基之熱硬化性樹脂中，可視熱硬化性官能基之種類來選擇硬化劑。When the die-bonding layer 3 contains a thermoplastic resin having a thermosetting functional group, examples of such a thermoplastic resin include an acrylic resin containing a thermosetting functional group. As an acrylic resin in the acrylic resin containing a thermosetting functional group, the thing containing the monomer unit derived from (meth)acrylate is mentioned. Among thermosetting resins having thermosetting functional groups, the curing agent can be selected depending on the type of thermosetting functional group.

就使樹脂成分之硬化反應充分地進行、或者提高硬化反應速度之觀點而言，黏晶層3亦可含有熱硬化觸媒。作為熱硬化觸媒，例如可列舉咪唑系化合物、三苯基膦系化合物、胺系化合物、及三鹵代硼烷系化合物。From the viewpoint of making the hardening reaction of the resin component proceed sufficiently or increasing the hardening reaction speed, the die-bonding layer 3 may contain a thermosetting catalyst. Examples of the thermosetting catalyst include imidazole-based compounds, triphenylphosphine-based compounds, amine-based compounds, and trihaloborane-based compounds.

黏晶層3亦可包含熱塑性樹脂。熱塑性樹脂係作為黏合劑發揮功能。作為熱塑性樹脂，例如可列舉：天然橡膠、丁基橡膠、異戊二烯橡膠、氯丁二烯橡膠、乙烯-乙酸乙烯酯共聚物、乙烯-丙烯酸共聚物、乙烯-丙烯酸酯共聚物、聚丁二烯樹脂、聚碳酸酯樹脂、熱塑性聚醯亞胺樹脂、聚醯胺6或聚醯胺6,6等聚醯胺樹脂、苯氧基樹脂、丙烯酸樹脂、PET或PBT等飽和聚酯樹脂、聚醯胺醯亞胺樹脂、氟樹脂等。上述熱塑性樹脂可僅使用一種，亦可將兩種以上組合使用。作為上述熱塑性樹脂，就由於離子性雜質較少且耐熱性較高，故容易確保基於黏晶層之連接可靠性之觀點而言，較佳為丙烯酸樹脂。The die bonding layer 3 may also include a thermoplastic resin. The thermoplastic resin system functions as a binder. Examples of thermoplastic resins include natural rubber, butyl rubber, isoprene rubber, chloroprene rubber, ethylene-vinyl acetate copolymer, ethylene-acrylic acid copolymer, ethylene-acrylic acid ester copolymer, polybutylene Diene resin, polycarbonate resin, thermoplastic polyimide resin, polyamide resin such as polyamide 6 or polyamide 6,6, phenoxy resin, acrylic resin, saturated polyester resin such as PET or PBT, Polyamide imide resin, fluororesin, etc. Only one type of the above-mentioned thermoplastic resin may be used, or two or more types may be used in combination. As the above-mentioned thermoplastic resin, since it has less ionic impurities and higher heat resistance, it is easy to ensure the connection reliability based on the die-bonding layer, and an acrylic resin is preferable.

上述丙烯酸樹脂較佳為包含源自(甲基)丙烯酸酯之單體單元作為以質量比例計最多之單體單元的聚合物。作為(甲基)丙烯酸酯，例如可列舉：(甲基)丙烯酸烷基酯、(甲基)丙烯酸環烷基酯、及(甲基)丙烯酸芳基酯等。上述丙烯酸樹脂亦可包含源自可與(甲基)丙烯酸酯共聚之其他成分之單體單元。作為上述其他成分，例如可列舉：含羧基單體、酸酐單體、含羥基單體、含縮水甘油基單體、含磺酸基單體、含磷酸基單體、丙烯醯胺、丙烯腈等含官能基單體、或各種多官能性單體等。就於黏晶層中實現高凝聚力之觀點而言，上述丙烯酸樹脂較佳為(甲基)丙烯酸酯(尤其是烷基之碳數為4以下之(甲基)丙烯酸烷基酯)、含羧基單體、含氮原子單體、及多官能性單體(尤其是聚縮水甘油基系多官能單體)之共聚物，更佳為丙烯酸乙酯與丙烯酸丁酯、丙烯酸、丙烯腈、及(甲基)丙烯酸多縮水甘油基酯之共聚物。The above-mentioned acrylic resin is preferably a polymer containing monomer units derived from (meth)acrylate as the most monomer unit in terms of mass ratio. Examples of (meth)acrylates include alkyl (meth)acrylates, cycloalkyl (meth)acrylates, and aryl (meth)acrylates. The above-mentioned acrylic resin may also contain monomer units derived from other components copolymerizable with (meth)acrylate. Examples of the above-mentioned other components include: carboxyl group-containing monomers, acid anhydride monomers, hydroxyl group-containing monomers, glycidyl group-containing monomers, sulfonic acid group-containing monomers, phosphoric acid group-containing monomers, acrylamide, acrylonitrile, etc. Functional group-containing monomers, or various polyfunctional monomers, etc. From the viewpoint of achieving high cohesion in the sticky layer, the above-mentioned acrylic resin is preferably a (meth)acrylate (especially an alkyl (meth)acrylate with an alkyl group of 4 or less carbon atoms) and a carboxyl group. Copolymers of monomers, nitrogen atom-containing monomers, and multifunctional monomers (especially polyglycidyl-based multifunctional monomers), more preferably ethyl acrylate and butyl acrylate, acrylic acid, acrylonitrile, and ( Copolymer of polyglycidyl meth)acrylate.

黏晶層3亦可視需要含有一種或兩種以上之其他成分。作為其他成分，例如可列舉：阻燃劑、矽烷偶合劑、及離子捕捉劑。The die-bonding layer 3 may also contain one or more than two other components as needed. Examples of other components include flame retardants, silane coupling agents, and ion scavengers.

黏晶層3之厚度較佳為40 μm以上，更佳為60 μm以上，進而較佳為80 μm以上。又，黏晶層3之厚度較佳為200 μm以下，更佳為160 μm以下，進而較佳為120 μm以下。The thickness of the die-bonding layer 3 is preferably 40 μm or more, more preferably 60 μm or more, and still more preferably 80 μm or more. In addition, the thickness of the die-bonding layer 3 is preferably 200 μm or less, more preferably 160 μm or less, and still more preferably 120 μm or less.

本實施方式之切晶黏晶膜20例如用作用以製造半導體積體電路之輔助用具。以下對使用切晶黏晶膜20之具體例進行說明。 以下，對使用基材層1為一層之切晶黏晶膜20之例進行說明。The diced die bonding film 20 of this embodiment is used, for example, as an auxiliary tool for manufacturing semiconductor integrated circuits. Hereinafter, a specific example of using the dicing die bonding film 20 will be described. Hereinafter, an example of using the dicing die attach film 20 in which the base layer 1 is one layer will be described.

製造半導體積體電路之方法具有下述步驟：半切割步驟，其為了藉由切斷處理將半導體晶圓加工成晶片(Die)而在半導體晶圓上形成槽，進而對半導體晶圓進行研削而使厚度變薄；背面研磨步驟，其對半切割步驟後之半導體晶圓進行研削而使厚度變薄；安裝步驟，其將背面研磨步驟後之半導體晶圓之一面(例如與電路面處於相反側之面)貼附於黏晶層3而將半導體晶圓固定於切晶帶10；擴開步驟，其將經半切割加工之半導體晶片彼此之間隔擴大；切口維持步驟，其維持半導體晶片彼此之間隔；拾取步驟，其於黏晶層3與黏著劑層2之間進行剝離，以貼附有黏晶層3之狀態取出半導體晶片(Die)；及黏晶步驟，其使貼附有黏晶層3之狀態之半導體晶片(Die)接著於被接著體。於實施該等步驟時，使用本實施方式之切晶帶(切晶黏晶膜)作為製造輔助用具。The method of manufacturing a semiconductor integrated circuit has the following steps: a half-cutting step, which forms grooves on the semiconductor wafer by cutting the semiconductor wafer into a die, and then grinds the semiconductor wafer To make the thickness thinner; the back grinding step, which grinds the semiconductor wafer after the half-cutting step to make the thickness thinner; the mounting step, which grinds one side of the semiconductor wafer after the back grinding step (for example, on the opposite side to the circuit surface) The surface) is attached to the die bonding layer 3 to fix the semiconductor wafer to the dicing tape 10; the expansion step, which expands the distance between the half-cut semiconductor wafers; and the incision maintaining step, which maintains the semiconductor wafers between each other Interval; a pick-up step, which peels off between the die-bonding layer 3 and the adhesive layer 2, and takes out the semiconductor chip (Die) in a state where the die-bonding layer 3 is attached; and the die-bonding step, which causes the die to be attached The semiconductor chip (Die) in the state of layer 3 is then attached to the bonded body. When performing these steps, the chip dicing tape (chip dicing film) of this embodiment is used as a manufacturing auxiliary tool.

於半切割步驟中，如圖3A及圖3B所示，實施用於將半導體積體電路切斷成小片(Die)之半切割加工。詳細而言，於半導體晶圓W之與電路面相反側之面貼附晶圓加工用帶T(參照圖3A)。又，將切晶環R安裝於晶圓加工用帶T(參照圖3A)。於貼附有晶圓加工用帶T之狀態下形成分割用槽(參照圖3B)。於背面研磨步驟中，如圖3C及圖3D所示，對半導體晶圓進行研削而使厚度變薄。詳細而言，於形成有槽之面上貼附背面研磨帶G，另一方面，將最初貼附之晶圓加工用帶T剝離(參照圖3C)。於貼附有背面研磨帶G之狀態下實施研削加工直至半導體晶圓W成為規定厚度(參照圖3D)。In the half-cutting step, as shown in FIG. 3A and FIG. 3B, a half-cutting process for cutting the semiconductor integrated circuit into small pieces (Die) is performed. Specifically, the wafer processing tape T is attached to the surface of the semiconductor wafer W on the opposite side to the circuit surface (see FIG. 3A). In addition, the dicing ring R is attached to the wafer processing tape T (see FIG. 3A). In the state where the wafer processing tape T is attached, a groove for dividing is formed (see FIG. 3B). In the back grinding step, as shown in FIGS. 3C and 3D, the semiconductor wafer is ground to make the thickness thinner. Specifically, the back polishing tape G is attached to the surface where the grooves are formed, and on the other hand, the wafer processing tape T attached first is peeled off (see FIG. 3C). In the state where the back grinding tape G is attached, the grinding process is performed until the semiconductor wafer W becomes a predetermined thickness (see FIG. 3D).

於安裝步驟中，如圖4A〜圖4B所示，將切晶環R安裝於切晶帶10之黏著劑層2後，於露出之黏晶層3之面上貼附經半切割加工之半導體晶圓W(參照圖4A)。其後，自半導體晶圓W剝離背面研磨帶G(參照圖4B)。In the mounting step, as shown in FIGS. 4A to 4B, after the dicing ring R is mounted on the adhesive layer 2 of the dicing tape 10, a semi-cut semiconductor is attached to the exposed surface of the die bonding layer 3 Wafer W (refer to FIG. 4A). After that, the back polishing tape G is peeled off from the semiconductor wafer W (see FIG. 4B).

於擴開步驟中，如圖5A〜圖5C所示，將切晶環R固定於擴開裝置之保持器H。使用擴開裝置所具備之頂起構件U將切晶黏晶膜20自下側頂起，藉此將切晶黏晶膜20以於面方向上擴開之方式進行拉伸(參照圖5B)。藉此，於特定之溫度條件下切斷經半切割加工之半導體晶圓W。上述溫度條件例如為-20〜5℃，較佳為-15〜0℃，更佳為-10〜-5℃。藉由使頂起構件U下降而解除擴開狀態(參照圖5C)。 進而，於擴開步驟中，如圖6A〜圖6B所示，於更高之溫度條件下(例如室溫(23℃)對切晶帶10進行拉伸以使面積擴大。藉此，將切斷之相鄰之半導體晶片W於膜表面之面方向上拉離，而進一步擴大間隔。 此處，本實施方式之切晶黏晶膜20由於黏晶帶10之-5℃下之拉伸儲存模數為100 MPa以上，故可更進一步提高於低溫條件下基於擴開而自半導體晶圓向複數個半導體晶片之切斷性。In the expanding step, as shown in FIGS. 5A to 5C, the crystal cutting ring R is fixed to the holder H of the expanding device. The dicing die attach film 20 is lifted up from the lower side using the lifting member U included in the expanding device, whereby the die dicing die attach film 20 is stretched in a plane direction (refer to FIG. 5B) . Thereby, the semi-cut semiconductor wafer W is cut under a specific temperature condition. The above-mentioned temperature conditions are, for example, -20 to 5°C, preferably -15 to 0°C, and more preferably -10 to -5°C. The expanded state is released by lowering the lifting member U (refer to FIG. 5C). Furthermore, in the expanding step, as shown in FIGS. 6A to 6B, the dicing tape 10 is stretched under a higher temperature condition (for example, room temperature (23° C.) to expand the area. With this, the cutting The broken adjacent semiconductor wafers W are pulled apart in the plane direction of the film surface to further expand the gap. Here, the dicing die bonding film 20 of the present embodiment has a tensile storage modulus of 100 MPa or more at -5°C of the die bonding tape 10, so it can further improve the self-contained semiconductor wafer based on expansion under low temperature conditions. The cutting performance of a plurality of semiconductor wafers in a circular direction.

於切口維持步驟中，如圖7所示，使熱風(例如100〜130℃)對準切晶帶10以使切晶帶10熱收縮後，進行冷卻固化，維持所切斷之相鄰之半導體晶片W間之距離(切口)。In the incision maintenance step, as shown in FIG. 7, hot air (for example, 100~130°C) is aligned with the dicing tape 10 to thermally shrink the dicing tape 10, and then cool and solidify to maintain the cut adjacent semiconductor The distance between wafers W (notches).

於拾取步驟中，如圖8所示，將貼附有黏晶層3之狀態之半導體晶片W自切晶帶10之黏著層2剝離。詳細而言，使頂銷構件P上升，而將拾取對象之半導體晶片W隔著切晶帶10頂起。藉由吸附治具J來保持被頂起之半導體晶片。In the pick-up step, as shown in FIG. 8, the semiconductor wafer W in the state where the die-bonding layer 3 is attached is peeled off from the adhesive layer 2 of the dicing tape 10. Specifically, the ejector pin member P is raised, and the semiconductor wafer W to be picked up is pushed up via the dicing tape 10. The lifted semiconductor chip is held by the suction jig J.

於黏晶步驟中，將貼附有黏晶層3之狀態之半導體晶片W接著於被接著體。 再者，於上述半導體積體電路之製造中，對使用切晶黏晶膜20作為輔助器具之例進行了說明，但即便於使用切晶帶10作為輔助器具時，亦可與上述同樣地製造半導體積體電路。In the die bonding step, the semiconductor wafer W in the state where the die bonding layer 3 is attached is attached to the bonded body. Furthermore, in the manufacture of the above-mentioned semiconductor integrated circuit, an example of using the dicing die attach film 20 as an auxiliary tool has been described, but even when the dicing tape 10 is used as an auxiliary tool, it can be manufactured in the same manner as described above. Semiconductor integrated circuit.

由本說明書所揭示之事項包括以下者。The matters disclosed in this manual include the following.

(1) 一種切晶帶， 其係於基材層上積層黏著劑層而成者， 該切晶帶之-5℃下之拉伸儲存模數為100 MPa以上。(1) A kind of diced tape, It is formed by laminating an adhesive layer on the substrate layer, The tensile storage modulus at -5°C of the dicing tape is more than 100 MPa.

根據上述構成，上述切晶帶之-5℃下之拉伸儲存模數為100 MPa以上，因此可使上述切晶帶具有相對較大之硬度。 因此，於貼附於半導體晶圓且在低溫條件(例如-15℃〜5℃)下擴開上述切晶帶而自上述半導體晶圓切斷為複數個半導體晶片之情形時，可於擴開開始時，對上述切晶帶整體充分地施加拉伸力。 藉此，容易將半導體晶圓切斷為複數個半導體晶片，並且容易獲得被相對均勻切斷之半導體晶片。 即，可更進一步提高半導體晶圓之切斷性。According to the above structure, the tensile storage modulus at -5°C of the crystal cut tape is 100 MPa or more, so the crystal cut tape can have a relatively large hardness. Therefore, when it is attached to a semiconductor wafer and the dicing tape is expanded under low temperature conditions (for example, -15°C to 5°C) and cut from the semiconductor wafer into a plurality of semiconductor wafers, it can be expanded At the beginning, a sufficient tensile force is applied to the entire dicing tape. Thereby, it is easy to cut the semiconductor wafer into a plurality of semiconductor wafers, and it is easy to obtain a relatively uniformly cut semiconductor wafer. That is, the cutting performance of the semiconductor wafer can be further improved.

(2) 如上述(1)記載之切晶帶， 其-5℃下之拉伸儲存模數為400 MPa以下。(2) As mentioned in (1) above, the slicing tape, Its tensile storage modulus at -5°C is below 400 MPa.

根據上述構成，對上述切晶帶整體施加充分之拉伸力、並且使上述切晶帶相對容易伸長，因此可抑制於自貼附於上述切晶帶之半導體晶圓向複數個半導體晶片切斷時由拉伸力導致之上述切晶帶破裂，並且更進一步提高自半導體晶圓向複數個半導體晶片之切斷性。 又，藉由使-5℃下之30%拉伸應力為30 N/10 mm以下，尤其是可更進一步提高自半導體晶圓向複數個小型半導體晶片之切斷性。According to the above configuration, sufficient tensile force is applied to the entire dicing tape, and the dicing tape is relatively easily elongated, so that it is possible to suppress the cutting of the semiconductor wafer attached to the dicing tape to a plurality of semiconductor wafers. At this time, the dicing band is broken by the tensile force, and the cutting performance from the semiconductor wafer to the plurality of semiconductor wafers is further improved. In addition, by setting the 30% tensile stress at -5°C to 30 N/10 mm or less, in particular, the cutting performance from the semiconductor wafer to a plurality of small semiconductor wafers can be further improved.

(3) 如上述(1)或(2)記載之切晶帶， 其-5℃下之30%拉伸應力為5.5 N/10 mm以上。(3) As mentioned in (1) or (2) above, the slicing tape, The 30% tensile stress at -5°C is 5.5 N/10 mm or more.

根據上述構成，-5℃下之30%拉伸應力為5.5 N/10 mm以上，因此於貼附於半導體晶圓且在低溫條件下擴開上述切晶帶而自上述半導體晶圓切斷為複數個半導體晶片之情形時，可使切晶帶即便於擴開中亦具有相對較大之硬度。 因此，變得更容易將半導體晶圓切斷為複數個半導體晶片，並且更容易獲得被相對均勻切斷之半導體晶片。 即，可更進一步地提高半導體晶圓之切斷性。According to the above structure, the 30% tensile stress at -5°C is 5.5 N/10 mm or more. Therefore, it is attached to a semiconductor wafer and expands the dicing tape under low temperature conditions to cut from the semiconductor wafer. In the case of a plurality of semiconductor wafers, the dicing tape can be made to have a relatively large hardness even when it is expanded. Therefore, it becomes easier to cut the semiconductor wafer into a plurality of semiconductor wafers, and it is easier to obtain a semiconductor wafer that is relatively uniformly cut. That is, the cutting performance of the semiconductor wafer can be further improved.

(4) 如上述(1)至(3)中任一項記載之切晶帶， 其-5℃下之30%拉伸應力為30 N/10 mm以下。(4) The dicing tape as described in any one of (1) to (3) above, The 30% tensile stress at -5°C is below 30 N/10 mm.

根據上述構成，於擴開中對上述切晶帶整體施加充分之拉伸力、並且使上述切晶帶相對容易伸長，因此於對貼附於半導體晶圓之切晶帶進行擴開而將上述半導體晶圓切斷為複數個半導體晶片之期間，可抑制由擴開導致之上述切晶帶破裂，並且更進一步提高自半導體晶圓向複數個半導體晶片之切斷性。 又，藉由使-5℃下之30%拉伸應力為30 N/10 mm以下，尤其是可更進一步提高自半導體晶圓向複數個小型半導體晶片之切斷性。According to the above configuration, sufficient tensile force is applied to the entire dicing tape during expansion, and the dicing tape is relatively easily elongated. Therefore, the dicing tape attached to the semiconductor wafer is expanded to expand the dicing tape. During the cutting of the semiconductor wafer into a plurality of semiconductor wafers, it is possible to suppress the cracking of the dicing band caused by the expansion, and to further improve the cutting performance from the semiconductor wafer to the plurality of semiconductor wafers. In addition, by setting the 30% tensile stress at -5°C to 30 N/10 mm or less, in particular, the cutting performance from the semiconductor wafer to a plurality of small semiconductor wafers can be further improved.

(5) 如上述(1)至(4)中任一項記載之切晶帶， 其室溫下之30%拉伸應力為3.2 N/10 mm以上。(5) The dicing tape as described in any one of (1) to (4) above, The 30% tensile stress at room temperature is 3.2 N/10 mm or more.

根據上述構成，室溫下之30%拉伸應力為3.2 N/10 mm以上，因此於貼附於半導體晶圓且在低溫條件下擴開上述切晶帶而自上述半導體晶圓切斷為複數個半導體晶片之情形時，即便於擴開中亦可更進一步提高半導體晶圓之切斷性。 又，可抑制被切斷之上述半導體晶片間之切晶帶所產生之拉伸應力轉移到半導體晶片側。 因此，可相對抑制對上述半導體晶片之外周緣部分施加相對較大之力而使得上述半導體晶片之外周緣部分自上述切晶帶之表面***(晶片***)。According to the above structure, the 30% tensile stress at room temperature is 3.2 N/10 mm or more. Therefore, it is attached to a semiconductor wafer and the dicing tape is expanded under low temperature conditions and cut from the semiconductor wafer into plurals. In the case of a semiconductor wafer, the cutting performance of the semiconductor wafer can be further improved even during expansion. In addition, it is possible to suppress the transfer of tensile stress generated by the dicing band between the above-mentioned semiconductor wafers that have been cut to the semiconductor wafer side. Therefore, it is possible to relatively suppress the application of a relatively large force to the outer peripheral portion of the semiconductor wafer to cause the outer peripheral portion of the semiconductor wafer to bulge (wafer bulge) from the surface of the dicing tape.

(6) 如上述(1)至(5)中任一項記載之切晶帶， 其室溫下之30%拉伸應力為30 N/10 mm以下。(6) The dicing tape as described in any one of (1) to (5) above, The 30% tensile stress at room temperature is 30 N/10 mm or less.

根據上述構成，於擴開中對上述切晶帶整體施加充分之拉伸力，並且使上述切晶帶相對容易伸長，因此於對貼附於半導體晶圓之切晶帶進行擴開而將上述半導體晶圓切斷為複數個半導體晶片之期間，可抑制由擴開導致之上述切晶帶破裂，並且更進一步提高自半導體晶圓向複數個半導體晶片之切斷性。 又，藉由將室溫下之30%拉伸應力設為30 N/10 mm以下，尤其是可更進一步提高自半導體晶圓向複數個小型半導體晶片之切斷性。According to the above configuration, sufficient tensile force is applied to the entire dicing tape during expansion, and the dicing tape is relatively easily elongated. Therefore, the dicing tape attached to the semiconductor wafer is expanded to expand the dicing tape. During the cutting of the semiconductor wafer into a plurality of semiconductor wafers, it is possible to suppress the cracking of the dicing band caused by the expansion, and to further improve the cutting performance from the semiconductor wafer to the plurality of semiconductor wafers. In addition, by setting the 30% tensile stress at room temperature to 30 N/10 mm or less, in particular, the cutting performance from the semiconductor wafer to a plurality of small semiconductor wafers can be further improved.

(7) 如上述(1)至(6)中任一項記載之切晶帶， 其-5℃下之30%拉伸應力相對於室溫下之30%拉伸應力之比為1.7以上。(7) The dicing tape as described in any one of (1) to (6) above, The ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 1.7 or more.

根據上述構成，-5℃下之30%拉伸應力相對於室溫下之30%拉伸應力之比為1.7以上，因此於貼附於半導體晶圓且在低溫條件下擴開上述切晶帶而自上述半導體晶圓切斷為複數個半導體晶片之情形時，即便於擴開中亦可更進一步提高半導體晶圓之切斷性。 又，可相對抑制因上述切晶帶所產生之拉伸應力轉移到半導體晶片側而導致之晶片***。According to the above structure, the ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 1.7 or more. Therefore, it is attached to a semiconductor wafer and expands the dicing tape under low temperature conditions. When the semiconductor wafer is cut into a plurality of semiconductor wafers, the cutting performance of the semiconductor wafer can be further improved even during expansion. In addition, it is possible to relatively suppress wafer swelling caused by the transfer of the tensile stress generated by the dicing tape to the semiconductor wafer side.

(8) 如上述(1)至(7)中任一項記載之切晶帶， 其-5℃下之30%拉伸應力相對於室溫下之30%拉伸應力之比為3.0以下。(8) The dicing tape as described in any one of (1) to (7) above, The ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 3.0 or less.

根據上述構成，於擴開中對上述切晶帶整體施加充分之拉伸力，並且使上述切晶帶相對容易伸長，因此於對貼附於半導體晶圓之切晶帶進行擴開而將上述半導體晶圓切斷為複數個半導體晶片之期間，可抑制由擴開導致之上述切晶帶破裂，並且可更進一步提高自半導體晶圓向複數個半導體晶片之切斷性。 又，藉由使-5℃下之30%拉伸應力相對於室溫下之30%拉伸應力之比為3.0以下，尤其是可更進一步提高自半導體晶圓向複數個小型半導體晶片之切斷性。According to the above configuration, sufficient tensile force is applied to the entire dicing tape during expansion, and the dicing tape is relatively easily elongated. Therefore, the dicing tape attached to the semiconductor wafer is expanded to expand the dicing tape. During the cutting of the semiconductor wafer into a plurality of semiconductor wafers, the cracking of the above-mentioned dicing band caused by the expansion can be suppressed, and the cutting performance from the semiconductor wafer to the plurality of semiconductor wafers can be further improved. In addition, by making the ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature 3.0 or less, in particular, the cutting from a semiconductor wafer to a plurality of small semiconductor wafers can be further improved. Intermittent.

(9) 如上述(1)至(8)中任一項記載之切晶帶，其中 上述基材層形成為以彈性體層為中心層且於該中心層之彼此相對之兩面具有非彈性體層之三層構造。(9) The dicing tape as described in any one of (1) to (8) above, wherein The base material layer is formed into a three-layer structure with an elastomer layer as a center layer and non-elastomeric layers on opposite sides of the center layer.

根據上述構成，可使上述彈性體層作為緩和拉伸應力之應力緩和層發揮功能。即，可相對減小上述基材層所產生之拉伸應力，因此可使上述基材層具有適度硬度並且相對容易拉伸。 藉此，可提高自半導體晶圓向複數個半導體晶片之切斷性。 又，可抑制於切斷步驟中之擴開時上述基材層破裂而發生破損。According to the above configuration, the elastomer layer can function as a stress relaxation layer that relaxes tensile stress. That is, the tensile stress generated by the base layer can be relatively reduced, so that the base layer can have moderate hardness and be relatively easy to stretch. Thereby, the cutting performance from the semiconductor wafer to a plurality of semiconductor wafers can be improved. In addition, it is possible to prevent the base material layer from cracking and breaking during the spreading in the cutting step.

(10) 一種切晶黏晶膜，其具備： 於基材層上積層黏著劑層而成之切晶帶、及 積層於上述切晶帶之黏著劑層上之黏晶層，且 該切晶黏晶膜之-5℃下之拉伸儲存模數為100 MPa以上。(10) A diced chip adhesive film, which has: Die-cutting tape formed by laminating an adhesive layer on the substrate layer, and A die-bonding layer laminated on the adhesive layer of the above-mentioned die-cutting tape, and The tensile storage modulus at -5°C of the diced sticky film is more than 100 MPa.

根據上述構成，於貼附於半導體晶圓且在低溫條件(例如-15℃〜5℃)下擴開上述切晶帶而將上述半導體晶圓切斷為複數個半導體晶片之情形時，可於擴開開始時，對上述切晶帶整體充分地施加拉伸力。 藉此，可更進一步提高半導體晶圓之切斷性，此外，還可提高黏晶層之切斷性。According to the above-mentioned configuration, when the dicing tape is expanded to cut the semiconductor wafer into a plurality of semiconductor wafers by attaching to a semiconductor wafer and expanding the dicing tape under low temperature conditions (for example, -15°C to 5°C), At the beginning of the expansion, a sufficient tensile force is applied to the entire dicing tape. Thereby, the cutting performance of the semiconductor wafer can be further improved, and in addition, the cutting performance of the die bonding layer can be improved.

再者，本發明之切晶帶及切晶黏晶膜並不限定於上述實施方式。又，本發明之切晶帶及切晶黏晶膜不受上述之作用效果限定。本發明之切晶帶及切晶黏晶膜可於不脫離本發明之主旨之範圍內進行各種變更。 [實施例]Furthermore, the dicing tape and the dicing die bonding film of the present invention are not limited to the above-mentioned embodiments. In addition, the chip dicing tape and chip adhesive film of the present invention are not limited by the above-mentioned effects. The chip dicing tape and chip adhesive film of the present invention can be variously modified without departing from the spirit of the present invention. [Example]

繼而，列舉實施例對本發明進一步具體地進行說明。以下之實施例係用於進一步詳細地說明本發明者，並非對本發明之範圍進行限定。Next, the present invention will be described in further detail by citing examples. The following examples are used to further illustrate the present inventors in detail, and do not limit the scope of the present invention.

[實施例1] ＜基材層之成形＞ 使用兩種三層擠出T模成形機，將具有A層/B層/C層之三層構造(以B層為中心層且於B層之兩面積層有作為外層之A層及C層之三層構造)之基材層成形。A層及C層之樹脂係使用茂金屬PP(商品名：WINTEC WXK1233、日本聚丙烯公司製)，B層之樹脂係使用EVA(商品名：EvaflexEV250、三井杜邦聚化學公司製)。 上述擠出成形係於模頭溫度190℃下進行。即，A層、B層、及C層係於190℃下擠出成形。藉由擠出成形所獲得之基材層之厚度為100 μm。再者，A層、B層、及C層之厚度比(層厚比)為A層：B層：C層=1：10：1。 使所成形之基材層充分固化後，將固化後之基材層捲取成卷狀而製成卷狀體。 ＜切晶帶之製作＞ 使用敷料器以厚度成為10 μm之方式將黏著劑組合物自卷狀之基材層塗佈於基材層之一面。將塗佈黏著劑組合物後之基材層於110℃下加熱乾燥3分鐘而形成黏著劑層，藉此獲得切晶帶。 上述黏著劑組合物係以如下方式製備。 首先，將INA(丙烯酸異壬酯)173質量份、HEA(丙烯酸羥乙酯)54.5質量份、AIBN(2,2'-偶氮二異丁腈)0.46質量份、乙酸乙酯372質量份加以混合而獲得第1樹脂組合物。 繼而，於裝備有圓底可分離式燒瓶(容量1 L)、溫度計、氮氣導入管及攪拌葉片之聚合用實驗裝置之上述圓底可分離式燒瓶內加入上述第1樹脂組合物，一邊攪拌上述第1樹脂組合物一邊使上述第1樹脂組合物之液溫成為常溫(23℃)，對上述圓底可分離式燒瓶內進行6小時氮氣置換。 接下來，於使氮氣流入至上述圓底可分離式燒瓶內之狀態下，一邊攪拌上述第1樹脂組合物一邊使上述第1樹脂組合物之液溫於62℃下保持3小時，之後進而於75℃下保持2小時，使上述INA、上述HEA、及上述AIBN聚合而獲得第2樹脂組合物。之後，停止氮氣向上述圓底可分離式燒瓶內流入。 將上述第2樹脂組合物進行冷卻直至液溫成為常溫，之後向上述第2樹脂組合物中加入作為具有聚合性碳-碳雙鍵之化合物之甲基丙烯酸2-異氰酸基乙酯(昭和電工公司製、商品名「KarenzMOI(註冊商標)」)52.5質量份及二月桂酸二丁基錫IV(和光純藥工業公司製)0.26質量份，獲得第3樹脂組合物，將所得之第3樹脂組合物於大氣氣氛下以液溫50℃攪拌24小時。 繼而，於上述第3樹脂組合物中分別加入相對於聚合物固形物成分100質量份為0.75質量份之CORONATEL(異氰酸酯化合物)及2質量份之Omnirad127(光聚合起始劑)後，使用乙酸乙酯將上述第3樹脂組合物以固形物成分濃度成為20質量%之方式進行稀釋，而製備黏著劑組合物。 ＜切晶黏晶膜之製作＞ 將丙烯酸樹脂(長瀨化學公司製、商品名「SG-P3」、玻璃轉移溫度12℃)100質量份、環氧樹脂(三菱化學公司製、商品名「JER1001」)46質量份、酚樹脂(明和化成公司製、商品名「MEH-7851ss」)51質量份、球狀二氧化矽(Admatechs公司製、商品名「SO-25R」)191質量份及硬化觸媒(四國化成工業公司製、商品名「CUREZOLPHZ」)0.6質量份加入至甲基乙基酮中並加以混合，獲得固形物成分濃度20質量%之黏晶組合物。 繼而，使用敷料器，將上述黏晶組合物以厚度成為10 μm之方式塗佈於作為剝離襯墊之PET系隔離件(厚度50 μm)之實施過聚矽氧處理之面上，於130℃下乾燥2分鐘而自上述黏晶組合物進行脫溶劑，獲得於上述剝離襯墊上積層有黏晶層而成之黏晶片。 繼而，於上述切晶帶之上述黏著劑層上貼合上述黏晶片中之未積層上述剝離片之側，之後將上述剝離襯墊自上述黏晶層進行剝離，獲得具備黏晶層之切晶黏晶膜。[Example 1] ＜Forming of the substrate layer＞ Using two three-layer extrusion T-die forming machines, the three-layer structure with layer A/layer B/layer C (with layer B as the central layer and two area layers of layer B as the outer layer A layer and C layer Three-layer structure) of the base material layer is formed. The resin of the A layer and the C layer uses metallocene PP (trade name: WINTEC WXK1233, manufactured by Japan Polypropylene Corporation), and the resin of the B layer uses EVA (trade name: EvaflexEV250, manufactured by Mitsui DuPont Chemical Co., Ltd.). The above-mentioned extrusion molding was performed at a die temperature of 190°C. That is, the A layer, the B layer, and the C layer were extrusion molded at 190°C. The thickness of the substrate layer obtained by extrusion molding is 100 μm. Furthermore, the thickness ratio (layer thickness ratio) of the A layer, the B layer, and the C layer is A layer: B layer: C layer=1:10:1. After the formed substrate layer is fully cured, the cured substrate layer is wound into a roll to form a roll. ＜Production of crystal cut ribbon＞ Using an applicator, apply the adhesive composition from the rolled substrate layer to one surface of the substrate layer so that the thickness becomes 10 μm. The substrate layer coated with the adhesive composition was heated and dried at 110° C. for 3 minutes to form an adhesive layer, thereby obtaining a dicing tape. The above-mentioned adhesive composition is prepared in the following manner. First, 173 parts by mass of INA (isononyl acrylate), 54.5 parts by mass of HEA (hydroxyethyl acrylate), 0.46 parts by mass of AIBN (2,2'-azobisisobutyronitrile), and 372 parts by mass of ethyl acetate were added. They are mixed to obtain a first resin composition. Then, the above-mentioned first resin composition was added to the above-mentioned round-bottom separable flask (volume 1 L), a thermometer, a nitrogen introduction tube, and a stirring blade equipped with a polymerization experimental apparatus for polymerization, and the above was stirred while stirring. For the first resin composition, while making the liquid temperature of the first resin composition normal temperature (23°C), the inside of the round-bottom separable flask was replaced with nitrogen for 6 hours. Next, with nitrogen gas flowing into the round-bottom separable flask, while stirring the first resin composition, the liquid temperature of the first resin composition was kept at 62°C for 3 hours, and then The temperature was maintained at 75°C for 2 hours to polymerize the INA, the HEA, and the AIBN to obtain a second resin composition. After that, the flow of nitrogen gas into the above-mentioned round-bottom separable flask was stopped. The second resin composition is cooled until the liquid temperature becomes room temperature, and then 2-isocyanatoethyl methacrylate (Showa) is added to the second resin composition as a compound having a polymerizable carbon-carbon double bond. Denko Corporation, product name "Karenz MOI (registered trademark)") 52.5 parts by mass and dibutyltin dilaurate IV (manufactured by Wako Pure Chemical Industries, Ltd.) 0.26 parts by mass to obtain a third resin composition, and combine the obtained third resin The material was stirred at a liquid temperature of 50°C for 24 hours in an atmosphere. Then, 0.75 parts by mass of CORONATEL (isocyanate compound) and 2 parts by mass of Omnirad 127 (photopolymerization initiator) were added to the third resin composition with respect to 100 parts by mass of the polymer solid content, and ethyl acetate was used. Ester dilutes the said 3rd resin composition so that the solid content concentration may become 20 mass %, and the adhesive composition was prepared. ＜Production of slicing and sticking film＞ Acrylic resin (manufactured by Nagase Chemical Company, brand name "SG-P3", glass transition temperature 12°C) 100 parts by mass, epoxy resin (manufactured by Mitsubishi Chemical Company, brand name "JER1001") 46 parts by mass, phenol resin ( Produced by Meiwa Chemical Co., Ltd., brand name "MEH-7851ss") 51 parts by mass, spherical silica (manufactured by Admatechs Co., brand name "SO-25R") 191 parts by mass, and hardening catalyst (manufactured by Shikoku Kasei Kogyo Co., Ltd., Brand name "CUREZOLPHZ") 0.6 parts by mass was added to methyl ethyl ketone and mixed to obtain a crystal bonding composition with a solid content concentration of 20% by mass. Then, using an applicator, apply the above-mentioned die-bonding composition to the silicone-treated surface of the PET separator (thickness 50 μm) as a release liner so that the thickness becomes 10 μm, at 130°C Dry for 2 minutes to remove the solvent from the above-mentioned die-bonding composition to obtain a die-bonded wafer formed by laminating a die-bonding layer on the release liner. Then, the side of the bonding wafer where the release sheet is not laminated is attached to the adhesive layer of the dicing tape, and then the release liner is peeled from the bonding layer to obtain a dicing chip with a bonding layer Mucous film.

對於如此獲得之切晶帶，以下述方式測定-5℃下之拉伸儲存模數、以及-5℃及23℃下之30%拉伸應力。又，對擴開時晶片自切晶黏晶膜之***(以下稱為晶片***)、以及晶片及黏晶層之切斷性(以下稱為切斷性)進行評價。For the thus-obtained diced tape, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the following manner. In addition, the uplift of the wafer from the die-cut die-bonding film during expansion (hereinafter referred to as wafer uplift) and the cutting properties of the wafer and die-bonding layer (hereinafter referred to as cutting properties) were evaluated.

(-5℃下之拉伸儲存模數) 自實施例1之切晶帶切出長度40 mm(測定長度)×寬度10 mm之試驗片，使用固體黏彈性測定裝置(型號RSAIII、Rheometric Scientific股份有限公司製)，於頻率1 Hz、應變量0.1%、升溫速度10℃/分鐘、治具間距離22.5 mm之條件下，於-50〜100℃之溫度範圍測定上述試驗片之拉伸儲存模數，此時，讀取-5℃下之拉伸彈性模數之值，藉此求出-5℃下之拉伸儲存模數。(Tensile storage modulus at -5℃) A test piece with a length of 40 mm (measurement length)×width 10 mm was cut from the crystal cutting tape of Example 1, and a solid viscoelasticity measuring device (model RSAIII, manufactured by Rheometric Scientific Co., Ltd.) was used at a frequency of 1 Hz and a strain amount. Measure the tensile storage modulus of the above test piece in the temperature range of -50~100℃ under the conditions of 0.1%, heating rate 10℃/min, and 22.5 mm distance between fixtures. At this time, read the value at -5℃ The value of the tensile modulus of elasticity is used to obtain the tensile storage modulus at -5°C.

(-5℃及室溫下之30%拉伸應力) 自實施例1之切晶帶切出長度100 mm×寬度10 mm之試驗片，使用拉伸試驗機(Tensilon萬能試驗機、島津製作所製)，於測定溫度(-5℃及室溫)下，於治具間距離50 mm及拉伸速度100 mm/分鐘之條件下拉伸上述試驗片，測定伸長率達到30%時(治具間距離65 mm)之應力。(30% tensile stress at -5℃ and room temperature) A test piece with a length of 100 mm × a width of 10 mm was cut from the crystal cutting tape of Example 1, and a tensile tester (Tensilon universal testing machine, manufactured by Shimadzu Corporation) was used to measure the temperature (-5°C and room temperature), The above test piece was stretched under the conditions of 50 mm distance between jigs and 100 mm/min tensile speed, and the stress was measured when the elongation reached 30% (distance between jigs 65 mm).

(晶片***之評價) 於實施例1之切晶黏晶膜上貼附裸晶圓(直徑300 mm)及切晶環。繼而，使用晶片分離裝置DDS230(DISCO公司製)進行半導體晶圓及黏晶層之切斷，評價切斷後之晶片***。裸晶圓係切斷成大小為長度12 mm×寬度4 mm×厚度0.055 mm之裸晶片。 再者，作為裸晶圓，使用翹曲晶圓。(Evaluation of chip uplift) A bare wafer (300 mm in diameter) and a dicing ring were attached to the chip dicing adhesive film of Example 1. Then, the semiconductor wafer and the die bonding layer were cut using a wafer separation device DDS230 (manufactured by DISCO), and the wafer swelling after the cut was evaluated. The bare wafer is cut into a bare chip with a length of 12 mm × a width of 4 mm × a thickness of 0.055 mm. Furthermore, as a bare wafer, a warped wafer is used.

翹曲晶圓係以如下方式製作。 首先，使下述(a)〜(f)溶解於甲基乙基酮，獲得固形物成分濃度20質量%之翹曲調整組合物。 (a)丙烯酸樹脂(長瀨化學公司製、商品名「SG-70L」)：5質量份 (b)環氧樹脂(三菱化學公司製、商品名「JER828」)：5質量份 (c)酚樹脂(明和化成公司製、商品名「LDR8210」)：14質量份 (d)環氧樹脂(三菱化學公司製、商品名「MEH-8005」)：2質量份 (e)球狀二氧化矽(Admatechs公司製、商品名「SO-25R」)：53質量份 (f)磷系觸媒(TPP-K)：1質量份 繼而，使用敷料器，將上述翹曲調整組合物以厚度25 μm塗佈於作為剝離襯墊之PET系隔離件(厚度50 μm)之經聚矽氧處理之面上，於130℃下乾燥2分鐘而自上述翹曲調整組合物進行脫溶劑，獲得於上述剝離襯墊上積層有翹曲調整層而成之翹曲調整片。 繼而，使用層壓機(MCK公司製、型號MRK-600)於60℃、0.1 MPa、10 mm/s之條件下將裸晶圓貼附於上述翹曲調整片中之未積層上述剝離襯墊之一側，放入至烘箱中，以175℃加熱1小時而使上述翹曲調整層之樹脂熱硬化，藉此上述翹曲調整層收縮，獲得翹曲之裸晶圓。 於使上述翹曲調整層收縮後，於翹曲之裸晶圓中之未積層上述翹曲調整層之一側貼附晶圓加工用帶(日東電工股份有限公司製、商品名「V-12SR2」)後，經由上述晶圓加工用帶將切晶環固定於翹曲之裸晶圓上。其後，自翹曲之裸晶圓除去上述翹曲調整層。 使用切割裝置(DISCO公司製、型號6361)，於翹曲之裸晶圓之除去了上述翹曲調整層之整個面(以下稱為一面)上以格子狀(寬度20 μm)形成距該面有100 μm深度之槽。 繼而，於翹曲之裸晶圓之一面上貼合背面研磨帶，自翹曲之裸晶圓之另一面(與上述一面相反側之面)除去上述晶圓加工用帶。 繼而，使用背面研磨機(DISCO公司製、型號DGP8760)，自另一面側對翹曲之裸晶圓進行研削以使翹曲之裸晶圓之厚度成為55 μm(0.055 mm)，將所獲得之晶圓作為翹曲晶圓。The warped wafer is produced in the following manner. First, the following (a) to (f) are dissolved in methyl ethyl ketone to obtain a warpage adjusting composition having a solid content of 20% by mass. (a) Acrylic resin (manufactured by Nagase Chemical Co., Ltd., trade name "SG-70L"): 5 parts by mass (b) Epoxy resin (manufactured by Mitsubishi Chemical Corporation, trade name "JER828"): 5 parts by mass (c) Phenolic resin (manufactured by Meiwa Chemical Co., Ltd., trade name "LDR8210"): 14 parts by mass (d) Epoxy resin (manufactured by Mitsubishi Chemical Corporation, trade name "MEH-8005"): 2 parts by mass (e) Spherical silicon dioxide (manufactured by Admatechs, trade name "SO-25R"): 53 parts by mass (f) Phosphorus catalyst (TPP-K): 1 part by mass Then, using an applicator, apply the warpage adjustment composition to a thickness of 25 μm on the silicone-treated surface of a PET separator (thickness 50 μm) as a release liner, and dry at 130°C 2 The solvent was removed from the warpage adjustment composition for minutes to obtain a warpage adjustment sheet in which a warpage adjustment layer was laminated on the release liner. Then, using a laminator (manufactured by MCK, model MRK-600) at 60°C, 0.1 MPa, and 10 mm/s, the bare wafer was attached to the unlaminated release liner in the warpage adjustment sheet. One side is placed in an oven and heated at 175°C for 1 hour to thermally harden the resin of the warpage adjustment layer, whereby the warpage adjustment layer shrinks to obtain a warped bare wafer. After shrinking the warpage adjustment layer, a wafer processing tape (manufactured by Nitto Denko Co., Ltd., trade name "V-12SR2") is attached to the side of the warped bare wafer where the warpage adjustment layer is not laminated. ") Afterwards, the dicing ring is fixed on the warped bare wafer through the above-mentioned wafer processing tape. Thereafter, the warpage adjustment layer is removed from the warped bare wafer. Using a dicing device (manufactured by DISCO, model 6361), the entire surface of the warped bare wafer from which the warpage adjustment layer has been removed (hereinafter referred to as one side) is formed in a grid pattern (width 20 μm) with a distance from the surface. Grooves with a depth of 100 μm. Then, a back polishing tape is attached to one side of the warped bare wafer, and the wafer processing tape is removed from the other side of the warped bare wafer (the side opposite to the above-mentioned one side). Then, using a backside grinder (manufactured by DISCO, model DGP8760), the warped bare wafer was ground from the other side so that the thickness of the warped bare wafer became 55 μm (0.055 mm), and the obtained The wafer serves as a warped wafer.

晶片***係以如下方式詳細地評價。 首先，利用冷擴開單元於擴開溫度-5℃、擴開速度100 mm/秒、擴開量12 mm之條件下切斷裸晶圓及黏晶層，獲得帶有黏晶層之半導體晶片。 繼而，於室溫、擴開速度1 mm/秒、擴開量5 mm之條件下進行擴開。然後，於維持擴開狀態之情況下於加熱溫度200℃、加熱距離18 mm、旋轉速度5°/秒之條件下使與裸晶圓之外周緣之交界部分之切晶黏晶膜熱收縮。 繼而，對於切晶黏晶膜之基材層表面，藉由顯微鏡觀察來拍攝帶有黏晶層之半導體晶片之***狀態並進行二值化，藉此算出***之面積。然後，將***之面積未達4%之情形評價為〇，將為4%以上之情形評價為×。The wafer bump was evaluated in detail in the following manner. First, the cold expansion unit is used to cut the bare wafer and the die bond layer under the conditions of an expansion temperature of -5°C, an expansion speed of 100 mm/sec, and an expansion amount of 12 mm to obtain a semiconductor wafer with a die bond layer. Then, expand at room temperature, expand at 1 mm/sec, and expand at 5 mm. Then, while maintaining the expanded state, the diced mucosal film at the interface with the outer periphery of the bare wafer is heat-shrinked under the conditions of a heating temperature of 200°C, a heating distance of 18 mm, and a rotation speed of 5°/sec. Then, for the surface of the substrate layer of the dicing die attach film, the swelling state of the semiconductor wafer with the die attaching layer is photographed by microscope observation and binarization is performed to calculate the area of the swelling. Then, the case where the area of the uplift is less than 4% is evaluated as ○, and the case where the area of the uplift is more than 4% is evaluated as ×.

(切斷性之評價) 於實施例1之切晶黏晶膜上貼附裸晶圓(直徑300 mm)及切晶環。繼而，使用晶片分離裝置DDS230(DISCO公司製)進行裸晶圓及黏晶層之切斷。 裸晶圓係切斷成大小為長度3.2 mm×寬度1.4 mm×厚度0.025 mm之裸晶片。(Evaluation of severance) A bare wafer (300 mm in diameter) and a dicing ring were attached to the chip dicing adhesive film of Example 1. Then, the bare wafer and the die bonding layer were cut using a wafer separation device DDS230 (manufactured by DISCO). The bare wafer is cut into a bare chip with a length of 3.2 mm × a width of 1.4 mm × a thickness of 0.025 mm.

切斷性係以如下方式詳細地評價。 首先，利用冷擴開單元於擴開溫度-5℃、擴開速度100 mm/秒、擴開量14 mm之條件下切斷裸晶圓及黏晶層，獲得帶有黏晶層之半導體晶片。 繼而，於室溫、擴開速度1 mm/秒、擴開量10 mm之條件下進行擴開。然後，於維持擴開狀態之情況下於加熱溫度200℃、加熱距離18 mm、旋轉速度5°/秒之條件下使與裸晶圓之外周緣之交界部分之切晶黏晶膜熱收縮。 繼而，藉由顯微鏡觀察來觀察帶有黏晶層之半導體晶片之切斷部，並算出切斷率。之後，將切斷率為90%以上之情形評價為〇，將切斷率低於90%之情形評價為×。The cutting property was evaluated in detail in the following manner. First, use the cold expansion unit to cut the bare wafer and the die bond layer under the conditions of an expansion temperature of -5°C, an expansion speed of 100 mm/sec, and an expansion amount of 14 mm to obtain a semiconductor wafer with a die bond layer. Then, expand under the conditions of room temperature, expansion speed 1 mm/sec, and expansion amount 10 mm. Then, while maintaining the expanded state, the diced mucosal film at the interface with the outer periphery of the bare wafer is heat-shrinked under the conditions of a heating temperature of 200°C, a heating distance of 18 mm, and a rotation speed of 5°/sec. Then, the cut portion of the semiconductor wafer with the die-bonding layer was observed by microscope observation, and the cut rate was calculated. After that, the case where the cut rate was 90% or more was evaluated as ○, and the case where the cut rate was less than 90% was evaluated as ×.

[實施例2] 將基材層設為80 μm，除此以外，與實施例1同樣地進行，獲得實施例2之切晶帶及切晶黏晶膜。 又，對於實施例2之切晶帶，與實施例1同樣地測定-5℃下之拉伸儲存模數、以及-5℃及23℃下之30%拉伸應力。 進而對實施例2之切晶黏晶膜評價晶片***及切斷性。[Example 2] Except for setting the base layer to be 80 μm, the same procedure as in Example 1 was carried out to obtain the dicing tape and the dicing sticky film of Example 2. In addition, for the diced tape of Example 2, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1. Furthermore, the wafer swelling and cutting properties of the dicing die attach film of Example 2 were evaluated.

[實施例3] 將構成基材層之B層(中心層)之EVA設為Evaflex EV550(三井杜邦聚化學公司製)，將基材層設為80 μm，除此以外，與實施例1同樣地進行，獲得實施例3之切晶帶及切晶黏晶膜。 又，對於實施例3之切晶帶，與實施例1同樣地測定-5℃下之拉伸儲存模數、以及-5℃及23℃下之30%拉伸應力。 進而對實施例3之切晶黏晶膜評價晶片***及切斷性。[Example 3] The EVA constituting the B layer (center layer) of the base layer was set to Evaflex EV550 (manufactured by Mitsui DuPont Chemical Co., Ltd.), and the base layer was set to 80 μm, except that the same procedure as in Example 1 was carried out. The dicing tape and dicing sticky film of Example 3. In addition, for the dicing tape of Example 3, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1. Furthermore, the die-cutting die-cutting film of Example 3 was evaluated for wafer swelling and cutting properties.

[實施例4] 將B層之樹脂設為丙烯系彈性體(商品名：Vistamaxx3980、ExxonMobil Chemical公司製)，除此以外，與實施例1同樣地進行，獲得實施例4之切晶帶及切晶黏晶膜。 又，對於實施例4之切晶帶，與實施例1同樣地測定-5℃下之拉伸儲存模數、以及-5℃及23℃下之30%拉伸應力。 進而對實施例4之切晶黏晶膜評價晶片***及切斷性。[Example 4] Except that the resin of the B layer was made into an acrylic elastomer (trade name: Vistamaxx3980, manufactured by ExxonMobil Chemical Co., Ltd.), the same procedure as in Example 1 was carried out to obtain the dicing tape and the dicing die attach film of Example 4. In addition, for the diced tape of Example 4, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1. Furthermore, the die-cutting die-bonding film of Example 4 was evaluated for wafer uplift and cutting properties.

[實施例5] 將基材層之厚度設為80 μm，將基材層之層厚比設為A層：B層：C層=1：4：1，除此以外，與實施例1同樣地進行，獲得實施例5之切晶帶及切晶黏晶膜。 又，對於實施例5之切晶帶，與實施例1同樣地測定-5℃下之拉伸儲存模數、以及-5℃及23℃下之30%拉伸應力。 進而對實施例5之切晶黏晶膜評價晶片***及切斷性。[Example 5] The thickness of the substrate layer was set to 80 μm, and the layer thickness ratio of the substrate layer was set to A layer: B layer: C layer = 1:4:1, except that the same procedure as in Example 1 was carried out to obtain the implementation Example 5 of the dicing tape and the dicing chip adhesive film. In addition, for the diced tape of Example 5, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1. Furthermore, the die-cutting die-cutting film of Example 5 was evaluated for wafer swelling and cutting properties.

[實施例6] 將構成基材層之A層及C層(外層)之茂金屬PP設為WINTEC WMX03(日本聚丙烯公司製)，除此以外，與實施例1同樣地進行，獲得實施例6之切晶帶及切晶黏晶膜。 又，對於實施例6之切晶帶，與實施例1同樣地測定-5℃下之拉伸儲存模數、以及-5℃及23℃下之30%拉伸應力。 進而對實施例6之切晶黏晶膜評價晶片***及切斷性。[Example 6] Except that the metallocene PP constituting the A layer and the C layer (outer layer) of the base layer was set to WINTEC WMX03 (manufactured by Nippon Polypropylene Co., Ltd.), the same procedure as in Example 1 was carried out to obtain the crystal cut tape of Example 6 And diced crystal sticky film. In addition, for the diced tape of Example 6, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1. Furthermore, the die-cutting die-cutting film of Example 6 was evaluated for wafer swelling and cutting properties.

[實施例7] 將構成基材層之B層之EVA樹脂設為Ultrathene651(三井杜邦聚化學公司製)，除此以外，與實施例1同樣地進行，獲得實施例7之切晶帶及切晶黏晶膜。 又，對於實施例7之切晶帶，與實施例1同樣地測定-5℃下之拉伸儲存模數、以及-5℃及23℃下之30%拉伸應力。 進而對實施例7之切晶黏晶膜評價晶片***及切斷性。[Example 7] Except that the EVA resin constituting the layer B of the base layer was Ultrathene651 (manufactured by Mitsui DuPont Chemical Co., Ltd.), the same procedure as in Example 1 was carried out to obtain the dicing tape and the dicing adhesive film of Example 7. In addition, for the diced tape of Example 7, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1. Furthermore, the die-cutting die-cutting film of Example 7 was evaluated for wafer swelling and cutting properties.

[實施例8] 將基材層設為單層構造，將基材層之厚度設為125 μm，除此以外，與實施例1同樣地進行，獲得實施例8之切晶帶及切晶黏晶膜。 基材層係使用單層擠出T模成形機來成形。作為基材層之樹脂，使用丙烯系彈性體(商品名：Vistamaxx3980、ExxonMobil Chemical公司製)。 又，對於實施例8之切晶帶，與實施例1同樣地測定-5℃下之拉伸儲存模數、以及-5℃及23℃下之30%拉伸應力。 進而對實施例8之切晶黏晶膜評價晶片***及切斷性。[Example 8] The substrate layer was made into a single layer structure, and the thickness of the substrate layer was set to 125 μm, except that the same procedure as in Example 1 was carried out to obtain the diced wafer and the diced wafer of Example 8. The substrate layer was formed using a single-layer extrusion T-die forming machine. As the resin of the base layer, a propylene-based elastomer (trade name: Vistamaxx3980, manufactured by ExxonMobil Chemical Co., Ltd.) was used. In addition, for the diced tape of Example 8, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1. Furthermore, the die-cutting die-cutting film of Example 8 was evaluated for wafer swelling and cutting properties.

[實施例9] 將基材層之厚度設為100 μm，除此以外，與實施例8同樣地進行，獲得實施例9之切晶帶及切晶黏晶膜。 又，對於實施例9之切晶帶，與實施例1同樣地測定-5℃下之拉伸儲存模數、以及-5℃及23℃下之30%拉伸應力。 進而對實施例9之切晶黏晶膜評價晶片***及切斷性。[Example 9] Except for setting the thickness of the base layer to 100 μm, the same procedure as in Example 8 was carried out to obtain the dicing tape and the dicing sticky film of Example 9. In addition, for the diced tape of Example 9, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1. Furthermore, the die-cutting die-cutting film of Example 9 was evaluated for wafer swelling and cutting properties.

[比較例1] 將基材層之樹脂設為Evaflex EV250(三井杜邦聚化學公司製)，除此以外，與實施例8同樣地進行，獲得比較例1之切晶帶及切晶黏晶膜。 又，對於比較例1之切晶帶，與實施例1同樣地測定-5℃下之拉伸儲存模數、以及-5℃及23℃下之30%拉伸應力。 進而，對於比較例1之切晶黏晶膜評價晶片***及切斷性。[Comparative Example 1] Except that the resin of the base layer was Evaflex EV250 (manufactured by Mitsui DuPont Chemical Co., Ltd.), the same procedure as in Example 8 was carried out to obtain a dicing tape and a dicing adhesive film of Comparative Example 1. In addition, for the dicing tape of Comparative Example 1, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1. Furthermore, the wafer swelling and cutting properties were evaluated for the dicing die attach film of Comparative Example 1.

[比較例2] 將基材層之厚度設為100 μm，除此以外，與比較例1同樣地進行，獲得比較例2之切晶帶及切晶黏晶膜。 又，對於比較例2之切晶帶，與實施例1同樣地測定-5℃下之拉伸儲存模數、以及-5℃及23℃下之30%拉伸應力。 進而，對於比較例2之切晶黏晶膜評價晶片***及切斷性。[Comparative Example 2] Except that the thickness of the base layer was set to 100 μm, the same procedure as in Comparative Example 1 was carried out to obtain a dicing tape and a dicing sticky film of Comparative Example 2. In addition, for the dicing tape of Comparative Example 2, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1. Furthermore, the die-cut die-cut film of Comparative Example 2 was evaluated for wafer uplift and cutting properties.

將各例之切晶帶之-5℃下之拉伸儲存模數、-5℃及23℃下之拉伸應力之測定結果、以及各例之切晶黏晶膜之晶片***及切斷性之評價結果示於以下表1。The tensile storage modulus at -5°C, the tensile stress measurement results at -5°C and 23°C of the dicing tape of each example, and the wafer uplift and cutting properties of the dicing adhesive film of each example The evaluation results are shown in Table 1 below.

[表1]    實施例1 實施例2 實施例3 實施例4 實施例5 實施例6 基材層 層構成 3層 3層 3層 3層 3層 3層 層厚比 (A層：B層：C層) 1：10：1 1：10：1 1：10：1 1：10：1 1：4：1 1：10：1 樹脂 (A層/B層/C層) WXK1233/EV250/ WXK1233 WXK1233/EV250/WXK1233 WXK1233/EV550/ WXK1233 WXK1233/Vistamaxx/WXK1233 WXK1233/EV250/WXK1233 WMX03/EV250/WMX03 厚度[μm] 100 80 80 100 80 100 黏著劑層 厚度[μm] 10 10 10 10 10 10 黏晶層 厚度[μm] 10 10 10 10 10 10 -5℃下之初始彈性模數[MPa] 304.4 304.4 280.7 323.2 377.4 105.7 -5℃下之30%拉伸應力[N/10 mm] 10.7 8.6 9.5 15.0 10.6 6.7 室溫下之30%拉伸應力 [N/10 mm] 5.3 3.2 3.9 7.1 5.1 3.7 拉伸應力之比(-5℃/室溫) 2.0 2.7 1.4 2.1 2.1 1.8 晶片*** 〇 〇 〇 〇 〇 〇 切斷性 〇 〇 〇 〇 〇 〇    實施例7 實施例8 實施例9 比較例1 比較例2    基材層 層構成 3層 單層 單層 單層 單層    層厚比 (A層：B層：C層) 1：10：1 - - - -    樹脂 (A層/B層/C層) WXK1233/Ultrathene/WXK1233 Vistamaxx Vistamaxx EV250 EV250    厚度[μm] 100 125 100 125 100    黏著劑層 厚度[μm] 10 10 10 10 10    黏晶層 厚度[μm] 10 10 10 10 10    -5℃下之初始彈性模數[MPa] 110.5 184.8 184.8 21.1 21.1    -5℃下之30%拉伸應力[N/10 mm] 7.1 16.7 13.4 5.0 4.0    室溫下之30%拉伸應力[N/10 mm] 4.2 7.8 6.2 3.1 2.5    拉伸應力之比(-5℃/室溫) 1.7 2.1 2.2 1.6 1.6    晶片*** 〇 × × × ×    切斷性 〇 〇 〇 × ×    [Table 1] Example 1 Example 2 Example 3 Example 4 Example 5 Example 6 Substrate layer Layer composition 3 layers 3 layers 3 layers 3 layers 3 layers 3 layers Layer thickness ratio (layer A: layer B: layer C) 1:10:1 1:10:1 1:10:1 1:10:1 1: 4: 1 1:10:1 Resin (layer A/layer B/layer C) WXK1233/EV250/ WXK1233 WXK1233/EV250/WXK1233 WXK1233/EV550/ WXK1233 WXK1233/Vistamaxx/WXK1233 WXK1233/EV250/WXK1233 WMX03/EV250/WMX03 Thickness [μm] 100 80 80 100 80 100 Adhesive layer Thickness [μm] 10 10 10 10 10 10 Sticky layer Thickness [μm] 10 10 10 10 10 10 Initial modulus of elasticity at -5℃ [MPa] 304.4 304.4 280.7 323.2 377.4 105.7 30% tensile stress at -5℃ [N/10 mm] 10.7 8.6 9.5 15.0 10.6 6.7 30% tensile stress at room temperature [N/10 mm] 5.3 3.2 3.9 7.1 5.1 3.7 Ratio of tensile stress (-5℃/room temperature) 2.0 2.7 1.4 2.1 2.1 1.8 Wafer bump 〇 〇 〇 〇 〇 〇 Severance 〇 〇 〇 〇 〇 〇 Example 7 Example 8 Example 9 Comparative example 1 Comparative example 2 Substrate layer Layer composition 3 layers Single layer Single layer Single layer Single layer Layer thickness ratio (layer A: layer B: layer C) 1:10:1 - - - - Resin (layer A/layer B/layer C) WXK1233/Ultrathene/WXK1233 Vistamaxx Vistamaxx EV250 EV250 Thickness [μm] 100 125 100 125 100 Adhesive layer Thickness [μm] 10 10 10 10 10 Sticky layer Thickness [μm] 10 10 10 10 10 Initial modulus of elasticity at -5℃ [MPa] 110.5 184.8 184.8 21.1 21.1 30% tensile stress at -5℃ [N/10 mm] 7.1 16.7 13.4 5.0 4.0 30% tensile stress at room temperature [N/10 mm] 4.2 7.8 6.2 3.1 2.5 Ratio of tensile stress (-5℃/room temperature) 1.7 2.1 2.2 1.6 1.6 Wafer bump 〇 X X X X Severance 〇 〇 〇 X X

自表1可知，實施例1〜9之切晶帶之-5℃下之拉伸儲存模數之值均顯示為100 MPa以上，實施例1〜9之切晶黏晶膜之切斷性優異。 又，自表1可知，具備實施例1〜7之切晶帶、即基材層為三層構造之切晶帶之實施例1〜7之切晶黏晶膜均抑制了晶片***。 與此相對，可知：比較例1及2之切晶帶之-5℃下之拉伸儲存模數之值均低於100 MPa，比較例1及2之切晶黏晶膜之切斷性較差，並且無法抑制晶片***。 再者，表1所揭示之結果係與切晶黏晶膜相關者，但預測切晶黏晶膜中所含之切晶帶亦可獲得與表1所示者同樣之結果。 [關聯申請之相互參照]It can be seen from Table 1 that the tensile storage modulus at -5°C of the crystal sliced tapes of Examples 1 to 9 are all shown to be more than 100 MPa, and the crystal sliced mucous membranes of Examples 1 to 9 have excellent cutting properties . In addition, it can be seen from Table 1 that the dicing adhesive films of Examples 1 to 7 having the dicing tapes of Examples 1-7, that is, the dicing tape with a three-layer structure of the substrate layer, all suppressed wafer swelling. In contrast, it can be seen that the tensile storage modulus at -5°C of the dicing tapes of Comparative Examples 1 and 2 are all lower than 100 MPa, and the cutting performance of the dicing mucous film of Comparative Examples 1 and 2 is poor. , And can not suppress wafer swelling. Furthermore, the results disclosed in Table 1 are related to the chip adhesive film, but it is predicted that the dicing tape contained in the chip adhesive film can also obtain the same results as those shown in Table 1. [Cross Reference of Related Applications]

本申請案主張日本專利特願2019-110200號之優先權，且藉由引用而併入至本申請案說明書之記載中。This application claims the priority of Japanese Patent Application No. 2019-110200, and is incorporated into the description of the specification of this application by reference.

1:基材層 1a:第1樹脂層 1b:第2樹脂層 1c:第3樹脂層 2:黏著劑層 3:黏晶層 10:切晶帶 20:切晶黏晶膜 G:背面研磨帶 H:保持器 J:吸附治具 P:頂銷構件 R:切晶環 T:晶圓加工用帶 U:頂起構件 W:半導體晶圓1: Substrate layer 1a: The first resin layer 1b: The second resin layer 1c: 3rd resin layer 2: Adhesive layer 3: Sticky crystal layer 10: Cut crystal belt 20: slicing and sticking film G: Back grinding tape H: retainer J: Adsorption fixture P: ejector component R: Slicing ring T: Tape for wafer processing U: Jack up member W: semiconductor wafer

圖1係表示本發明之一實施方式之切晶帶之構成的剖視圖。 圖2係表示本發明之一實施方式之切晶黏晶膜之構成的剖視圖。 圖3A係模式性地表示半導體積體電路之製造方法中之半切割加工之狀態的剖視圖。 圖3B係模式性地表示半導體積體電路之製造方法中之半切割加工之狀態的剖視圖。 圖3C係模式性地表示半導體積體電路之製造方法中之背面研磨加工之狀態的剖視圖。 圖3D係模式性地表示半導體積體電路之製造方法中之背面研磨加工之狀態的剖視圖。 圖4A係模式性地表示半導體積體電路之製造方法中之安裝步驟之狀態的剖視圖。 圖4B係模式性地表示半導體積體電路之製造方法中之安裝步驟之狀態的剖視圖。 圖5A係模式性地表示半導體積體電路之製造方法中之低溫下之擴開步驟的狀態之剖視圖。 圖5B係模式性地表示半導體積體電路之製造方法中之低溫下之擴開步驟的狀態之剖視圖。 圖5C係模式性地表示半導體積體電路之製造方法中之低溫下之擴開步驟的狀態之剖視圖。 圖6A係模式性地表示半導體積體電路之製造方法中之常溫下之擴開步驟的狀態之剖視圖。 圖6B係模式性地表示半導體積體電路之製造方法中之常溫下之擴開步驟的狀態之剖視圖。 圖7係模式性地表示半導體積體電路之製造方法中之切口維持步驟之狀態的剖視圖。 圖8係模式性地表示半導體積體電路之製造方法中之拾取步驟之狀態的剖視圖。Fig. 1 is a cross-sectional view showing the structure of a dicing tape according to an embodiment of the present invention. Fig. 2 is a cross-sectional view showing the structure of a dicing die bond film according to an embodiment of the present invention. 3A is a cross-sectional view schematically showing the state of half-cutting in the method of manufacturing a semiconductor integrated circuit. FIG. 3B is a cross-sectional view schematically showing the state of the half-cutting process in the manufacturing method of the semiconductor integrated circuit. FIG. 3C is a cross-sectional view schematically showing the state of the back grinding process in the manufacturing method of the semiconductor integrated circuit. FIG. 3D is a cross-sectional view schematically showing the state of the back grinding process in the manufacturing method of the semiconductor integrated circuit. 4A is a cross-sectional view schematically showing the state of the mounting step in the manufacturing method of the semiconductor integrated circuit. 4B is a cross-sectional view schematically showing the state of the mounting step in the manufacturing method of the semiconductor integrated circuit. FIG. 5A is a cross-sectional view schematically showing the state of the expansion step at a low temperature in the manufacturing method of the semiconductor integrated circuit. FIG. 5B is a cross-sectional view schematically showing the state of the expansion step at a low temperature in the manufacturing method of the semiconductor integrated circuit. FIG. 5C is a cross-sectional view schematically showing the state of the expansion step at a low temperature in the manufacturing method of the semiconductor integrated circuit. 6A is a cross-sectional view schematically showing the state of the expansion step at room temperature in the manufacturing method of the semiconductor integrated circuit. FIG. 6B is a cross-sectional view schematically showing the state of the expansion step at room temperature in the manufacturing method of the semiconductor integrated circuit. FIG. 7 is a cross-sectional view schematically showing the state of the cut maintaining step in the manufacturing method of the semiconductor integrated circuit. FIG. 8 is a cross-sectional view schematically showing the state of the pickup step in the manufacturing method of the semiconductor integrated circuit.

1:基材層 1: Substrate layer

1a:第1樹脂層 1a: The first resin layer

1b:第2樹脂層 1b: The second resin layer

1c:第3樹脂層 1c: 3rd resin layer

2:黏著劑層 2: Adhesive layer

10:切晶帶 10: Cut crystal belt

Claims (7)

一種切晶帶，其係 於基材層上積層黏著劑層而成者， 該切晶帶之-5℃下之拉伸儲存模數為100 MPa以上。A kind of slicing tape, which is It is formed by laminating an adhesive layer on the substrate layer, The tensile storage modulus at -5°C of the dicing tape is more than 100 MPa. 如請求項1之切晶帶，其 -5℃下之30%拉伸應力為5.5 N/10 mm以上。Such as the crystal cut tape of claim 1, which The 30% tensile stress at -5℃ is 5.5 N/10 mm or more. 如請求項1或2之切晶帶，其 室溫下之30%拉伸應力為3.2 N/10 mm以上。Such as the dicing tape of claim 1 or 2, which The 30% tensile stress at room temperature is 3.2 N/10 mm or more. 如請求項1之切晶帶，其 -5℃下之30%拉伸應力相對於室溫下之30%拉伸應力之比為1.7以上。Such as the crystal cut tape of claim 1, which The ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 1.7 or more. 如請求項2之切晶帶，其 -5℃下之30%拉伸應力相對於室溫下之30%拉伸應力之比為1.7以上。Such as the crystal cut tape of claim 2, which The ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 1.7 or more. 如請求項3之切晶帶，其 -5℃下之30%拉伸應力相對於室溫下之30%拉伸應力之比為1.7以上。Such as the crystal cut tape of claim 3, which The ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 1.7 or more. 一種切晶黏晶膜，其具備： 於基材層上積層黏著劑層而成之切晶帶、及 積層於上述切晶帶之黏著劑層上之黏晶層，且 該切晶黏晶膜之-5℃下之拉伸儲存模數為100 MPa以上。A diced chip adhesive film, which has: Die-cutting tape formed by laminating an adhesive layer on the substrate layer, and A die-bonding layer laminated on the adhesive layer of the above-mentioned die-cutting tape, and The tensile storage modulus at -5°C of the diced sticky film is more than 100 MPa.

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