CN1119834C - 半导体存储器件的制造方法及其结构 - Google Patents
半导体存储器件的制造方法及其结构 Download PDFInfo
- Publication number
- CN1119834C CN1119834C CN99109414A CN99109414A CN1119834C CN 1119834 C CN1119834 C CN 1119834C CN 99109414 A CN99109414 A CN 99109414A CN 99109414 A CN99109414 A CN 99109414A CN 1119834 C CN1119834 C CN 1119834C
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- Prior art keywords
- insulating barrier
- material layer
- opening portion
- contact openings
- neighboring area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 239000000463 material Substances 0.000 claims abstract description 65
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 44
- 238000005530 etching Methods 0.000 claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims description 59
- 239000000758 substrate Substances 0.000 claims description 31
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 239000003990 capacitor Substances 0.000 claims description 11
- 238000005260 corrosion Methods 0.000 claims description 11
- 230000007797 corrosion Effects 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 238000003860 storage Methods 0.000 claims description 9
- 239000010937 tungsten Substances 0.000 claims description 8
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- -1 tungsten nitride Chemical class 0.000 claims description 4
- 230000009977 dual effect Effects 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 55
- 239000011229 interlayer Substances 0.000 description 20
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 9
- 238000000151 deposition Methods 0.000 description 7
- 238000009413 insulation Methods 0.000 description 3
- 238000002310 reflectometry Methods 0.000 description 3
- 208000005189 Embolism Diseases 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (17)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980026585A KR100279298B1 (ko) | 1998-07-02 | 1998-07-02 | 반도체 메모리 장치의 제조 방법 및 그 구조 |
KR26585/98 | 1998-07-02 | ||
KR26585/1998 | 1998-07-02 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1241031A CN1241031A (zh) | 2000-01-12 |
CN1119834C true CN1119834C (zh) | 2003-08-27 |
Family
ID=19542818
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN99109414A Expired - Fee Related CN1119834C (zh) | 1998-07-02 | 1999-06-29 | 半导体存储器件的制造方法及其结构 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6337267B1 (zh) |
JP (1) | JP4064005B2 (zh) |
KR (1) | KR100279298B1 (zh) |
CN (1) | CN1119834C (zh) |
TW (1) | TW512516B (zh) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100317972B1 (ko) * | 1999-11-05 | 2001-12-24 | 윤종용 | 반도체 집적회로의 커패시터 제조방법 및 그에 의해제조된 커패시터 |
KR100400302B1 (ko) * | 2000-06-30 | 2003-10-01 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
KR100431656B1 (ko) * | 2001-09-11 | 2004-05-17 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
KR100444773B1 (ko) * | 2001-12-18 | 2004-08-21 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
KR100434511B1 (ko) * | 2002-08-12 | 2004-06-05 | 삼성전자주식회사 | 다마신 배선을 이용한 반도체 소자의 제조방법 |
US6835653B1 (en) * | 2003-09-16 | 2004-12-28 | Nanya Technology Corp. | Method of forming adjacent holes on a semiconductor substrate |
KR100570059B1 (ko) | 2003-12-15 | 2006-04-10 | 주식회사 하이닉스반도체 | 반도체 소자의 메탈콘택 형성 방법 |
US7135401B2 (en) * | 2004-05-06 | 2006-11-14 | Micron Technology, Inc. | Methods of forming electrical connections for semiconductor constructions |
JP2006196511A (ja) * | 2005-01-11 | 2006-07-27 | Sony Corp | 半導体集積回路 |
KR100652409B1 (ko) * | 2005-05-06 | 2006-12-01 | 삼성전자주식회사 | 콘택이 구비된 반도체소자 및 그 제조방법 |
KR100650632B1 (ko) * | 2005-11-10 | 2006-11-27 | 삼성전자주식회사 | 캐패시터의 제조 방법 및 이를 이용한 반도체 장치의 제조방법 |
KR101400061B1 (ko) * | 2007-12-07 | 2014-06-27 | 삼성전자주식회사 | 커패시터, 커패시터를 포함하는 반도체 장치, 커패시터의형성 방법 및 커패시터를 포함하는 반도체 장치의 제조방법 |
KR20090068730A (ko) * | 2007-12-24 | 2009-06-29 | 주식회사 동부하이텍 | 반도체 소자 및 그의 제조 방법 |
KR101414076B1 (ko) * | 2008-09-10 | 2014-07-02 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
JP6948892B2 (ja) * | 2017-09-19 | 2021-10-13 | キオクシア株式会社 | 半導体記憶装置 |
CN108054135B (zh) * | 2017-11-10 | 2020-09-01 | 上海华力微电子有限公司 | 接触孔的金属连接结构及其制造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100219483B1 (ko) * | 1996-06-03 | 1999-09-01 | 윤종용 | 반도체 장치의 커패시터 제조방법 |
US6238971B1 (en) * | 1997-02-11 | 2001-05-29 | Micron Technology, Inc. | Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures |
US6214727B1 (en) * | 1997-02-11 | 2001-04-10 | Micron Technology, Inc. | Conductive electrical contacts, capacitors, DRAMs, and integrated circuitry, and methods of forming conductive electrical contacts, capacitors, DRAMs, and integrated circuitry |
US5920790A (en) * | 1997-08-29 | 1999-07-06 | Motorola, Inc. | Method of forming a semiconductor device having dual inlaid structure |
US6143640A (en) * | 1997-09-23 | 2000-11-07 | International Business Machines Corporation | Method of fabricating a stacked via in copper/polyimide beol |
KR100258576B1 (ko) * | 1997-11-04 | 2000-06-15 | 윤종용 | 반도체 장치의 마이크로 콘택 형성 방법 |
KR100292940B1 (ko) * | 1998-03-30 | 2001-07-12 | 윤종용 | 디램 셀 캐패시터의 제조 방법 |
KR100327123B1 (ko) * | 1998-03-30 | 2002-08-24 | 삼성전자 주식회사 | 디램셀캐패시터의제조방법 |
JP2000106396A (ja) * | 1998-09-29 | 2000-04-11 | Sharp Corp | 半導体装置の製造方法 |
-
1998
- 1998-07-02 KR KR1019980026585A patent/KR100279298B1/ko not_active IP Right Cessation
-
1999
- 1999-05-06 TW TW088107370A patent/TW512516B/zh not_active IP Right Cessation
- 1999-06-29 CN CN99109414A patent/CN1119834C/zh not_active Expired - Fee Related
- 1999-07-01 JP JP18780999A patent/JP4064005B2/ja not_active Expired - Fee Related
- 1999-07-02 US US09/347,821 patent/US6337267B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR100279298B1 (ko) | 2001-02-01 |
JP4064005B2 (ja) | 2008-03-19 |
JP2000031429A (ja) | 2000-01-28 |
KR20000007306A (ko) | 2000-02-07 |
TW512516B (en) | 2002-12-01 |
CN1241031A (zh) | 2000-01-12 |
US6337267B1 (en) | 2002-01-08 |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: MOSAID TECHNOLOGIES INC. Free format text: FORMER OWNER: SAMSUNG ELECTRONICS CO., LTD. Effective date: 20120313 |
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C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20120313 Address after: Ontario, Canada Patentee after: Mosaid Technologies Inc. Address before: Gyeonggi Do, South Korea Patentee before: Samsung Electronics Co., Ltd. |
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C56 | Change in the name or address of the patentee |
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. Free format text: FORMER NAME: MOSAID TECHNOLOGIES INC. |
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CP01 | Change in the name or title of a patent holder |
Address after: Ontario, Canada Patentee after: Examine Vincent Zhi Cai management company Address before: Ontario, Canada Patentee before: Mosaid Technologies Inc. |
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CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20030827 Termination date: 20160629 |
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CF01 | Termination of patent right due to non-payment of annual fee |