CN110223980B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN110223980B
CN110223980B CN201910146551.1A CN201910146551A CN110223980B CN 110223980 B CN110223980 B CN 110223980B CN 201910146551 A CN201910146551 A CN 201910146551A CN 110223980 B CN110223980 B CN 110223980B
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semiconductor device
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CN110223980A (zh
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岩岛弥生
平林康弘
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Denso Corp
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Denso Corp
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Abstract

一种半导体装置具有包括元件范围和周边范围的半导体衬底。半导体衬底包括：体区，其布置在元件范围内；p型深区，其从元件范围跨周边范围布置，从半导体衬底的上表面分布到比每个栅极沟槽的下端深的位置，并且包含端栅极沟槽；以及p型耐压区，其布置在周边范围内，并且从上表面分布到比p型深区的下端浅的位置。p型深区内的p型杂质浓度在从体区朝向p型耐压区的方向上增加。

Description

半导体装置
技术领域
本申请中公开的技术涉及一种半导体装置。
背景技术
日本专利申请公开第2016-018848号公开了一种包括元件范围和周边范围的半导体装置。在该元件范围内，提供了一种绝缘栅双极型晶体管(IGBT)。p型深区设置在元件范围与周边范围之间的边界处。该深区从半导体衬底的上表面分布到比每个栅极沟槽的下端低的位置。该深区包含位于元件范围的端部处的栅极沟槽。通过设置该深区，可以抑制电场集中在位于元件范围的端部处的栅极沟槽附近。
发明内容
已知一种在元件范围内设置有IGBT和二极管的半导体装置。提供带有上述深区的这种半导体装置会产生将二极管的恢复电流集中到深区的问题。在本说明书中，提出了一种半导体装置，其能够抑制深区的电场集中，并且还抑制深区中的恢复电流的集中。
本申请公开的半导体装置包括：半导体衬底、上部电极、下部电极和栅电极。所述半导体衬底包括元件范围和设置在所述元件范围之外的周边范围，在所述元件范围中，多个栅极沟槽设置在所述半导体衬底的上表面上。所述上部电极设置在所述半导体衬底的所述上表面上。所述下部电极设置在所述半导体衬底的下表面上。所述栅电极布置在每个栅极沟槽内，并且通过栅极绝缘膜与所述半导体衬底电绝缘。所述半导体衬底包括发射极区、体区、深区、耐压区、漂移区、集电极区和阴极区。所述发射极区是n型区，其布置在所述元件范围内，连接至所述上部电极，并且与所述栅极绝缘膜接触。所述体区是p型区，其布置在所述元件范围内，并且在所述发射极区下方与所述栅极绝缘膜接触。所述深区是p型区，其从所述元件范围跨所述周边范围布置，从所述上表面分布到比每个栅极沟槽的下端深的位置，并且包含所述多个栅极沟槽中的最靠近所述周边范围设置的端栅极沟槽。所述耐压区是p型区，其布置在所述周边范围内，并且从所述上表面分布到比所述深区的下端浅的位置。所述漂移区是n型区，其从所述元件范围跨所述周边范围布置，在所述体区下方与所述栅极绝缘膜接触，通过所述体区与所述发射极区分隔开，从下方与所述深区接触，并从下方与所述耐压区接触。所述集电极区是p型区，其布置在所述漂移区下方，并与所述下部电极接触。所述阴极区n型区，其布置在所述漂移区下方，并与所述下部电极接触。所述深区内的p型杂质浓度在从所述体区朝向所述耐压区的方向上增加。
所述深区内的p型杂质浓度可在深度方向上改变。在这种情况下，该深区中的特定深度处的p型杂质浓度可在从所述体区朝向所述耐压区的方向上增加。
在该半导体装置中，由于深区内的p型杂质浓度在耐压区侧较高，所以在半导体装置关断的同时，等势线可能在横向方向上从元件区朝向耐压区延伸。因此，抑制了电场集中在位于元件区的端部处的栅极沟槽附近。另外，二极管的恢复电流可能集中到体区附近的深区。在半导体装置中，由于深区内的p型杂质浓度在体区侧较低，因此位于体区附近的深区的电阻较高。因此，电流不太可能流过位于体区附近的深区。结果，抑制了恢复电流集中到深区。
附图说明
下面将参照附图描述本发明的实例性实施例的特征、优势以及技术和工业意义，其中相同附图标记表示相同元件，并且其中：
图1是半导体装置10的平面图；
图2是沿图1的线II-II截取的剖面图；
图3是沿图1的线III-III截取的剖面图；
图4是示出p型杂质浓度沿着图2的直线IV的分布的曲线图；
图5示出了图2的相同部分中的电势分布和恢复电流的路径；
图6是变形例的半导体装置的对应于图2的剖面图；并且
图7是变形例的半导体装置的对应于图2的剖面图。
具体实施方式
图1中所示的实施例的半导体装置10包括半导体衬底12。两个上部电极14和多个信号电极17设置在半导体衬底12的上表面12a上。半导体衬底12在每个上部电极14下方包括IGBT范围20和二极管范围22。注意，在图1中，为了更容易理解附图，二极管范围22由斜线阴影线表示。IGBT设置在IGBT范围20内，并且二极管设置在二极管范围22内。在下文中，IGBT范围20以及二极管范围22统称为元件范围24。在每个元件范围24中，IGBT范围20和二极管范围22交替布置。周边范围26围绕相应的元件范围24布置。周边范围26布置在半导体衬底12的元件范围24与外周端面12c之间。周边范围26设置成加强半导体装置10的耐压性。在以下的说明中，较靠近外周端面12c的一侧被称为外周侧，而与该侧相反的一侧(更远离外周端面12c的一侧)被称为内周侧。
如图2、图3中所示，下部电极16设置在半导体衬底12的下表面12b上。下部电极16覆盖半导体衬底12的整个下表面12b。
如图2、图3中所示，多个栅极沟槽30以恒定间隔布置在元件范围24内的半导体衬底12的上表面12a中(即，IGBT范围20和二极管范围22)。多个栅极沟槽30彼此平行地延伸。每个栅极沟槽30的内表面覆盖有栅极绝缘膜32。栅电极34布置在每个栅极沟槽30中。栅电极34通过栅极绝缘膜32与半导体衬底12电绝缘。栅电极34的上表面覆盖有层间绝缘膜36。栅电极34通过层间绝缘膜36与上部电极14电绝缘。
如图2中所示，在IGBT范围20内，发射极区40、上体区42、势垒区44和下体区46设置在由相邻的栅极沟槽30夹着的每个范围内。
发射极区40是具有较高n型杂质浓度的n型区。发射极区40布置在包括上表面12a的范围内，并且与上部电极14欧姆接触。发射极区40在栅极沟槽30的上端处与栅极绝缘膜32接触。
上体区42是p型区。上体区42包括接触区域42a和低浓度区域42b。接触区域42a具有比低浓度区域42b中更高的p型杂质浓度。接触区域42a布置在包括上表面12a的范围内，并且与上部电极14欧姆接触。低浓度区域42b布置在接触区域42a和发射极区40下方。低浓度区域42b在发射极区40下方与栅极绝缘膜32接触。
势垒区44是具有较低n型杂质浓度的n型区域，并且布置在低浓度区域42b下方。势垒区44通过上体区42与发射极区40分隔开。势垒区44在低浓度区域42b下方与栅极绝缘膜32接触。
下体区46是p型区，并且布置在势垒区44下方。下体区46通过势垒区44与上体区42分隔开。下体区46在势垒区44下方与栅极绝缘膜32接触。
深区50布置在IGBT范围20(即，元件范围24)和周边范围26之间的边界处。深区50是p型区。深区50从半导体衬底12的上表面12a分布到低于每个栅极沟槽30的下端的位置。深区50包含多个栅极沟槽30，多个栅极沟槽30包括位于最外周侧(周边范围26侧)的端栅极沟槽30a。也就是说，深区50包含多个栅极沟槽30中的最靠近外周侧设置的一些栅极沟槽。深区50在位于外周侧的多个栅极沟槽30的整个侧表面及整个底表面上与栅极绝缘膜32接触。深区50与上体区42、势垒区44和下体区46相邻。深区50包括接触区域50a、50b和低浓度区域50c。接触区域50a、50b设置在靠近上表面12a的外表面层上。接触区域50a设置在深区50的内周侧(上体区42侧)的部分中。接触区域50a与上部电极14欧姆接触。接触区域50b设置在深区50的外周侧的部分中。接触区域50b与电极18接触。低浓度区域50c布置在接触区域50a、50b下方。低浓度区域50c分布到低于各个栅极沟槽30的下端的位置。低浓度区域50c的p型杂质浓度低于接触区域50a、50b的p型杂质浓度。
在周边范围26内，提供了降低表面电场区域60。降低表面电场区域60是p型区。降低表面电场区域60布置在包括半导体衬底12的上表面12a的范围内。降低表面电场区域60从上表面12a分布到比深区50的下端浅的位置。降低表面电场区域60在外周侧与深区50相邻。当在从上方的平面图中观看半导体衬底12时，降低表面电场区域60围绕元件范围24的周边。
图4示出了沿图2的线IV截取的、低浓度区域50c和降低表面电场区域60内的p型杂质浓度。如图4所示，低浓度区域50c内的p型杂质浓度在从内周侧(即，上体区42侧)朝向外周侧(即，降低表面电场区域60侧)的方向上连续地增加。如图2所示，低浓度区域50c在从内周侧朝向外周侧的方向上变得更深。这是因为，在半导体装置10的制造工艺中，p型杂质的扩散距离在p型杂质浓度较高的外周侧比在p型杂质浓度较低的内周侧变长。如图4所示，降低表面电场区域60内的p型杂质浓度在从内周(低浓度区域50c侧)朝向外周侧的方向上减小。低浓度区域50c内的p型杂质浓度的峰值(最大值)高于降低表面电场区域60内的p型杂质浓度的峰值(最大值)。低浓度区域50c内的p型杂质浓度的峰值低于接触区域42a、50a、50b内的p型杂质浓度。
如图2所示，漂移区70布置在下体区46、深区50和降低表面电场区域60下方。漂移区70从元件范围24跨周边范围26分布。漂移区70从下方与下体区46、深区50和降低表面电场区域60接触。漂移区70在下体区46下方与栅极绝缘膜32接触。漂移区70在降低表面电场区域60的周向外侧与半导体衬底12的上表面12a接触。在周边范围26内，高浓度n型区域72布置在远离降低表面电场区域60的位置处。高浓度n型区域72具有比漂移区70中更高的n型杂质浓度。高浓度n型区域72布置在包括上表面12a的范围内。高浓度n型区域72通过漂移区70与降低表面电场区域60分隔开。
缓冲区74布置在漂移区70下方。缓冲区74是n型区，其具有比漂移区70中更高的n型杂质浓度。缓冲区74从元件范围24跨周边范围26分布。缓冲区74从下方与漂移区70接触。
集电极区76布置在包括半导体衬底12的下表面12b的范围内。集电极区76是具有较高p型杂质浓度的p型区域。集电极区76与下部电极16欧姆接触。集电极区76从IGBT范围20跨周边范围26分布。集电极区76从下方与缓冲区74接触。
在IGBT范围20内，IGBT由发射极区40、上体区42、势垒区44、下体区46、漂移区70、缓冲区74、集电极区76、栅电极34等形成。当IGBT工作时，上部电极14用作发射电极，并且下部电极16用作集电电极。当栅电极34的电势增加到不小于栅极阈值的值时，在上体区42和下体区46中产生沟道。在这种状态下，当下部电极16的电势变得高于上部电极14的电势时，电流从发射极区40经由上体区42的沟道、势垒区44、下体区46的沟道、漂移区70和缓冲区74流动到集电极区76。当栅电极34的电势降低到小于栅极阈值的值时，沟道消失，从而停止电子流动。以这种方式，IGBT根据栅电极34的电势执行切换。
如图3所示，在二极管范围22内，阴极区78设置在包括下表面12b的范围内。阴极区78是具有比缓冲区74中的n型杂质浓度高的n型杂质浓度的n型区。阴极区78与下部电极16欧姆接触。阴极区78从下方与缓冲区74接触。除了设置阴极区78代替集电极区76之外，二极管范围22的结构与IGBT范围20的结构相同。
在二极管范围22内，二极管由上体区42、势垒区44、下体区46，漂移区70、缓冲区74、阴极区78等形成。当二极管工作时，上部电极14用作阳极电极，并且下部电极16用作阴极电极。当上部电极14的电势增加到高于下部电极16的电势时，电流从上体区42经由势垒区44、下体区46、漂移区70和和缓冲区74流动到阴极区78。由于势垒区44内的n型杂质浓度低，所以电流流过势垒区44。当上部电极14的电势降低到低于下部电极16的电势时，电流停止。
接下来，将描述IGBT关断时的电势分布。当IGBT在下部电极16的电势高于上部电极14的电势的状态下关断时，反向电压被施加到下体区46与漂移区70之间的边界处的p-n结。因此，耗尽层从下体区46扩散到漂移区70。在这种状态下，耗尽层从深区50扩散到漂移区70。而且，耗尽层从降低表面电场区域60扩散到漂移区70。降低表面电场区域60促使耗尽层在位于降低表面电场区域60周向外侧的漂移区70中扩散。因此，漂移区70在宽范围内耗尽。
如图5中的虚线100所示，在IGBT关断的状态下，当等势线从漂移区70进入深区50时，在端栅极沟槽30a的下端附近发生电场集中。然而，在本实施例中，等电势线不太可能进入深区50。即，在本实施例中，p型杂质浓度在深区50的一部分中高，该部分位于外周侧。因此，如虚线102所示，等势线可能朝向外周侧延伸。因此，即使p型杂质浓度在深区50的一部分中较低，也不太可能发生如虚线100所示的等势线进入深区50，其中该部分位于内周侧。因此，在半导体装置10中，抑制了栅极沟槽30a的下端附近的电场集中。
接下来，将描述二极管的恢复操作。如上所述，通过将上部电极14的电势设定为高于下部电极16的电势，二极管导通。然后，空穴从下体区46流入漂移区70。结果，漂移区70的电阻由于电导率调制现象而降低，从而电子可以以较低的损耗通过漂移区70。此时，空穴基本上跨漂移区70分布。此后，当上部电极14的电势降低到低于下部电极16的电势时，二极管关断。当二极管关断时，分布在漂移区70中的空穴被释放到上部电极14。因此，在当二极管关断的时刻，反向电流(恢复电流)流过二极管。如上所述，在二极管导通的状态下，由于空穴基本上遍布漂移区70，所以空穴也存在于周边范围26内的漂移区70中。在二极管的恢复操作中，存在于周边范围26内的漂移区70中的一些空穴通过深区50被释放到上部电极14。此时，如图5中的箭头110所示的，空穴的流动(即，恢复电流)可能集中到深区50的部分，该部分位于更靠近上部电极14的内周侧。然而，在半导体装置10中，由于深区50的内周侧的部分中的p型杂质浓度较低，深区50的内周侧的该部分具有较高的电阻。因此，抑制了如箭头110所示的流经深区50的内周侧的部分的恢复电流。因此，抑制了恢复电流集中到深区50。
如上所述，根据本实施例的半导体装置10，可以在IGBT关断时抑制端栅极沟槽30a附近的电场集中，并且在二极管的恢复操作期间抑制恢复电流集中到深区50。
例如，可以以下面的方式形成p型杂质浓度在从内周侧朝向外周侧的方向上逐渐增加的深区50。首先，在要形成深区50的范围的上部中形成网状掩模。网状掩模是具有许多细小孔的掩模。这里，掩模形成为使得孔的比率在内周侧变小而在外周侧变高。接下来，通过掩模将p型杂质注入到半导体衬底中。因为孔的比率在外周侧上比在内周侧上大，所以注入p型杂质来使得p型杂质浓度在外周侧上比在内周侧上高。此后，对半导体衬底进行退火以使注入的p型杂质扩散并激活。借此，能够形成p型杂质浓度在从内周侧朝向外周侧的方向上逐渐增加的深区50。
在上述实施例中，深区50内的p型杂质浓度在从内周侧朝向外周侧的方向上连续地增加。然而，深区50内的p型杂质浓度可以在从内周侧朝向外周侧的方向上阶梯式地增加。在这种情况下，如图6中所示，深区50在从内周侧朝向外周侧的方向上阶梯式地变得更深。
在上述实施例中，降低表面电场区域60设置在深区50的外周侧上。然而，如图7中所示，代替降低表面电场区域60，可以在深区50的外周侧上设置一个或多个保护环62(所谓的FLR：场限制环)。保护环62是p型区。保护环62布置在包括上表面12a的范围内，并且与深区50分隔开。在图7中，示出了多个保护环62，并且每个保护环62彼此分隔开。当在从上方的平面图中观看半导体衬底12时，每个保护环62环形地延伸以围绕元件范围24。以这种方式，即使设置保护环62来代替降低表面电场区域60，也可以确保半导体装置10的耐压性。
在前述实施例中，二极管范围22内的上表面12a侧上的半导体结构(即，发射极区40、上体区42、势垒区44和下体区46)等于IGBT范围20内的上表面12a侧的半导体结构。然而，二极管范围22的上表面12a侧的半导体结构和IGBT范围20的上表面12a侧的半导体结构可以彼此不同。例如，在二极管范围22内，可以不存在发射极区40和势垒区44。
在上述实施例中，深区50设置在IGBT范围20与周边范围26之间的边界处。然而，如果二极管范围22和周边范围26经由栅极沟槽30彼此相邻，则深区50可以设置在二极管范围22与周边范围26之间的边界处。
在前述实施例中，体区通过势垒区44而分成上体区42和下体区46。然而，可以不存在势垒区44。
下面列出了本说明书公开的技术要素。以下每个技术要素都独立具有实用性。
在本说明书公开的一个实例的半导体装置中，所述深区可以包括：高浓度区域，其布置在包括半导体衬底的上表面的范围内；以及低浓度区域，其布置在所述高浓度区域下方，并且具有低于所述高浓度区域中的p型杂质浓度的p型杂质浓度。所述低浓度区域内的p型杂质浓度可以在从体区侧朝向耐压区侧的方向上增加。
在本说明书公开的一个实例的半导体装置中，所述低浓度区域内的p型杂质浓度的峰值可以高于所述耐压区内的p型杂质浓度的峰值。
以这种方式，通过将低浓度区域中的p型杂质浓度设置得高到一定程度，可以适当地抑制位于元件范围的外周端的沟槽附近的电场集中。
在本说明书公开的一个实例的半导体装置中，所述耐压区可以是与所述深区相邻的降低表面电场区域。
在本说明书公开的一个实例的半导体装置中，所述耐压区可以是一个或多个环形保护环，其通过所述漂移区与所述深区分隔开，并围绕所述元件范围的周边。
在本说明书公开的一个实例的半导体装置中，所述深区内的p型杂质浓度可以在从所述体区侧朝向所述耐压区侧的方向上连续地增加。
在本说明书公开的一个实例的半导体装置中，所述深区内的p型杂质浓度可以在从所述体区侧朝向所述耐压区侧的方向上阶梯式地增加。
尽管上面已经详细描述了实施例，但是这些实施例仅仅是说明性的，并且不限制权利要求的范围。在权利要求的范围内描述的技术还包括对上面例举的具体实例的各种改变和修改。在本说明书或附图中说明的技术要素独立地或通过各种组合来提供技术效用，并且不限于所提交的权利要求中描述的组合。此外，已经举例说明了本说明书或附图中示出的技术以同时满足多个目标，并且满足这些目标中的任何一个都给出了对技术的技术效用。

Claims (7)

1.一种半导体装置，其特征在于包括：
半导体衬底，其包括元件范围和设置在所述元件范围之外的周边范围，在所述元件范围中，多个栅极沟槽设置在所述半导体衬底的上表面上；
上部电极，其设置在所述半导体衬底的所述上表面上；
下部电极，其设置在所述半导体衬底的下表面上；以及
栅电极，所述栅电极中的每个布置在每个栅极沟槽内并且通过栅极绝缘膜与所述半导体衬底电绝缘，其中
所述半导体衬底包括：
n型发射极区，其布置在所述元件范围内，连接至所述上部电极，并且与所述栅极绝缘膜接触；
p型体区，其布置在所述元件范围内，并且在所述n型发射极区下方与所述栅极绝缘膜接触；
p型深区，其从所述元件范围跨所述周边范围布置，从所述上表面分布到比每个栅极沟槽的下端深的位置，并且包含所述多个栅极沟槽中的最靠近所述周边范围设置的端栅极沟槽；
p型耐压区，其布置在所述周边范围内，并且从所述上表面分布到比所述p型深区的下端浅的位置；
n型漂移区，其从所述元件范围跨所述周边范围布置，在所述p型体区下方与所述栅极绝缘膜接触，通过所述p型体区与所述n型发射极区分隔开，从下方与所述p型深区接触，并从下方与所述p型耐压区接触；
p型集电极区，其布置在所述n型漂移区下方，并与所述下部电极接触；以及
n型阴极区，其布置在所述n型漂移区下方，并与所述下部电极接触，并且
所述p型深区内的p型杂质浓度在从所述p型体区朝向所述p型耐压区的方向上增加。
2.根据权利要求1所述的半导体装置，其特征在于
所述p型深区包括：高浓度区域，其布置在包括所述上表面的范围内；以及低浓度区域，其布置在所述高浓度区域下方，并且具有低于所述高浓度区域中的p型杂质浓度的p型杂质浓度，并且
所述低浓度区域内的所述p型杂质浓度在从所述p型体区朝向所述p型耐压区的所述方向上增加。
3.根据权利要求2所述的半导体装置，其特征在于
所述低浓度区域内的所述p型杂质浓度的最大值高于所述p型耐压区内的p型杂质浓度的最大值。
4.根据权利要求1所述的半导体装置，其特征在于，所述p型耐压区是与所述p型深区相邻的降低表面电场区域。
5.根据权利要求1所述的半导体装置，其特征在于，所述p型耐压区是环形保护环，其通过所述n型漂移区与所述p型深区分隔开，并围绕所述元件范围的周边。
6.根据权利要求1至5中任一项所述的半导体装置，其特征在于，所述p型深区内的所述p型杂质浓度在从所述p型体区朝向所述p型耐压区的所述方向上连续地增加。
7.根据权利要求1至5中任一项所述的半导体装置，其特征在于，所述p型深区内的所述p型杂质浓度在从所述p型体区朝向所述p型耐压区的所述方向上阶梯式地增加。
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