CN1091948C - Mos器件及其制造方法 - Google Patents

Mos器件及其制造方法 Download PDF

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Publication number
CN1091948C
CN1091948C CN97111860A CN97111860A CN1091948C CN 1091948 C CN1091948 C CN 1091948C CN 97111860 A CN97111860 A CN 97111860A CN 97111860 A CN97111860 A CN 97111860A CN 1091948 C CN1091948 C CN 1091948C
Authority
CN
China
Prior art keywords
grid
insulating barrier
upper strata
lower floor
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN97111860A
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English (en)
Chinese (zh)
Other versions
CN1183637A (zh
Inventor
孙正焕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
LG Semicon Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Semicon Co Ltd filed Critical LG Semicon Co Ltd
Publication of CN1183637A publication Critical patent/CN1183637A/zh
Application granted granted Critical
Publication of CN1091948C publication Critical patent/CN1091948C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
CN97111860A 1996-11-27 1997-06-26 Mos器件及其制造方法 Expired - Fee Related CN1091948C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019960058079A KR100214523B1 (ko) 1996-11-27 1996-11-27 모스소자의 제조 방법
KR58079/96 1996-11-27

Publications (2)

Publication Number Publication Date
CN1183637A CN1183637A (zh) 1998-06-03
CN1091948C true CN1091948C (zh) 2002-10-02

Family

ID=19483813

Family Applications (1)

Application Number Title Priority Date Filing Date
CN97111860A Expired - Fee Related CN1091948C (zh) 1996-11-27 1997-06-26 Mos器件及其制造方法

Country Status (3)

Country Link
JP (1) JPH10189968A (ja)
KR (1) KR100214523B1 (ja)
CN (1) CN1091948C (ja)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100384870B1 (ko) * 1999-06-28 2003-05-22 주식회사 하이닉스반도체 반도체소자의 제조방법
KR20010045138A (ko) * 1999-11-03 2001-06-05 박종섭 반도체 장치 제조방법
KR20020019139A (ko) * 2000-09-05 2002-03-12 황인길 반도체 소자 및 그 제조 방법
CN103137694B (zh) * 2011-12-02 2016-01-20 上海华虹宏力半导体制造有限公司 一种表面沟道场效应晶体管及其制造方法
CN104103587B (zh) * 2013-04-03 2017-10-20 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN103811489B (zh) * 2014-03-05 2017-03-01 石以瑄 基于薄膜晶体管的微波毫米波集成电路、功率交换电路及其制作方法
CN110148564A (zh) * 2019-06-05 2019-08-20 长江存储科技有限责任公司 一种ddd uhv mos器件结构及其制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5182619A (en) * 1991-09-03 1993-01-26 Motorola, Inc. Semiconductor device having an MOS transistor with overlapped and elevated source and drain
US5585295A (en) * 1996-03-29 1996-12-17 Vanguard International Semiconductor Corporation Method for forming inverse-T gate lightly-doped drain (ITLDD) device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5182619A (en) * 1991-09-03 1993-01-26 Motorola, Inc. Semiconductor device having an MOS transistor with overlapped and elevated source and drain
US5585295A (en) * 1996-03-29 1996-12-17 Vanguard International Semiconductor Corporation Method for forming inverse-T gate lightly-doped drain (ITLDD) device

Also Published As

Publication number Publication date
JPH10189968A (ja) 1998-07-21
KR19980039122A (ko) 1998-08-17
KR100214523B1 (ko) 1999-08-02
CN1183637A (zh) 1998-06-03

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C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee