CN1091948C - Mos器件及其制造方法 - Google Patents
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Abstract
一种制造倒T栅MOS晶体管的方法,该方法包括下列步骤:提供第一导电类型为P型的硅衬底;在所述硅衬底上形成由二氧化硅或氮化硅构成的第一绝缘层;在所述第一绝缘层上形成多晶硅构成的半导体层;在所述半导体层上形成由W、Ti和Co中任一种材料构成的导体层;在所述导体层上形成由氧化物构成的第二绝缘层;选择地去除所述第二绝缘层和所述导体层,分别形成栅覆盖绝缘层和上层栅电极;在所述上层栅极的每一侧上形成第二导电类型为N型的轻掺杂杂质区;在所述半导体层上及所述栅覆盖绝缘层和上层栅极的每一侧上形成第一侧壁间隔层;在所述侧壁间隔层的每一侧上形成所述第二导电类型的重掺杂区;选择地去除所述半导体层,形成宽度比所述上层栅极大相当于两个所述第一侧壁间隔层的下层栅极,于是形成具有半导体下层栅极和导体上层栅极的倒T栅MOS晶体管。
Description
本发明的技术领域
本发明涉及一种半导体器件,特别涉及一种倒T栅MOS器件的制造方法,用于在栅区上完全堆叠LDD(轻掺杂漏)区,从而改善热载流子特性,并减少结漏电。
本发明的背景技术
按称作Single Ploy CMOS(单多晶CMOS)的常规技术,形成一对NMOS和PMOS晶体管,其栅极由n+多晶硅(poly-Si)制成。为了调节单多晶CMOS器件的阈值电压,要对硅衬底表面进行相反地掺杂。然而,相反地掺杂表面产生了埋沟道PMOS器件,该器件具有严重的短沟道效应。
称作Dual Poly CMOS(双多晶CMOS)的常规技术对单多晶CMOS做了改进,提供了带有n+多晶硅栅的NMOS器件和带有p+多晶硅栅的PMOS器件。这种技术产生了表面沟道PMOS器件,所以解决了埋沟道PMOS器件(具有短沟道效应)的问题。但不幸的是,形成p+多晶硅栅结构既复杂又困难。
称作Midgap Gate Electrodes(中间禁带栅极)的常规技术对双多晶CMOS做了改进,用如钨(W)等中间禁带金属栅结构代替p+多晶硅栅结构。该技术有以下几个优点,即,与用p+多晶硅形成栅相比用钨形成栅较简单和较容易。象p+多晶硅栅一样,钨栅解决了埋沟道PMOS器件的问题。而且,钨栅的栅电阻较低,可以提高器件的速度。
在常规MOS(金属氧化物半导体)器件中,注入到栅中的热电子会严重地损害器件的可靠性。人们已研究了减少这种热电子同时保持利用钨作栅材料的优点的常规技术,这种常规技术就是如图1所示的倒T栅MOS器件。
图1的常规倒T栅器件包括:形成于p型衬底11上的栅氧化膜12;形成于栅氧化膜12上的钨下层栅部件13;形成于钨下层栅部件13上的多晶硅上层栅部件14;形成于衬底11中的一对轻掺杂n-源/漏区15,它们借助多晶硅上层栅部件14对准;形成于多晶硅上层栅部件14每侧的第一侧壁间隔层16;形成于n-源/漏区15上的一对n+源/漏区17,它们借助氧化侧壁间隔层16对准;形成于栅氧化膜12上、及下层栅部件13和第一侧壁间隔层16两者各侧壁上的第二侧壁间隔层18;形成于n+源/漏区17和多晶硅上层栅部件14上的硅化物膜19;及多晶硅上层栅部件14上的栅覆盖绝缘层10。
同时,图1的源/漏区15和17构成轻掺杂漏(LDD)结构。这里,MOS器件结构的栅用作由多晶硅上层栅部件14和钨下层栅部件13构成的倒T栅。
下面说明常规倒T栅MOS器件的制造方法。
首先,在p型衬底11上形成栅氧化膜12,在栅氧化膜12上形成钨(W)层。在钨(W)层上形成n+多晶硅膜和绝缘层,并进行构图和腐蚀,从而分别形成了多晶硅上层栅部件14和栅覆盖绝缘层10。对衬底11进行离子注入,形成第一对n-源/漏区15。形成氧化膜,并构图和腐蚀,以形成第一侧间隔层16。然后,对n-源/漏区15进行n+源/漏离子注入,以形成第二对源/漏区17,然后腐蚀钨(W)层,形成钨下层栅部件13。
接着,在暴露的表面上形成氧化膜,并构图和腐蚀,以形成第二侧壁间隔层18。最后,在n+源/漏区17和上层栅部件14上形成硅化物层19。从而完成常规倒T栅MOS器件。
如上所述,常规倒T栅MOS器件有由钨(W)形成的下层栅部件13和形成于下层栅部件13上的多晶硅上层栅部件14。该倒T栅形成于栅氧化膜12上。因为钨下层栅部件13与栅氧化膜12的腐蚀选择率极低,所以已观察到下层钨(W)栅部件13被钻蚀。在形成下层栅部件时,对栅氧化膜12的腐蚀相当大。
本发明的内容
因此,本发明的目的是提供一种倒T栅MOS器件的制造方法,用于在栅区上完全堆叠LDD(轻掺杂漏)区,从而改善热载流子特性,进而防止由于热载流子引起的器件特性退化,减少结漏电,且不发生如现有技术中的较大量钻蚀。
为了实现本发明的上述目的,根据本发明的MOS器件制造方法包括以下步骤:一种制造倒T栅MOS晶体管的方法,该方法包括下列步骤:提供第一导电类型为P型的硅衬底;在所述硅衬底上形成由二氧化硅或氮化硅构成的第一绝缘层;在所述第一绝缘层上形成多晶硅构成的半导体层;在所述半导体层上形成由W、Ti和Co中任一种材料构成的导体层;在所述导体层上形成由氧化物构成的第二绝缘层;选择地去除所述第二绝缘层和所述导体层,分别形成栅覆盖绝缘层和上层栅电极;在所述上层栅极的每一侧上形成第二导电类型为N型的轻掺杂杂质区;在所述半导体层上及所述栅覆盖绝缘层和上层栅极的每一侧上形成第一侧壁间隔层;在所述侧壁间隔层的每一侧上形成所述第二导电类型的重掺杂区;选择地去除所述半导体层,形成宽度比所述上层栅极大相当于两个所述第一侧壁间隔层的下层栅极,于是形成具有半导体下层栅极和导体上层栅极的倒T栅MOS晶体管。
下面的详细说明可以使本发明的上述和其它目的更清楚。然而,应该明白,因为对于本领域的普通技术人员来说,以下的详细说明和具体实例使那些本发明精神和范围内的各种变化和改型变得更明显,所以,这些详细说明和具体实例只是说明性的,用于表示本发明的优选实施例。
附图的简要说明
通过以下的详细说明及参考附图可以更充分地理解本发明,这些说明和附图只是说明性的,并不能限制本发明,各附图中:
图1是常规倒TMOS晶体管的剖面图;及
图2A-2G依次是展示根据本发明的MOS器件制造方法的剖面图。
本发明的具体实施方式
下面结合例证性的图2A-2G说明根据本发明优选实施例的MOS器件制造方法。
首先,如图2A所示,在例如Si等p型半导体衬底20上生长厚约40-50埃的例如SiO2等氧化物膜(或代之以氮化物膜)22。在氧化膜22上淀积厚约500-2000埃的多晶硅层24。在多晶硅层24上淀积厚约500-2000埃的如W、Ti或Co等构成的金属层26。用n+型或p+杂质掺杂多晶硅层24。在金属层26上形成厚约500-2000埃的绝缘层,例如,二氧化硅等氧化物或如氮化硅等氮化物,厚度可以是1000埃。
如图2B所示,在绝缘层27上淀积光刻胶膜28。部件去除光刻胶膜28,即构图。然后用其余的光刻胶膜28作掩模腐蚀绝缘27金属层26,以形成金属上层栅部件13和栅覆盖绝缘层31。
参见图2C,去除光刻胶膜28。然后,在衬底20中注入n-型杂质,从而形成一对轻掺杂n-杂质区32,它们利用金属上层栅部件30自对准。这里,一对轻掺杂区32用作轻掺杂漏(LDD)区。
如图2D所示,通过淀积和腐蚀工艺,在多晶硅24上、及金属上层栅部件30和栅覆盖绝缘层31的每一侧形成第一侧壁间隔层34。在衬底20中注入n+型杂质,从而形成一对n+型重掺杂杂质区36,它们利用第一侧壁间隔层34自对准。这里,一对n+重掺杂杂质区36为n+型源/漏区。
参见图2E,选择地腐蚀位于n+型源/漏区36上的多晶硅层24和栅氧化层22,由多晶硅层24形成多晶硅下层栅部件40。第一侧壁间隔层34用作腐蚀多晶硅24的掩模,此后完成倒T栅。根据本发明的倒T栅包括金属上层栅部件30和多晶硅下层栅部件40。
图2F和2G示出了在上层金属栅部件30和源/漏区36上形成硅化物欧姆接触层的两步所选步骤。欧姆接触层分别减小金属线与上层金属栅部件30及源/漏区之间的电阻。
如图2F所示,在暴露的表面上淀积厚约500-2000埃的例如氧化膜或氮化膜。腐蚀该膜,在栅氧化膜22、多晶硅下层栅部件40和第一侧壁间隔层34的每一侧上形成第二侧壁间隔层42。
最后,如图2G所示,在n+源/漏区36的暴露表面上淀积例如W、Ti和Co等金属层。在约950-1050℃的温度下,对金属层进行快速热退火(RTA)工艺,从而在源/漏区36上形成硅化物层50。
在RTA工艺期间,掺入多晶硅下层栅部件40的n+(或p+)型杂质扩散进衬底20的LDD区32,从而获得轻掺杂杂质区32即LDD区完全堆叠于栅上的结构。这正是倒T栅晶体管的特征。
例示性的附图指示的是衬底和LDD区的导电类型分别为p型和n型。另外,衬底和杂质区的导电类型还可以分别是n型和p型。
如上所述,根据本发明的MOS器件制造方法通过在栅上完全堆叠LDD(轻掺杂漏区)区改善了热载流子特性。
另外,栅氧化膜的上表面上形成多晶硅层代替金属层,由此防止了栅氧化膜被钻蚀。由于多晶硅和栅氧化膜之间的选择率较大,所以这是可能的。
尽管上面说明了本发明,但显然可以按许多方式变化本发明。但不能认为这些变化脱离了本发明的精神和范围,对于本领域的普通人员来说,很显然这些改型皆落在以下的权利要求书的范围内。
Claims (11)
1.一种制造倒T栅MOS晶体管的方法,该方法包括下列步骤:
提供第一导电类型为P型的硅衬底;
在所述硅衬底上形成由二氧化硅或氮化硅构成的第一绝缘层;
在所述第一绝缘层上形成多晶硅构成的半导体层;
在所述半导体层上形成由W、Ti和Co中任一种材料构成的导体层;
在所述导体层上形成由氧化物构成的第二绝缘层;
选择地去除所述第二绝缘层和所述导体层,分别形成栅覆盖绝缘层和上层栅电极;
在所述上层栅极的每一侧上形成第二导电类型为N型的轻掺杂杂质区;
在所述半导体层上及所述栅覆盖绝缘层和上层栅极的每一侧上形成第一侧壁间隔层;
在所述侧壁间隔层的每一侧上形成所述第二导电类型的重掺杂区;
选择地去除所述半导体层,形成宽度比所述上层栅极大相当于两个所述第一侧壁间隔层的下层栅极,于是形成具有半导体下层栅极和导体上层栅极的倒T栅MOS晶体管。
2.根据权利要求1的方法,还包括以下步骤:
选择地去除所述第一绝缘层的暴露部分;
在所述硅衬底上、及所述第一绝缘层、所述下层栅极和所述第一侧壁间隔层的每一侧上形成第二侧壁间隔层;及
在所述第二侧壁间隔层每一侧上的所述硅衬底上形成欧姆接触层。
3.根据权利要求2的方法,其特征在于,所述欧姆接触层是硅化物。
4.根据权利要求1的方法,其特征在于,形成所述栅覆盖绝缘层的所述第二绝缘层是氧化物。
5.根据权利要求1的方法,其特征在于,所述氧化物是二氧化硅。
6.根据权利要求1的方法,其特征在于,形成所述轻掺杂杂质区的所述步骤包括离子注入。
7.根据权利要求1的方法,其特征在于,形成所述重掺杂区的所述步骤包括离子注入。
8.一种倒T栅MOS晶体管,该晶体管包括:
第一导电类型为P型的硅衬底;
由硅衬底的氧化物和氮化物中的一种形成的栅绝缘层;
多晶硅下层栅极;
由金属W、Ti和Co中的任一种形成的上层栅极,所述上层栅极的宽度窄于所述下层栅极,这样由所述上层和下层栅极一起组成倒T栅;
在所述上层栅极上的氧化物栅覆盖层;
在所述下层栅极之下的所述硅衬底中的第二导电类型为N型的轻掺杂杂质区,所述下层栅极的宽度宽于上层栅极;及
在下层栅极每一侧上的所述硅衬底中的所述第二导电类型重掺杂区。
9.根据权利要求8的晶体管,还包括:
在与所述下层栅极的每一侧间隔一定间距的所述硅衬底上的欧姆接触层。
10.根据权利要求9的晶体管,其特征在于,所述欧姆接触层是硅化物。
11.根据权利要求8的晶体管,其特征在于,所述氧化物是二氧化硅。
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KR1019960058079A KR100214523B1 (ko) | 1996-11-27 | 1996-11-27 | 모스소자의 제조 방법 |
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KR100384870B1 (ko) * | 1999-06-28 | 2003-05-22 | 주식회사 하이닉스반도체 | 반도체소자의 제조방법 |
KR20010045138A (ko) * | 1999-11-03 | 2001-06-05 | 박종섭 | 반도체 장치 제조방법 |
KR20020019139A (ko) * | 2000-09-05 | 2002-03-12 | 황인길 | 반도체 소자 및 그 제조 방법 |
CN103137694B (zh) * | 2011-12-02 | 2016-01-20 | 上海华虹宏力半导体制造有限公司 | 一种表面沟道场效应晶体管及其制造方法 |
CN104103587B (zh) * | 2013-04-03 | 2017-10-20 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
CN103811489B (zh) * | 2014-03-05 | 2017-03-01 | 石以瑄 | 基于薄膜晶体管的微波毫米波集成电路、功率交换电路及其制作方法 |
CN110148564A (zh) * | 2019-06-05 | 2019-08-20 | 长江存储科技有限责任公司 | 一种ddd uhv mos器件结构及其制造方法 |
Citations (2)
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US5182619A (en) * | 1991-09-03 | 1993-01-26 | Motorola, Inc. | Semiconductor device having an MOS transistor with overlapped and elevated source and drain |
US5585295A (en) * | 1996-03-29 | 1996-12-17 | Vanguard International Semiconductor Corporation | Method for forming inverse-T gate lightly-doped drain (ITLDD) device |
-
1996
- 1996-11-27 KR KR1019960058079A patent/KR100214523B1/ko not_active IP Right Cessation
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- 1997-06-26 CN CN97111860A patent/CN1091948C/zh not_active Expired - Fee Related
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US5182619A (en) * | 1991-09-03 | 1993-01-26 | Motorola, Inc. | Semiconductor device having an MOS transistor with overlapped and elevated source and drain |
US5585295A (en) * | 1996-03-29 | 1996-12-17 | Vanguard International Semiconductor Corporation | Method for forming inverse-T gate lightly-doped drain (ITLDD) device |
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KR19980039122A (ko) | 1998-08-17 |
KR100214523B1 (ko) | 1999-08-02 |
CN1183637A (zh) | 1998-06-03 |
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