CN108807505B - Silicon carbide MOSFET device and manufacturing method thereof - Google Patents

Silicon carbide MOSFET device and manufacturing method thereof Download PDF

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CN108807505B
CN108807505B CN201810991192.5A CN201810991192A CN108807505B CN 108807505 B CN108807505 B CN 108807505B CN 201810991192 A CN201810991192 A CN 201810991192A CN 108807505 B CN108807505 B CN 108807505B
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silicon carbide
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deep
metal
schottky contact
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CN108807505A (en
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张金平
邹华
赵阳
罗君轶
李泽宏
张波
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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Abstract

The invention provides a silicon carbide MOSFET device and a manufacturing method thereof.A discontinuous grid structure is formed on the basis of a common silicon carbide UMOSFET structure, two silicon carbide deep P injection regions are introduced between the two grid structures, and metal or polysilicon is introduced between the two silicon carbide deep P injection regions. The metal or the polycrystalline silicon is in direct contact with the silicon carbide N-epitaxy to form Schottky contact or heterojunction contact with rectification characteristics, the improvement has great optimization effect on basic characteristics of the traditional silicon carbide UMOSFET, integration of a multi-sub rectification device is realized, and the working performance of the third quadrant of the device is greatly optimized.

Description

Silicon carbide MOSFET device and manufacturing method thereof
Technical Field
The invention belongs to the power semiconductor technology, and particularly relates to a Metal Oxide Semiconductor Field Effect (MOSFET) device structure and a manufacturing method thereof.
Background
The development and efficient utilization of energy resources are the subject of constant human development. Since the 21 st century of human history, fossil energy has been the dominant source of energy for world energy production and consumption. Combined with the development and utilization of current energy resources, fossil energy remains the energy basis for human survival and development for a long period of time. The fossil energy will be exhausted and environmental pollution will be caused easily, so that the environmental and sustainable development problems caused by the exhaustion of the fossil energy are the problems that human beings must face. Electric energy is one of the main forms of energy available to human beings, and the improvement of the use efficiency of the electric energy is an important solution to the world energy problem. The electric power system is a necessary way for human beings to utilize electric energy and improve the use efficiency of the electric energy, and the electric power system reflects the modernization degree of the electric power system on the aspects of the transportation, management and use efficiency of the electric energy. Specifically, the power system mainly adjusts, measures, controls, protects, schedules, communicates, and the like, in the process of generating electric energy, and in the process, the power semiconductor device plays a central role. The performance of the power semiconductor device determines the performance of the power system. To a certain extent, the performance of the power semiconductor device is good and bad, and the energy conservation and emission reduction benefits are concerned.
The traditional power device is mainly a silicon-based power device, mainly comprises a thyristor, a power PIN device, a power bipolar junction device, a Schottky barrier diode, a power MOSFET and an insulated gate field effect transistor, is widely applied in a full power range, and occupies the market of the power semiconductor device by long-term and mature design technology and process technology. However, as researchers have studied the mechanism thoroughly, the performance of the silicon-based power device is close to the theoretical limit of the silicon material, and it is difficult to achieve a large improvement in performance by designing and optimizing the silicon-based power device.
Wide bandgap semiconductor materials represented by silicon carbide (SiC) and gallium nitride (GaN), also called next-generation semiconductor materials, are highly favored by power device designers for their excellent material characteristics. Silicon carbide material is a typical representative of the third generation semiconductor material, and is one of the most mature and widely applied wide bandgap semiconductor materials in the crystal growth technology and device manufacturing level at present. Compared with silicon materials, the silicon material has larger forbidden band width, higher thermal conductivity, higher electron saturation drift velocity and critical breakdown electric field which is 10 times that of the silicon materials, so that the silicon material becomes an ideal semiconductor material in the application occasions of high temperature, high frequency, high power and radiation resistance. Because the silicon carbide power device can obviously reduce the energy consumption of electronic equipment, the silicon carbide power device has the name of a green energy device which drives a new energy revolution.
Silicon carbide MOSFET devices are the next generation of semiconductor devices fabricated with the wide bandgap semiconductor material silicon carbide. By virtue of excellent material characteristics, the silicon-based IGBT device is considered to be a new generation semiconductor power device with the potential energy of replacing the traditional silicon-based IGBT device in the full-power application range. However, the on-state current density of silicon carbide MOSFETs is greatly limited by the low MOS channel mobility due to non-idealities in the MOS channel. Thus, silicon carbide UMOSFETs having higher channel densities, and thus greater on-state current densities, have received extensive attention and research. Although the silicon carbide trench MOSFET has lower on-resistance and a more compact cell layout, the problem of reliability is caused for long-term use of the silicon carbide trench MOSFET due to the problem of too high electric field of the bottom gate oxide layer. A conventional silicon carbide UMOSFET structure is shown in fig. 1.
Silicon carbide MOSFET devices are often required to be used in applications in anti-parallel with a diode. There are generally two ways to achieve this. One is to directly use the P-type base region of the device and silicon carbide N-A parasitic diode formed by a drift region and a silicon carbide N + substrate. The parasitic silicon carbide diode has large conduction voltage drop and poor reverse recovery characteristic, causes higher power loss and is not beneficial to the popularization in the power market; meanwhile, the low working efficiency caused by low working speed is very unfavorable for the silicon carbide MOSFET device in the practical circuit application; the other is by using the device in anti-parallel with an external diode. The method increases the number of metal interconnections, increases parasitic inductance, and is not beneficial to improving the reliability of the system; meanwhile, due to the increase of the number of devices, the volume of the system is increased, the matched heat dissipation requirement is also improved, and the packaging cost is also increased. The foregoing problems have prevented the spread of silicon carbide MOSFET devices in a wide variety of practical applications.
Disclosure of Invention
The invention aims to solve the problems, and provides a silicon carbide MOSFET device and a manufacturing method thereof, which can solve the problems of poor robustness, high power loss, low working efficiency, high production cost and the like caused by overhigh electric field of a gate dielectric layer in the application of the silicon carbide MOSFET device in an inverter circuit, a chopper circuit and the like. The invention is based on the silicon carbide UMOSFET structure (as shown in figure 1), by forming discontinuous gate structures, introducing two silicon carbide deep P injection regions between the two gate structures, and simultaneously depositing metal or polysilicon between the two silicon carbide deep P injection regions. The metal or polysilicon is in direct contact with the silicon carbide N-epitaxy to form a schottky contact or a heterojunction contact with rectifying characteristics. When the deposited material is metal, the barrier height of the formed contact can be adjusted by changing the metal material, process control and the N-epitaxial concentration of the silicon carbide, and finally a Schottky contact with lower on-state voltage drop (Von) is formed. Typically, the contact Von is in the range of 0.8V to 1.6V. Thereby realizing the in-vivo integration of the Schottky diode with the forward working performance superior to that of the parasitic diode. Because the diode is a multi-sub device, the diode has faster reverse recovery time, lower reverse recovery loss and higher reverse recovery reliability due to the fact that minority carrier storage does not exist in the reverse recovery process, and therefore the diode has better reverse recovery performance compared with a parasitic diode. Compared with a mode of anti-parallel connection of a diode in vitro, the improvement obviously reduces the volume of a power electronic system and reduces the packaging cost. Meanwhile, because the metal lead wire between the diode and the diode is not arranged, the parasitic effect caused by the metal lead wire is avoided, and the application reliability of the system is improved. Meanwhile, compared with a mode of integrating diodes in a plurality of in-vivo single blocks, the structure of the invention has more compact cellular area. The area of the unit cell after the diode is integrated is completely the same as that of the traditional silicon carbide double-groove MOSFET, and the basic performance of the MOSFET device is not influenced. Therefore, the structure of the invention has good performance advantages. If the deposited material is polysilicon, the contact formed is a Si/SiC heterojunction contact. Its characteristics are similar to schottky contacts: the device is also a multi-sub device and has rectification characteristic. The forward conduction voltage drop Von is generally considered to be 1.1V, which is superior to the parasitic diode characteristic of the silicon carbide MOSFET, and the forward conduction voltage drop Von also has excellent optimization function for optimizing the third quadrant working characteristic of the device. In addition, when the Schottky contact metal material or the polycrystalline silicon and the silicon carbide P + region below the grid structure play a role in protecting the Schottky contact metal material or the polycrystalline silicon, the grid dielectric electric field of the device is greatly reduced, the electric field distribution of the device is optimized, and the voltage withstanding level of the device is improved.
In order to achieve the purpose, the invention adopts the following technical scheme:
a silicon carbide MOSFET device is characterized in that a cell structure of the cell structure comprises a drain electrode metal 1, a silicon carbide N + substrate 2 and a silicon carbide N-epitaxial layer 3 which are sequentially arranged from bottom to top; a source groove is formed above the silicon carbide N-epitaxial layer 3, the source groove is filled by deposition of Schottky contact metal 12 or polycrystalline silicon 13, and the Schottky contact metal 12 or the polycrystalline silicon 13 is directly contacted with the silicon carbide N-epitaxial layer 3 to form Schottky contact or Si/SiC heterojunction contact with rectification characteristics; the Schottky contact metal 12 is embedded with a silicon carbide deep P doped region 4 at the left and right sides respectively, the two silicon carbide deep P doped regions 4 are deeper than the bottom of the Schottky contact metal 12, the left upper part of the silicon carbide deep P doped region 4 at the left side of the Schottky contact metal 12 and the right upper part of the silicon carbide deep P doped region 4 at the right side of the Schottky contact metal 12 are respectively provided with a first gate structure and a second gate structure, the right part of the first gate structure is embedded with the silicon carbide deep P doped region 4 at the left side, the left part of the second gate structure is embedded with the silicon carbide deep P doped region 4 at the right side, the depth of the gate structure is shallower than that of the Schottky contact metal 12, the gate structure comprises a gate dielectric layer 5, a polysilicon gate 6 and a gate electrode 10, the polysilicon gate 6 is surrounded by the gate dielectric layer 5 and is led out from the upper part of the gate electrode 10, the left side of the first gate structure is provided with a first mesa structure, the right side of the second grid structure is provided with a second mesa structure; the depth of the mesa structure is shallower than that of the gate structure; the mesa structures comprise a silicon carbide Pbase region 7, a silicon carbide P + contact region 14 and a silicon carbide N + source region 8, in the first mesa structure, the silicon carbide P + contact region 14 and the silicon carbide N + source region 8 are located on the surface of a semiconductor and above the silicon carbide Pbase region 7, and meanwhile the silicon carbide N + source region 8 and the silicon carbide Pbase region 7 are in close contact with the first gate structure on the right side; in the second mesa structure, the silicon carbide P + contact region 14 and the silicon carbide N + source region 8 are positioned on the semiconductor surface and above the silicon carbide Pbase region 7, and the silicon carbide N + source region 8 and the silicon carbide Pbase region 7 are in close contact with the second gate structure on the left side; the device surface is covered by a layer of source metal 9 which is spaced from the gate electrode 10 by borophosphosilicate glass BPSG 11.
Preferably, the device does not have a silicon carbide P + contact region 14, but rather has a silicon carbide deep P-doped region 4 above the left side of the silicon carbide N-epitaxial layer 3, to the left of the silicon carbide Pbase region 7 and the silicon carbide N + source region 8, the silicon carbide deep P-doped region 4 being of a depth corresponding to the depth of the silicon carbide deep P-doped region 4 adjacent the gate structure.
Preferably, the schottky contact metal 12 region is replaced by polysilicon 13; the polysilicon 13 and the schottky contact metal 12 have the same area size.
Preferably, a polysilicon 13 is provided between the two silicon carbide deep P-doped regions 4 directly under the schottky contact metal 12, and the polysilicon 13 is in contact with the silicon carbide N-epitaxial layer 3 and the schottky contact metal 12.
Preferably, the silicon carbide deep P-doped region 4 under the schottky contact metal 12 has discontinuous trenches in the Z direction, the depth of the trenches is equal to or less than the depth of the silicon carbide deep P-doped region 4, the trenches are filled with the schottky contact metal 12 or the polysilicon 13 by deposition, and the bottom of the trenches is the silicon carbide N-epitaxial layer 3.
Preferably, the silicon carbide deep P-doped regions 4 are distributed in a convex shape toward one side of the gate structure in the Z direction, and have a Split-gate structure in the recess of the silicon carbide deep P-doped region 4 and the bottom of the gate structure.
Preferably, the silicon carbide material is replaced by a semiconductor material of Si, Ge, GaAs, GaN, diamond, silicon germanium, gallium oxide.
Further, the silicon carbide MOSFET device is not limited to silicon carbide and silicon materials, and other wide and narrow bandgap materials can be used.
To achieve the above object, the present invention further provides a method for manufacturing a silicon carbide MOSFET device, comprising the steps of:
step 1: selecting a silicon carbide wafer as a silicon carbide N + substrate 2 and a silicon carbide N-epitaxial layer 3;
step 2: performing aluminum ion implantation through a high-energy ion implantation process to form a silicon carbide Pbase area 7, or forming the silicon carbide Pbase area 7 in an epitaxial mode;
and 3, step 3: performing phosphorus ion implantation by using a PSD mask through photoetching and ion implantation processes to form a silicon carbide P + contact region 14;
and 4, step 4: performing phosphorus ion implantation by using an NSD mask through photoetching and ion implantation processes to form a silicon carbide N + source region 8;
and 5, step 5: performing aluminum ion implantation through the processes of photoetching and high-energy ion implantation to form a silicon carbide deep P + doped region 4, or etching a groove with a specified size by using a groove mask through a groove etching process, and forming the silicon carbide deep P doped region 4 by adopting an epitaxy and etching process;
and 6, step 6: etching a groove with a specified size by using a groove mask through a groove etching process;
and 7, step 7: depositing a layer of metal at the bottom of the source groove by deposition and etching processes to form Schottky contact metal 12, and removing redundant metal by etching;
and 8, step 8: etching a gate groove with a specified size by using a groove mask through a groove etching process;
step 9: forming a gate dielectric layer 5 by a dry oxygen oxidation process;
step 10: depositing a layer of polycrystalline silicon in the gate trench by deposition and etching processes to form a polycrystalline silicon gate 6, and removing redundant polycrystalline silicon by etching;
and 11, step 11: forming a gate electrode 10 by deposition, photolithography and etching processes;
step 12: forming boron phosphorus silicon glass BPSG11 through deposition, photoetching and etching processes;
step 13: and forming a source metal 9 and a drain metal 1 through deposition, photoetching and etching processes respectively, and thus finishing the manufacturing of the device.
Further, in step 7, the deposited source trench schottky contact metal 12 may be replaced with polysilicon 13 material;
furthermore, the process part of the gate structure can be completed first, and then the processes of source trench etching, deposition and the like are performed;
further, step 3 may not be performed, and when the silicon carbide deep P doped region 4 is formed at step 5, the silicon carbide deep P doped region 4 is formed at the same time where the silicon carbide P + contact region 14 is formed at step 3;
further, after the trench etching of the step 6, secondary trench etching can be performed, the etching is continued in the center of the source trench, and before the schottky contact metal 12 is deposited in the step 7, the polysilicon 13 is deposited in the secondary trench through deposition and etching processes;
furthermore, after the source trench is formed in the 5 th step, etching may be added again to form a discontinuous trench in the designated area at the bottom of the source trench. The depth of the groove etched for the second time is equal to the depth of the silicon carbide deep P doped region 4;
furthermore, after the source trench is formed in the 5 th step, etching may be added again to form a discontinuous trench in the designated area at the bottom of the source trench. The depth of the groove for secondary etching is less than the depth of the silicon carbide deep P doping area 4;
further, in the step 5, the silicon carbide deep P-doped regions 4 are formed to be distributed in a convex shape in the Z direction towards one side of the gate structure by changing the mask parameters, and in the subsequent step of the gate trench, a deeper trench is formed by increasing the etching strength, and a Split-gate structure is formed at the bottom of the trench.
The following illustrates the principles of the invention:
silicon carbide MOSFET devices are required to be used in anti-parallel with a diode in a number of applications. Without considering monolithic integration in vivo, it is believed that there are two ways in which this can be achieved. One is a parasitic silicon carbide PiN diode formed by directly using a silicon carbide P-type base region of a silicon carbide MOSFET device, a silicon carbide N-epitaxial layer 3 and a silicon carbide N + substrate 2. The forward conduction voltage drop Von of the parasitic silicon carbide PiN is generally considered to be 3.1V, and the application of the parasitic silicon carbide PiN under low-voltage power is extremely unfavorable due to the extremely large forward conduction voltage drop, so that the on-state loss of the device is remarkably increased. Meanwhile, since the device belongs to a bipolar device, minority carriers are accumulated in an on state due to the conductance modulation effect. Although minority carrier accumulation can reduce the on-state voltage drop in the on state, for switching transients, especially off transients, the parasitic diode has very poor reverse recovery characteristics due to problems of increased off time, increased off loss, increased reverse peak current, and reduced off reliability caused by minority carrier storage. Therefore, for the anti-parallel diode, the basic requirements of low conduction voltage drop Von and fast recovery are required; the other is by using the device in anti-parallel with a diode external to the device. Although the method meets the basic requirements of low conduction voltage drop Von and quick recovery, the method causes the increase of production cost and the reduction of reliability after the increase of metal connecting wires due to the increase of the number of devices, the increase of a power system, the improvement of heat dissipation requirements and other factors, so that the selection of the external parallel diode is not optimal. This also motivates other implementations that implement the anti-parallel diode approach. The invention is based on the common silicon carbide UMOSFET structure (as shown in figure 1), by forming discontinuous gate structures, and introducing two silicon carbide deep P injection regions between the two gate structures, and simultaneously introducing metal or polysilicon between the two silicon carbide deep P injection regions. The metal or polysilicon is in direct contact with the silicon carbide N-epitaxy to form a schottky contact or a heterojunction contact with rectifying characteristics. The schottky contact is shown in fig. 2; the heterojunction contact is shown in figure 4. When the structure is in the blocking work of the MOSFET, the voltage-resistant part of the device is provided by the silicon carbide deep P doping area 4 and the silicon carbide N-epitaxial layer 3, the voltage-resistant level of the device is obviously improved by the improved structure of the device, the electric leakage of Schottky contact or heterojunction contact is greatly reduced due to the shielding effect of the silicon carbide P + area 4, and the electric field of the gate oxide layer of the device is reduced, so that the long-term application reliability of the device is improved. When the structure is in forward work of the MOSFET, the doping of the JFET area of the device can be made higher due to the improvement of the avalanche breakdown voltage resistance of the device and the protection of the gate dielectric layer by the silicon carbide P + area 4, so that the specific conductance value of the MOSFET is reduced, and the conduction performance of the device is optimized. The structure of the invention has great optimization effect on the third quadrant operation of the device. When the deposited material is schottky contact metal, the barrier height mentioned above can be adjusted by adjusting the metal species, process conditions, and N-epitaxy of silicon carbide to form schottky contacts with a Von of about 0.6V to 2V; meanwhile, due to the protection function of the silicon carbide deep P doped region 4, the Schottky contact interface has small electric leakage. Silicon carbide PiN diodes are generally considered to have a Von of around 3.1V. The embedding of the Schottky barrier diode greatly reduces the on-state loss of the device under the third quadrant work, and meanwhile, the Schottky barrier diode belongs to a multi-sub device, and has shorter reverse recovery time, lower turn-off loss, lower reverse recovery peak current and better reliability of the device in the reverse recovery process due to the fact that the minority carrier storage effect does not exist. When the deposited material is polysilicon, the polysilicon contacts the silicon carbide N-epitaxial layer 3 at the sidewall of the source trench bottom to form a Si/SiC heterojunction. The heterojunction is reported to have rectification characteristics in relevant documents. Its forward conduction voltage drop Von is about 1.1V. Also with respect to the parasitic diode, has a greatly improved effect on the third quadrant operation of the device. Meanwhile, the diode is also a multi-sub device, and has excellent reverse recovery performance similar to a Schottky diode; in order to improve the third quadrant operating characteristics of the device, the invention also provides a device structure, as shown in fig. 5. The bottom of the source trench and the space between the two silicon carbide deep P doped regions 4 are etched for the second time, and polysilicon deposition is carried out in the trench. While the source trenches are still deposited with schottky contact metal. The improvement increases the rectifying contact area by approximately 40% from the increase of the rectifying contact area, thereby increasing the conduction junction area in diode applications. On one hand, the forward conduction characteristic of the Si/SiC heterojunction is better than that of a Schottky diode according to the report of the literature, so the improvement is beneficial to increasing the third quadrant working current of the device; on the other hand, the leakage performance of the Si/SiC heterojunction is far better than that of a Schottky contact, and meanwhile, the P-type silicon has a good shielding effect on the Schottky junction surface, so that the leakage of the Schottky junction surface is further reduced. In order to further improve the working performance of the third quadrant of the device, the invention further provides two optimized structures. Namely, a discontinuous trench structure is formed inside the silicon carbide deep P-doped region 4 by continuously etching the bottom of the designated source trench. The trench structure is also filled with a schottky contact metal 12 or polysilicon 13 deposition. The depth of the secondary groove etching is equal to or less than the depth of the silicon carbide deep P doping area 4, so that the contact area of the Schottky/heterojunction is increased, and the purpose of optimizing the working performance of the third quadrant of the device is achieved; in order to optimize the dynamic characteristics of the device, the invention also provides a discontinuous Split-gate structure formed at the bottom of the gate structure, as shown in fig. 10 and fig. 11. The structure effectively reduces the area just opposite to the grid drain of the device, and reduces the number of grid charges necessary in the turn-on process of the device, thereby optimizing the switching characteristic of the device and improving the switching speed of the device.
In conclusion, the beneficial effects of the invention are as follows:
firstly, the invention realizes the in-vivo integration of a Schottky Barrier Diode (SBD) and a silicon/silicon carbide heterojunction, thereby optimizing the working performance of the third quadrant of the device to a great extent. The integrated Schottky Barrier Diode (SBD) and silicon/silicon carbide heterojunction have very low leakage;
compared with the traditional silicon carbide UMOSFET device, the structure has higher voltage resistance and lower specific conductance Ron.sp, and meanwhile, the reduction of the electric field of the gate dielectric is beneficial to the improvement of the long-term application reliability of the device;
compared with the mode of in-vitro anti-parallel connection of diodes, the structure of the invention reduces the interconnection quantity of metal leads and reduces the parasitic inductance of a system; the number of system components is reduced, and the system volume is reduced; the requirement on the volume of a heat dissipation system is reduced; and the packaging cost is reduced. In general, the structure improves the reliability of the device and reduces the application cost of the device;
fourthly, the invention also optimizes the working performance of the third quadrant of the device in a multi-level mode, and obtains better application performance of the MOSFET third quadrant circuit.
Fifthly, the structure is compatible with the production process of the traditional silicon carbide UMOSFET device, and has the process advantage of easy production;
sixthly, the dynamic characteristics of the device are optimized. The Miller capacitance of the device is reduced by reducing the area just opposite to the gate drain, so that the switching speed of the device is increased;
drawings
FIG. 1 is a schematic diagram of a conventional silicon carbide UMOSFET device cell structure;
FIG. 2 is a schematic diagram of a basic cell structure of a SiC MOSFET device provided in example 1;
FIG. 3 is a schematic diagram of a basic cell structure of a SiC MOSFET device provided in example 2;
FIG. 4 is a schematic diagram of a basic cell structure of a SiC MOSFET device provided in example 3;
FIG. 5 is a schematic diagram showing a basic cell structure of a SiC MOSFET device provided in example 4;
FIG. 6 is a Z-direction schematic view of the Region "Region A" of the structure of example 1;
FIG. 7 is a schematic diagram showing a basic cell structure of a silicon carbide MOSFET device provided in example 5;
FIG. 8 is a schematic diagram showing a basic cell structure of a silicon carbide MOSFET device provided in example 6;
FIG. 9 is a Z-direction schematic view of the Region "Region B" of the structure of example 1;
FIG. 10 is a schematic diagram showing a basic cell structure of a silicon carbide MOSFET device provided in example 7;
fig. 11 is a schematic diagram illustrating a basic cell structure of a silicon carbide MOSFET device according to example 7;
FIG. 12 is a schematic view of a silicon carbide substrate provided in example 8 of the present invention;
fig. 13 is a schematic diagram of a Pbase region formed by an ion implantation process according to embodiment 8 of the present invention;
fig. 14 is a schematic diagram of forming a silicon carbide P + contact region by performing aluminum ion implantation using a PSD mask through photolithography, ion implantation, and the like according to embodiment 8 of the present invention;
fig. 15 is a schematic diagram of forming a silicon carbide N + source region by performing a phosphorous ion implantation using an NSD mask through a photolithography process, an ion implantation process, and the like, according to embodiment 8 of the present invention;
fig. 16 is a schematic diagram of forming a silicon carbide deep P-doped region by photolithography and ion implantation processes according to embodiment 8 of the present invention;
fig. 17 is a schematic diagram of a source trench etched to a specified size by using a trench T mask through a trench etching process according to embodiment 8 of the present invention;
FIG. 18 is a schematic diagram of a Schottky contact metal formed by depositing a layer of metal on the bottom of the source trench by a deposition and etching process in accordance with embodiment 8 of the present invention;
fig. 19 is a schematic diagram of a trench gate etched to a specified size by using a trench mask through a trench etching process according to embodiment 8 of the present invention;
fig. 20 is a schematic diagram of a gate dielectric layer formed by a dry oxygen oxidation process as provided in embodiment 8 of the present invention;
fig. 21 is a schematic diagram of forming a polysilicon gate by deposition, photolithography and etching processes according to embodiment 8 of the present invention;
fig. 22 is a schematic diagram of a gate electrode formed by deposition, photolithography and etching processes according to embodiment 8 of the present invention;
FIG. 23 is a schematic diagram of forming BPSG by deposition, photolithography and etching processes according to embodiment 8 of the present invention;
fig. 24 is a schematic diagram of forming a drain metal and a drain metal by deposition, photolithography and etching processes according to embodiment 8 of the present invention.
The structure comprises a substrate, a silicon carbide N + substrate, a silicon carbide N-epitaxial layer, a silicon carbide deep P doped region, a gate dielectric layer, a polysilicon gate, a silicon carbide Pbase region, a silicon carbide N + source region, a source metal, a gate electrode, a boron-phosphorus-silicon glass BPSG, a Schottky contact metal, a polycrystalline silicon and a silicon carbide P + contact region, wherein the substrate is 1, the substrate is 2, the epitaxial layer is 3, the deep P doped region is 4, the gate dielectric layer is 5, the polycrystalline silicon gate is 6, the Pbase region is 7, the source region is 8, the source metal is; 15 is Split-gate polysilicon.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings, which illustrate a 1200V silicon carbide MOSFET device, and further illustrate the principles and features of the present invention. The examples are given solely for the purpose of illustration and are not intended to limit the scope of the invention.
Example 1:
carbonizationA silicon MOSFET device, as shown in fig. 2, the cell structure includes a drain metal 1, a silicon carbide N + substrate 2, and a silicon carbide N-epitaxial layer 3, which are sequentially disposed from bottom to top; a source groove is formed above the silicon carbide N-epitaxial layer 3, the source groove is filled by deposition of Schottky contact metal 12 or polycrystalline silicon 13, and the Schottky contact metal 12 or the polycrystalline silicon 13 is directly contacted with the silicon carbide N-epitaxial layer 3 to form Schottky contact or Si/SiC heterojunction contact with rectification characteristics; the Schottky contact metal 12 is embedded with a silicon carbide deep P doped region 4 at the left and right sides respectively, the two silicon carbide deep P doped regions 4 are deeper than the bottom of the Schottky contact metal 12, the left upper part of the silicon carbide deep P doped region 4 at the left side of the Schottky contact metal 12 and the right upper part of the silicon carbide deep P doped region 4 at the right side of the Schottky contact metal 12 are respectively provided with a first gate structure and a second gate structure, the right part of the first gate structure is embedded with the silicon carbide deep P doped region 4 at the left side, the left part of the second gate structure is embedded with the silicon carbide deep P doped region 4 at the right side, the depth of the gate structure is shallower than that of the Schottky contact metal 12, the gate structure comprises a gate dielectric layer 5, a polysilicon gate 6 and a gate electrode 10, the polysilicon gate 6 is surrounded by the gate dielectric layer 5 and is led out from the upper part of the gate electrode 10, the left side of the first gate structure is provided with a first mesa structure, the right side of the second grid structure is provided with a second mesa structure; the depth of the mesa structure is shallower than that of the gate structure; the mesa structures comprise a silicon carbide Pbase region 7, a silicon carbide P + contact region 14 and a silicon carbide N + source region 8, in the first mesa structure, the silicon carbide P + contact region 14 and the silicon carbide N + source region 8 are located on the surface of a semiconductor and above the silicon carbide Pbase region 7, and meanwhile the silicon carbide N + source region 8 and the silicon carbide Pbase region 7 are in close contact with the first gate structure on the right side; in the second mesa structure, the silicon carbide P + contact region 14 and the silicon carbide N + source region 8 are positioned on the semiconductor surface and above the silicon carbide Pbase region 7, and the silicon carbide N + source region 8 and the silicon carbide Pbase region 7 are in close contact with the second gate structure on the left side; the device surface is covered by a layer of source metal 9 which is spaced from the gate electrode 10 by borophosphosilicate glass BPSG 11. Wherein the drain metal 1 has a thickness of 0.5-2 μm and a width of 2-8 μm, and the gate metal 10 has a thickness of 0.5-2 μm and a width of 0.2-0.5Mum, the thickness of the source metal 9 is 4μm-6μm, and the width is 2-8μm; the silicon carbide N + substrate 2 has a thickness of 1 to 3 μm and a concentration of 1e18 to 1e19cm-3(ii) a The silicon carbide N-epitaxial layer 3 has a thickness of 6 to 10 μm and a concentration of 1e15 to 1e16cm-3(ii) a The silicon carbide deep P doped region 4 has a thickness of 1-3 μm, a width of 0.5-2 μm, and a concentration of 1e 17-6 e17cm-3(ii) a The silicon carbide Pbase region 7 has a thickness of 0.3 to 0.8 μm, a width of 0.5 to 1.1 μm, and a concentration of 6e16 to 4e17cm-3(ii) a The silicon carbide N + source region 8 has a thickness of 0.2 to 0.4 μm, a width of 0.2 to 0.3 μm, and a concentration of 2e18 to 1e19cm-3(ii) a The silicon carbide P + contact region 14 has a thickness of 0.2 to 0.4 μm, a width of 0.2 to 0.3 μm, and a concentration of 1e18 to 1e19cm-3(ii) a The thickness of the gate dielectric layer 5 is 20-80 nm; the thickness of the polysilicon gate 6 is 0.4-1 μm, and the width is 0.4-1 μm. The thickness of the Schottky contact metal 12 is 1-2 μm, and the width is 0.4-1.5 μm. According to the silicon carbide MOSFET provided by the invention, the Schottky contact or the heterojunction contact is integrated in the body, so that the basic performance of the device is optimized, the working performance of the third quadrant of the device is optimized, and the application cost of a power system is reduced.
Example 2:
as shown in fig. 3, the needle of the present embodiment is substantially the same as that of embodiment 1 except that: the structure does not have a silicon carbide P + contact region 14, but has a silicon carbide deep P doped region 4 above the left side of the silicon carbide N-epitaxial layer 3, on the left side of the silicon carbide Pbase region 7 and the silicon carbide N + source region 8, the silicon carbide deep P doped region 4 being of the same depth as the silicon carbide deep P doped region 4 near the gate structure. The improvement is beneficial to strengthening the protection of the silicon carbide deep P doped region 4 to the semiconductor surface structure, so that the long-term application reliability of the device is improved.
Example 3:
the structure of the present embodiment is substantially the same as that of embodiment 1, except that: the schottky contact metal 12 area used is replaced by polysilicon 13 as shown in fig. 4. And a Si/SiC heterojunction structure with rectifying contact is formed between the sidewall of the bottom of the source trench and the silicon carbide N-epitaxial layer 3. The forward conduction voltage drop Von of the heterojunction structure is about 1.1V, and the heterojunction structure also has good lifting effect on the third quadrant operation of the device. Meanwhile, the heterojunction belongs to a multi-sub device, so that the diode has good reverse recovery performance.
Example 4:
as shown in fig. 5, this embodiment is different from embodiment 1 in that a polysilicon 13 region is located between two silicon carbide deep P-doped regions 4 directly under the schottky contact metal 12. The polysilicon 13 is in contact with the silicon carbide N-epitaxial layer 3 and the schottky contact metal 12. The introduction of the polysilicon 13 increases the working area of the third quadrant of the device, reduces the electric leakage of the device in an off state, and has a good optimization effect on the electrical performance of the third quadrant of the device.
Example 5:
the present embodiment is different from embodiment 1 in that: as shown in Region a in fig. 7, the silicon carbide deep P-doped Region 4 under the schottky contact metal 12 has discontinuous trenches in the Z-direction, the depth of the trenches is equal to the depth of the silicon carbide deep P-doped Region 4, the trenches are filled with the schottky contact metal 12 or the polysilicon 13 by deposition, and the bottom of the trenches is the silicon carbide N-epitaxial layer 3. Example 1 the source trench under structure is shown as Region a in fig. 6. This example optimizes the on-state current density for the third quadrant operation of the device relative to example 1.
Example 6:
the structure of the present embodiment is substantially the same as that of embodiment 5, except that: the depth of the trench is less than the depth of the silicon carbide deep P-doped Region 4, as shown by Region a in fig. 8. Compared with embodiment 5, this embodiment has lower leakage in the off state, so that the embedded diode has better reliability.
Example 7:
the structure of this embodiment is substantially the same as that of embodiment 1, except that the silicon carbide deep P + doped regions 4 are distributed in a zigzag shape toward one side of the gate structure in the Z direction, and have Split-gate structures in the recesses of the silicon carbide deep P + doped regions 4 and the bottom of the gate structure, as shown in the Region of Region B in fig. 10. The Reigon B region in the structure of example 1 is shown in fig. 9. The mode effectively reduces the area just opposite to the grid drain of the device, and reduces the number of grid charges necessary in the turn-on process of the device, thereby optimizing the switching characteristic of the device and improving the switching speed of the device.
Example 8:
in this embodiment, a method for manufacturing a 1200V silicon carbide MOSFET device is also taken as an example to describe the specific implementation manner of the above embodiments 1 to 7, and devices with different performance parameters can be prepared according to actual requirements according to common general knowledge in the art.
Step 1: a silicon carbide wafer with appropriate resistivity and thickness is selected as the following silicon carbide N + substrate 2 and silicon carbide N-region 3, as shown in fig. 12. Wherein the thickness of the silicon carbide N + substrate 2 is 1-3 μm, and the concentration is 1e 18-1 e19 cm-3; the silicon carbide N-epitaxial layer 3 has a thickness of 6 to 10 μm and a concentration of 1e15 to 1e16cm-3；
Step 2: and (3) performing aluminum ion implantation by a high-energy ion implantation process with the implantation energy of about 1500-1900 keV to form a silicon carbide Pbase region 7. The step can also be carried out by epitaxial method to form a film with a thickness of 0.3-0.8 μm, a width of 0.5-1.1 μm, and a concentration of 6e 16-4 e17cm-3A silicon carbide Pbase region 7. The device after formation of the silicon carbide Pbase region 7 is shown in fig. 13;
and 3, step 3: through the procedures of photoetching, ion implantation and the like, aluminum ion implantation is carried out by utilizing a PSD mask, and the implantation energy is about 1300-1800 keV. A thickness of 0.2 to 0.4 μm, a width of 0.2 to 0.3 μm, and a concentration of 1e18 to 1e19cm-3Forming a silicon carbide P + contact region 14, as shown in fig. 14;
and 4, step 4: through the processes of photoetching, ion implantation and the like, phosphorus ion implantation is carried out by using an NSD mask, and the implantation energy is about 1300-1700 keV. A thickness of 0.2 to 0.4 μm, a width of 0.2 to 0.3 μm, and a concentration of 2e18 to 1e19cm-3To form a silicon carbide N + source region 8, as shown in fig. 15;
and 5, step 5: performing aluminum ion implantation by photolithography, ion implantation with an implantation energy of 1700-2000 keV, a thickness of 1-3 μm, a width of 0.5-2 μm, and a concentration of 1e 17-6 e17cm-3Silicon carbide deep P doped region 4. As shown in fig. 16. The process can also form the silicon carbide deep P + doped region 4 by etching and epitaxial processes;
and 6, step 6: etching a source groove with the thickness of 1-2 mu m and the width of 0.4-1.5 mu m by using a groove mask through a groove etching process, as shown in FIG. 17;
and 7, step 7: a layer of metal is deposited at the bottom of the source groove through deposition and etching processes to form Schottky contact metal 12 with the thickness of 1-2 mu m and the width of 0.4-1.5 mu m, and redundant metal is removed through etching. As shown in fig. 18;
and 8, step 8: etching a gate groove with the thickness of 0.4-1 μm and the width of 0.4-1 μm by using a groove mask through a groove etching process, as shown in FIG. 19;
step 9: forming a gate dielectric layer 5 with a thickness of 20-80 nm by a dry oxygen oxidation process at a temperature of about 1000-1400 ℃, as shown in fig. 20;
step 10: through deposition and etching processes, a layer of polycrystalline silicon is deposited in the gate trench to form a polycrystalline silicon gate 6 with the thickness of 0.4-1 mu m and the width of 0.4-1 mu m, and redundant polycrystalline silicon is removed through etching. As shown in fig. 21;
and 11, step 11: the gate electrode 10 having a thickness of 0.5 to 2 μm and a width of 0.2 to 0.4 μm is formed by deposition, photolithography and etching processes, as shown in fig. 22.
Step 12: the borophosphosilicate glass BPSG11 is formed by deposition, photolithography, and etching processes as shown in fig. 23.
Step 13: respectively forming source electrode metal 9 with the thickness of 4-6 mu m and the width of 2-8 mu m and drain electrode metal 1 with the thickness of 0.5-2 mu m and the width of 2-8 mu m by deposition, photoetching and etching processes. At this point, the device fabrication is complete, as shown in fig. 24.
Further, the polysilicon 13 deposited in the step 10 may be either N-type polysilicon or P-type polysilicon;
further, step 3 may not be performed, and when the silicon carbide deep P doped region 4 is formed in step 5, the silicon carbide deep P doped region 4 is formed at the position where the silicon carbide P + contact region 14 is formed in step 3 at the same time, so as to facilitate the protection of the silicon carbide deep P doped region 4 for the semiconductor surface functional region;
further, in step 7, the deposited source trench schottky contact metal 12 may also be replaced by polysilicon 13 material; the polysilicon can be N-type polysilicon or P-type polysilicon;
further, after the trench etching of the step 6, secondary trench etching can be carried out, the etching is continued in the center of the source trench, and before the schottky contact metal 12 is deposited in the step 7, the polycrystalline silicon 13 is deposited in the secondary trench through deposition and etching processes, so that the rectifying contact area is enlarged, and the application performance of the diode is optimized;
furthermore, after the source trench is formed in the 6 th step, etching may be added again to form a discontinuous trench in the designated area at the bottom of the source trench. The depth of the groove for the secondary etching is equal to the depth of the silicon carbide deep P doped region 4 formed in the later period, namely the thickness is 1-2 mu m;
furthermore, after the source trench is formed in the 5 th step, etching may be added again to form a discontinuous trench in the designated area at the bottom of the source trench. The depth of the groove of the secondary etching is smaller than the depth of the silicon carbide deep P doping area 4 formed in the later period, namely the thickness is smaller than 1um at minimum and smaller than 2um at maximum;
furthermore, the process part of the gate structure can be completed first, and then the processes of source trench etching, deposition and the like are performed;
further, in the step 5, by changing the mask parameters, the silicon carbide deep P doped regions 4 are formed to be distributed in a convex shape in the Z direction and back to another silicon carbide deep P doped region 4, and in the subsequent step of the gate trench, a deeper trench is formed by increasing the etching force, and a Split-gate structure is formed at the bottom of the trench.
It should also be claimed that: as known to those skilled in the art based on the basic knowledge in the art, in the structure of the silicon carbide power MOSFET of the present invention, the P-type polysilicon may also be implemented by N-type polysilicon, P-type single crystal silicon, or N-type single crystal silicon; the dielectric material used can be silicon dioxide (SiO)2) This can also be achieved by using silicon nitride (Si)3N4) Hafnium oxide (HfO)2) Aluminum oxide (Al)2O3) The realization of medium materials with equal height K; the silicon carbide material may also be gallium nitride,diamond and other wide bandgap materials. Meanwhile, the specific implementation mode of the manufacturing process can be adjusted according to actual needs.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (8)

1. A silicon carbide MOSFET device, characterized by: the cell structure comprises a drain electrode metal (1), a silicon carbide N + substrate (2) and a silicon carbide N-epitaxial layer (3) which are arranged from bottom to top in sequence; a source groove is formed above the silicon carbide N-epitaxial layer (3), the source groove is deposited and filled by a Schottky contact metal (12), and the Schottky contact metal (12) is directly contacted with the silicon carbide N-epitaxial layer (3) to form a Schottky contact with rectification characteristic; the Schottky contact metal (12) is embedded with a silicon carbide deep P doped region (4) at the left side and the right side respectively, the silicon carbide deep P doped region (4) is deep at the bottom of the Schottky contact metal (12), a first grid structure and a second grid structure are respectively arranged at the left upper part of the silicon carbide deep P doped region (4) at the left side of the Schottky contact metal (12) and the right upper part of the silicon carbide deep P doped region (4) at the right side of the Schottky contact metal (12), the partial region at the right side of the first grid structure is embedded into the silicon carbide deep P doped region (4) at the left side, the partial region at the left side of the second grid structure is embedded into the silicon carbide deep P doped region (4) at the right side, the depth of the grid structure is shallower than the Schottky contact metal (12), the grid structure comprises a grid dielectric layer (5), a polysilicon grid (6) and a grid electrode (10), and the polysilicon grid (6) is surrounded by the grid dielectric layer, the upper part of the grid electrode is led out through a grid electrode (10), the left side of the first grid electrode structure is provided with a first mesa structure, and the right side of the second grid electrode structure is provided with a second mesa structure; the depth of the mesa structure is shallower than that of the gate structure; the mesa structures comprise silicon carbide P-type base regions (7), silicon carbide P + contact regions (14) and silicon carbide N + source regions (8), in the first mesa structure, the silicon carbide P + contact regions (14) and the silicon carbide N + source regions (8) are located on the surface of a semiconductor and above the silicon carbide P-type base regions (7), and meanwhile the silicon carbide N + source regions (8) and the silicon carbide P-type base regions (7) are in close contact with a first grid structure on the right side; in the second mesa structure, the silicon carbide P + contact region (14) and the silicon carbide N + source region (8) are positioned on the semiconductor surface and above the silicon carbide P-type base region (7), and the silicon carbide N + source region (8) and the silicon carbide P-type base region (7) are in close contact with the second gate structure on the left side; the device surface is covered by a layer of source metal (9) which is separated from the gate electrode (10) by borophosphosilicate glass (BPSG) (11).
2. A silicon carbide MOSFET device as claimed in claim 1 wherein: the device is not provided with a silicon carbide P + contact region (14), and a silicon carbide deep P doping region (4) is arranged at the left upper part of the silicon carbide N-epitaxial layer (3), the left side of the silicon carbide P type base region (7) and the left side of the silicon carbide N + source region (8), and the depth of the silicon carbide deep P doping region (4) is consistent with that of the silicon carbide deep P doping region (4) near the grid structure.
3. A silicon carbide MOSFET device as claimed in claim 1 wherein: the Schottky contact metal (12) region is replaced by polysilicon (13); the polycrystalline silicon (13) and the Schottky contact metal (12) are same in area size.
4. A silicon carbide MOSFET device as claimed in any one of claims 1 to 2 in which: and polycrystalline silicon (13) is arranged under the Schottky contact metal (12) and between the two silicon carbide deep P doped regions (4), and the polycrystalline silicon (13) is in contact with the silicon carbide N-epitaxial layer (3) and the Schottky contact metal (12).
5. A silicon carbide MOSFET device as claimed in any one of claims 1 to 2 in which: the silicon carbide deep P doped region (4) below the Schottky contact metal (12) is provided with discontinuous grooves in the Z direction, the depth of the grooves is equal to or less than that of the silicon carbide deep P doped region (4), the Schottky contact metal (12) or polycrystalline silicon (13) is deposited and filled in the grooves, and the bottom of each groove is provided with a silicon carbide N-epitaxial layer (3).
6. A silicon carbide MOSFET device as claimed in any one of claims 1 to 3 in which: the silicon carbide deep P doped region (4) is distributed in a convex shape towards one side of the grid structure in the Z direction, and a Split-gate structure is arranged in the concave part of the silicon carbide deep P doped region (4) and the bottom of the grid structure.
7. A silicon carbide MOSFET device as claimed in claim 1 wherein: the silicon carbide material is replaced by a semiconductor material of Si, Ge, GaAs, GaN, diamond, silicon germanium, gallium oxide.
8. A method of fabricating a silicon carbide MOSFET device, comprising the steps of:
step 1: selecting a silicon carbide wafer as a silicon carbide N + substrate (2) and a silicon carbide N-epitaxial layer (3) at the back;
step 2: performing aluminum ion implantation through a high-energy ion implantation process to form a silicon carbide P-type base region (7), or forming the silicon carbide P-type base region (7) in an epitaxial mode;
and 3, step 3: performing phosphorus ion implantation by using a PSD mask through photoetching and ion implantation processes to form a silicon carbide P + contact region (14);
and 4, step 4: performing phosphorus ion implantation by using an NSD mask through photoetching and ion implantation processes to form a silicon carbide N + source region (8);
and 5, step 5: performing aluminum ion implantation through the procedures of photoetching and high-energy ion implantation to form a silicon carbide deep P doped region (4), or etching a groove with a specified size by using a groove mask through a groove etching process, and forming the silicon carbide deep P doped region (4) by adopting an epitaxy and etching process;
and 6, step 6: etching a groove with a specified size by using a groove mask through a groove etching process;
and 7, step 7: depositing a layer of metal at the bottom of the source groove by deposition and etching processes to form Schottky contact metal (12), and removing redundant metal by etching;
and 8, step 8: etching a gate groove with a specified size by using a groove mask through a groove etching process;
step 9: forming a gate dielectric layer (5) by a dry oxygen oxidation process;
step 10: depositing a layer of polysilicon in the gate trench by deposition and etching processes to form a polysilicon gate (6), and removing redundant polysilicon by etching;
and 11, step 11: forming a gate electrode (10) by deposition, photolithography and etching processes;
step 12: forming BPSG (11) through deposition, photoetching and etching processes;
step 13: and forming a source metal (9) and a drain metal (1) through deposition, photoetching and etching processes respectively, and thus finishing the manufacturing of the device.
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CN111354794B (en) * 2018-12-24 2021-11-05 东南大学 Power semiconductor device and method for manufacturing the same
CN111370476B (en) * 2018-12-25 2022-03-29 上海睿驱微电子科技有限公司 IEGT with hole current carrying path and method of construction thereof
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105047539A (en) * 2015-08-07 2015-11-11 西安电子科技大学 Method for improving channel mobility of SiC metal-oxide-semiconductor field-effect transistor (MOSFET)
CN106876485A (en) * 2017-03-06 2017-06-20 北京世纪金光半导体有限公司 Double trench MOSFET devices of a kind of SiC of integrated schottky diode and preparation method thereof
CN107256864A (en) * 2017-06-09 2017-10-17 电子科技大学 A kind of carborundum TrenchMOS devices and preparation method thereof
CN108183131A (en) * 2017-12-05 2018-06-19 中国电子科技集团公司第五十五研究所 A kind of unilateral MOS type device preparation method of integrated SBD structures

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105047539A (en) * 2015-08-07 2015-11-11 西安电子科技大学 Method for improving channel mobility of SiC metal-oxide-semiconductor field-effect transistor (MOSFET)
CN106876485A (en) * 2017-03-06 2017-06-20 北京世纪金光半导体有限公司 Double trench MOSFET devices of a kind of SiC of integrated schottky diode and preparation method thereof
CN107256864A (en) * 2017-06-09 2017-10-17 电子科技大学 A kind of carborundum TrenchMOS devices and preparation method thereof
CN108183131A (en) * 2017-12-05 2018-06-19 中国电子科技集团公司第五十五研究所 A kind of unilateral MOS type device preparation method of integrated SBD structures

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Assignor: University of Electronic Science and Technology of China

Contract record no.: X2023980042422

Denomination of invention: A silicon carbide MOSFET device and its manufacturing method

Granted publication date: 20210108

License type: Common License

Record date: 20230928