CN108735823B - Diode and manufacturing method thereof - Google Patents
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- CN108735823B CN108735823B CN201810571838.4A CN201810571838A CN108735823B CN 108735823 B CN108735823 B CN 108735823B CN 201810571838 A CN201810571838 A CN 201810571838A CN 108735823 B CN108735823 B CN 108735823B
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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Abstract
A diode device and a manufacturing method thereof belong to the technical field of power semiconductor devices. The cell structure of the device comprises a metal cathode, an N + substrate and an N-epitaxial layer, wherein two sides of the top layer of the N-epitaxial layer are provided with groove structures, and each groove structure comprises a P-type semiconductor region and a hetero-semiconductor from bottom to top; the top layer of the N-epitaxial layer is also provided with a P-type body region, an N + source region and a P + contact region; the N + source region, the P-type body region and part of the N-epitaxial layer are in contact with the hetero-semiconductor through the dielectric layer on the side wall of the groove, and the surface of the device is covered with a metal anode. The hetero-semiconductor, the dielectric layer, the source region, the body region and the epitaxial layer form a super barrier structure. The invention can solve the problems of large forward starting voltage, poor reverse recovery capability and the like of the existing PIN diode device; and on the premise of not influencing voltage resistance, the leakage is lower, the safe working area is larger, and the reliability of the device is improved.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a diode and a manufacturing method thereof.
Background
According to statistics, more than 90% of electricity consumption in the world is controlled by a power device. The power device and the module thereof provide an efficient way for realizing the conversion of various electric energy forms, and are widely applied to the fields of national defense construction, transportation, industrial production, medical treatment and health care and the like. Since the first power device application in the 50 s of the last century, energy sources were more efficiently converted and used with each generation of power devices. The history of the power semiconductor device, namely the power semiconductor device shows a new history.
Power diodes are the simplest electronic components among many power semiconductor devices, but are also one of the most widely used devices, and play a very critical role in the circuit. Therefore, the performance of the power diode is often one of the key factors for the success of the circuit design. The power diode typically employs a P + N-N + structure as shown in fig. 1, with the low doped region of the diode typically being driven to a large implant state when the device is in a forward biased state. The middle region in this state is the same as without doping (intrinsic) and therefore the P + N-N + diode PIN is commonly referred to as a PIN diode. The PIN diode is used as a bipolar device, the forward voltage drop of the PIN diode can be obviously reduced by a conductance modulation effect generated in the forward conduction process of the PIN diode, however, a large number of excess carriers exist in a drift region during turn-off, which causes unavoidable turn-off loss during turn-off, prolongs turn-off time, further influences the reverse recovery characteristic of the PIN diode, and is not beneficial to the application of the PIN diode in occasions such as high-speed rectification, fast recovery and the like. While the reverse recovery characteristics of PIN diodes are critical to power electronics systems.
Meanwhile, with the gradual maturity of power semiconductor technology, the characteristics of silicon-based power devices gradually approach the theoretical limit. Researchers strive to find better parameters in a narrow optimization space of a silicon-based power device and pay attention to excellent material characteristics of third-generation wide-bandgap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN) and the like in the fields of high power, high frequency, high temperature resistance, radiation resistance and the like. Among them, the silicon carbide power diode device is called a "green energy" device of "new energy revolution" by those in the industry because the silicon carbide, which is a wide bandgap semiconductor material, has a significant effect of reducing power loss. Besides, the silicon carbide material has many attractive properties, such as 10 times of the critical breakdown electric field strength of the silicon material, high thermal conductivity, large forbidden band width, high electron saturation drift velocity, etc., and these performance advantages make the silicon carbide material a hot research point for power semiconductor devices internationally. However, while the development of silicon carbide power diode devices is becoming mature, the disadvantages of wide bandgap semiconductor materials are also shown: the wide bandgap of the semiconductor material can cause a larger knee point voltage, taking silicon carbide as an example, the forward conduction voltage drop of the silicon carbide PIN diode device is about 3.1V, and the forward conduction voltage drop of the silicon PIN diode is only about 0.7V, so that compared with the silicon carbide PIN diode device, the conduction loss is obviously increased, the rectification efficiency is reduced, and the serious waste of energy resources is caused. This is contrary to the "green industry" concept that is highly emphasized by today's society.
Disclosure of Invention
In view of the above, the present invention aims to: aiming at the problems of larger conduction loss, poor reverse recovery characteristic and the like of a PIN diode in the prior art, the diode device structure capable of reducing forward conduction voltage and optimizing the reverse recovery characteristic is provided, and is suitable for various semiconductor materials; meanwhile, the invention also provides a preparation method of the diode device.
On one hand, the invention provides a diode device, the cellular structure of which comprises a metal cathode 5, an N + wide bandgap semiconductor substrate 4, an N-wide bandgap semiconductor epitaxial layer 3 and a metal anode 1 which are sequentially stacked from bottom to top; two sides of the top layer of the N-wide bandgap semiconductor epitaxial layer 3 are provided with groove structures, each groove structure comprises a P + wide bandgap semiconductor region 7 arranged at the bottom of each groove and a narrow bandgap semiconductor 6 arranged at the top of each groove, and the P + wide bandgap semiconductor region 7 is in direct contact with the narrow bandgap semiconductor 6; a P-type wide bandgap semiconductor body region 11 is further arranged between the trench structures on two sides of the top layer of the N-type wide bandgap semiconductor epitaxial layer 3, the top layer of the P-type wide bandgap semiconductor body region 11 is provided with a P + wide bandgap semiconductor contact region 10 and N + wide bandgap semiconductor source regions 9 arranged on two sides of the P + wide bandgap semiconductor contact region 10, and the P-type wide bandgap semiconductor epitaxial layer is characterized in that: the N + wide bandgap semiconductor source region 9, the P-type wide bandgap semiconductor body region 11 and part of the N-wide bandgap semiconductor epitaxial layer 3 are in contact with the narrow bandgap semiconductor 6 through the dielectric layer 8 on the side wall of the groove; the upper surfaces of the narrow bandgap semiconductor 6, the dielectric layer 8, the N + wide bandgap semiconductor source region 9 and the P + wide bandgap semiconductor contact region 10 are in contact with the metal anode 1; wherein: the narrow bandgap semiconductor 6, the dielectric layer 8, the N + wide bandgap semiconductor source region 9, the P-type wide bandgap semiconductor body region 11 and the N-wide bandgap semiconductor epitaxial layer 3 form a super barrier structure, and the narrow bandgap semiconductor 6 and the N-wide bandgap semiconductor epitaxial layer 3 form a heterojunction at a contact interface; the P-type wide bandgap semiconductor body region 11 and the N-wide bandgap semiconductor epitaxial layer 3, and the P + wide bandgap semiconductor region 7 and the N-wide bandgap semiconductor epitaxial layer 3 form PN junctions, respectively.
Further, the P + wide bandgap semiconductor region 7 may be shorted with the metal anode 1, or may be disposed in a floating state.
Further, the width of the P + wide bandgap semiconductor region 7 is larger than the width of the trench in the present invention.
Furthermore, the narrow bandgap semiconductor 6 of the invention further comprises a dielectric layer 8 which divides the narrow bandgap semiconductor 6 into two parts independent of each other, the narrow bandgap semiconductor 6 above the dielectric layer 8 is called a first narrow bandgap semiconductor, the narrow bandgap semiconductor 6 below the dielectric layer 8 is called a second narrow bandgap semiconductor, and the second narrow bandgap semiconductor is shorted with the metal anode 1 through ohmic contact.
Furthermore, when the narrow bandgap semiconductor 6 further has the dielectric layer 8 therein to separate the narrow bandgap semiconductor 6 into a first narrow bandgap semiconductor and a second narrow bandgap semiconductor, a metal anode region 1a is further provided between the P + wide bandgap semiconductor region 7 and the second narrow bandgap semiconductor in the present invention; ohmic contact is formed between the metal anode region 1a, the P + wide bandgap semiconductor region 7 and the second narrow bandgap semiconductor, and the metal anode region 1a and the metal anode 1 are equipotential.
Furthermore, in the invention, the P + wide bandgap semiconductor region 7 and the N-wide bandgap semiconductor epitaxial layer 3 form a super junction structure; according to the common knowledge of those skilled in the art, the P + wide bandgap semiconductor region 7 and the N-wide bandgap semiconductor epitaxial layer 3 satisfy the requirement of Qp ═ Qn.
Preferably, when the P + wide bandgap semiconductor region 7 and the N-wide bandgap semiconductor epitaxial layer 3 form a super junction structure, the doping concentration of the top layer of the N-wide bandgap semiconductor epitaxial layer 3 is higher than the doping concentration below the top layer.
Preferably, when the P + wide bandgap semiconductor region 7 and the N-wide bandgap semiconductor epitaxial layer 3 form a super junction structure, the doping concentration of the top layer of the P + wide bandgap semiconductor region 7 is higher than the doping concentration below the top layer.
According to the embodiment of the present invention, the material of the wide bandgap semiconductor is silicon carbide, and the material of the narrow bandgap semiconductor is silicon material, and according to the common general knowledge in the art, other combinations composed of the wide bandgap semiconductor material and the narrow bandgap semiconductor material are also suitable for the device structure provided by the present invention, and the present invention is not limited thereto.
Further, when the narrow bandgap semiconductor is made of a silicon material, the narrow bandgap semiconductor may be polysilicon or monocrystalline silicon, the polycrystalline silicon may be P-type polysilicon or N-type polysilicon, and the monocrystalline silicon may be P-type monocrystalline silicon or N-type monocrystalline silicon.
On the other hand, the invention provides a manufacturing method of a diode device, which is characterized by comprising the following steps:
step 1: selecting a wide bandgap semiconductor material as an N + wide bandgap semiconductor substrate 4 and an N-wide bandgap semiconductor epitaxial layer 3;
step 2: forming a P-type wide bandgap semiconductor body region 11 positioned above the N-wide bandgap semiconductor epitaxial layer 3 through an ion implantation process or an epitaxial process;
and step 3: forming N + wide bandgap semiconductor source regions 9 positioned on two sides of the top layer of the P-type wide bandgap semiconductor body region 11 through photoetching and ion implantation processes;
and 4, step 4: forming a P + wide bandgap semiconductor contact region 9 which is positioned on the top layer of the P type wide bandgap semiconductor body region 11 and two sides of which are contacted with the N + wide bandgap semiconductor source region 9 through photoetching and ion implantation processes;
and 5: forming grooves on two sides of the N-wide bandgap semiconductor epitaxial layer 3 through a groove etching process;
step 6: depositing and etching process or ion implantation process on the bottom of the groove or implanting P-type wide bandgap semiconductor material below the groove to form a P + wide bandgap semiconductor region 7;
and 7: depositing a narrow bandgap semiconductor material on the upper surface of the P + wide bandgap semiconductor region 7 through deposition and etching processes, removing redundant narrow bandgap semiconductor material through etching, and reserving a part of narrow bandgap semiconductor material at the bottom of the trench as a second narrow bandgap semiconductor;
and 8: forming a dielectric layer 8 on the surface and the side wall of the narrow bandgap semiconductor through a dry oxygen oxidation or deposition process;
and step 9: continuously depositing a narrow-bandgap semiconductor material on the dielectric layer 8 through a deposition and etching process, and removing redundant narrow-bandgap semiconductor material through etching to form a first narrow-bandgap semiconductor positioned on the dielectric layer 8, wherein the first narrow-bandgap semiconductor and the second narrow-bandgap semiconductor form a narrow-bandgap semiconductor 6 separated by the dielectric layer 8;
step 10: through deposition, photoetching and etching processes, a metal anode 1 is formed on the upper surfaces of the narrow bandgap semiconductor 6, the dielectric layer 8, the N + wide bandgap semiconductor source region 9 and the P + wide bandgap semiconductor contact region 10, and a metal cathode 5 is formed on the back surface of the turnover device, so that the manufacture of the device is completed.
According to the embodiment of the present invention, the material of the wide bandgap semiconductor is silicon carbide, and the material of the narrow bandgap semiconductor is silicon material, and according to the common general knowledge in the art, other combinations composed of the wide bandgap semiconductor material and the narrow bandgap semiconductor material are also suitable for the device structure provided by the present invention, and the present invention is not limited thereto.
Further, when the narrow bandgap semiconductor deposited in step 7 and step 9 is silicon, the semiconductor may be polysilicon or monocrystalline silicon, the polysilicon may be P-type polysilicon or N-type polysilicon, and the monocrystalline silicon may be P-type monocrystalline silicon or N-type monocrystalline silicon.
Further, when the narrow bandgap semiconductor is polysilicon, the operations of forming the dielectric layer 8 and the polysilicon in steps 8 and 9 may be replaced by the following operations: silicon nitride is deposited through the bottom of the trench and then thermal oxidation is performed. And then, etching the silicon nitride by using hot phosphoric acid, and finally forming the polycrystalline silicon in the groove by deposition and etching processes.
Further, step 9 is preceded by the following steps: and selectively removing the dielectric layer 8 on the surface of the narrow bandgap semiconductor through an etching process, so that the continuous narrow bandgap semiconductor 6 is formed in the subsequent manufacturing.
Further, the step 6 further includes, after depositing the P + wide bandgap semiconductor region 7, making the width of the P + wide bandgap semiconductor region 7 larger than the width of the trench through a thermal diffusion process.
Further, after forming the second narrow bandgap semiconductor in step 7, the method further includes forming a metal anode region 1a between the second narrow bandgap semiconductor and the P + wide bandgap semiconductor region 7 by adding trench etching, depositing metal, and removing excess metal by etching.
Further, the operations of forming the trench and the P + wide bandgap semiconductor region 7 in the steps 5 and 6 may be replaced by the following operations: the depth of the groove etching is deepened through multiple times of epitaxy, thermal diffusion and etching, so that the P + wide bandgap semiconductor region 7 and the N-wide bandgap semiconductor epitaxial layer 3 are distributed at intervals, and a super junction structure is formed by controlling the width and the doping concentration of the P + wide bandgap semiconductor region 7 and the N-wide bandgap semiconductor epitaxial layer 3.
Further, in the forming of the super junction structure, after the forming of the trench in the step 5, forming a heavily doped N-wide bandgap semiconductor epitaxial layer 3a on top of the N-wide bandgap semiconductor epitaxial layer 3 by an ion implantation process.
Further, in the above-described super junction structure, after the P + wide bandgap semiconductor region 7 is formed in step 5, forming a P + + wide bandgap semiconductor region 7a on top of the P + wide bandgap semiconductor region 7 by an ion implantation process is further included.
According to the invention, by reasonably improving the device structure, the narrow-bandgap semiconductor, the dielectric layer, the source region, the body region and the epitaxial layer form a super barrier structure, the narrow-bandgap semiconductor in the super barrier structure forms a heterojunction with the epitaxial layer, and the body region forms a PN junction with the epitaxial layer. Through the integration of the functional regions, the problems that the existing PIN diode device has large forward starting voltage (the silicon carbide PIN diode is about 3.1V, the reverse recovery capability is poor and the like) are solved.
The principles of the present invention will be explained in detail below by taking a diode device formed by using silicon carbide as an example for a wide bandgap semiconductor and polysilicon as an example for a narrow bandgap semiconductor, and those skilled in the art can easily obtain the principles of the device by combining other wide and narrow bandgap semiconductor materials according to the following disclosure.
In the diode device provided by the invention, the polycrystalline silicon, the dielectric layer and the P-type wide bandgap semiconductor body region form a metal (M) -insulator (I) -semiconductor (S) structure (hereinafter referred to as MIS structure), and parameters such as the doping concentration of the polycrystalline silicon, the thickness and the number of charges of the dielectric layer, the doping concentration of the P-type wide bandgap semiconductor body region and the like are adjusted through process control, so that the threshold voltage of the MIS structure is about 0.1V. When the voltage applied on the metal anode is close to 0.1V, a small part of carrier current flows through the N-wide bandgap semiconductor epitaxial layer, the P-type wide bandgap semiconductor body region and the N + wide bandgap semiconductor source region due to the existence of the current of the sub-threshold region of the MIS structure. The carrier current causes a voltage drop across the P-type wide bandgap semiconductor body. Meanwhile, at the other end of the dielectric layer (8), as the forward starting voltage of the Si/SiC heterojunction is greater than 0.1V, no current flows in the region where the polycrystalline silicon is located, namely the potential of the region where the polycrystalline silicon is located is the same everywhere. The potential on the two sides of the dielectric layer is gradually increased from top to bottom along the vertical direction of the device, and the difference enables the voltage on the metal anode not to be added to 0.1V (namely the gate voltage of the super barrier structure), so that the device can have obvious current passing, namely the conducting state. For a conventional power device, it is usually required to be above a higher voltage for normal operation, and the device structure proposed by the present invention has a turn-on voltage lower than 0.1V, which can be considered as close to 0V. Therefore, the device structure provided by the invention has absolute advantages in low-voltage application, and meanwhile, the device has the characteristic of high current density under normal working bias through structural improvement.
The diode device provided by the invention is provided with the groove type super barrier structure, the super barrier structure is provided with the heterojunction, and the super barrier structure and the heterojunction are provided with the multi-sub current, so that the on-state voltage drop which is the same as that of the traditional PIN diode can be obtained without an excessively high conductance modulation level. In other words, in the forward conduction mode, the stored charge of the device structure provided by the invention is far lower than that of the silicon carbide PIN diodeTherefore, the reverse recovery characteristic of the device can be optimized, and the reverse recovery charge Qrr of the device is reduced, so that the voltage drop V is reduced in the forward directionFA good compromise is obtained with the reverse recovery charge Qrr.
In the diode device provided by the invention, in a blocking state, the P + wide bandgap semiconductor region and the N-wide bandgap semiconductor epitaxial layer can form a PN junction withstand voltage, so that the voltage blocking capability of the diode device is basically the same as that of a silicon carbide PIN diode. But because of the extremely low leakage of the super barrier structure, the device structure provided by the invention has lower reverse leakage than the traditional silicon carbide PIN diode. Furthermore, the P + wide bandgap semiconductor region and the N-wide bandgap semiconductor epitaxial layer form a super junction structure, so that the voltage blocking capability of the device can be obviously improved, and the better compromise characteristic of forward voltage drop and breakdown voltage is obtained.
The invention has the beneficial effects that:
the diode device provided by the invention has a forward starting voltage close to 0V, so that the rectification efficiency of the diode is obviously improved, the on-state loss of the device is reduced, and the energy resource is saved.
Secondly, the diode device provided by the invention has the same forward conduction voltage drop VFAnd the conductivity modulation level is lower, so that the number of stored charges is reduced, the reverse recovery time is shortened, the reverse recovery time is reduced, and the reverse recovery characteristic of the device is optimized. Namely, the diode device provided by the invention has a forward conduction voltage drop VFA good compromise is obtained with the reverse recovery charge Qrr.
And thirdly, the diode device provided by the invention has lower electric leakage on the premise of not influencing withstand voltage, thereby having higher reliability and larger safe working area.
The diode device provided by the invention adopts a super junction structure, the voltage blocking capability of the device is obviously improved, and meanwhile, as the low-doped i region does not exist, the diode device can process larger di/dt working conditions and has stronger surge current resistance.
The diode device is convenient and quick in practical application and flexible in application, and the applied functional module can be selected according to specific application conditions, namely a unipolar working mode or a bipolar working mode can be selected to adapt to different application occasions.
Drawings
FIG. 1 is a schematic diagram of a cell structure of a conventional silicon carbide PIN diode device;
fig. 2 is a schematic diagram of a cell structure of a diode device provided in embodiment 1 of the present invention;
fig. 3 is a schematic diagram of a cell structure of a diode device provided in embodiment 2 of the present invention;
fig. 4 is a schematic diagram of a cell structure of a diode device provided in embodiment 3 of the present invention;
fig. 5 is a schematic diagram of a cell structure of a diode device provided in embodiment 4 of the present invention;
FIG. 6 is a schematic diagram showing the arrangement of the metal anode region in three-dimensional space in example 4 of the present invention;
fig. 7 is a schematic diagram of a cell structure of a diode device provided in embodiment 5 of the present invention;
fig. 8 is a schematic diagram of a cell structure of a diode device provided in embodiment 6 of the present invention;
fig. 9 is a functional region division schematic diagram of a diode device provided in embodiment 1 of the present invention;
fig. 10 is a schematic diagram of the potential distribution on both sides of the dielectric layer in the diode device provided in embodiment 1 of the present invention;
fig. 11 is an I-V characteristic curve of each functional region in the diode device provided in embodiment 1 of the present invention;
fig. 12 is an I-V characteristic curve of a diode device provided in embodiment 1 of the present invention;
fig. 13 is a schematic view of a substrate and an epitaxial layer of a diode device provided in embodiment 1 of the present invention;
fig. 14 is a schematic diagram of a body region formed in the diode device provided in embodiment 1 of the present invention;
fig. 15 is a schematic view of a source region formed by the diode device provided in embodiment 1 of the present invention;
fig. 16 is a schematic view of a contact region formed in the diode device provided in embodiment 1 of the present invention;
fig. 17 is a schematic view of a trench formed in the diode device provided in embodiment 1 of the present invention;
fig. 18 is a schematic view of a diode device according to embodiment 1 of the present invention, in which a P + wide bandgap semiconductor region is formed;
fig. 19 is a schematic diagram of a diode device according to embodiment 1 of the present invention, in which a second narrow bandgap semiconductor is formed;
fig. 20 is a schematic view of a diode device formation dielectric layer provided in embodiment 1 of the present invention;
fig. 21 is a schematic diagram of a diode device selectively etching a dielectric layer according to embodiment 1 of the present invention;
fig. 22 is a schematic view of a diode device according to embodiment 1 of the present invention, in which a first narrow bandgap semiconductor is formed;
fig. 23 is a schematic diagram of forming a metal anode and a metal cathode of the diode device provided in embodiment 1 of the present invention.
The numbering in the figures means the following:
1 is a metal anode, 1a is a metal anode region, 2 is an anode P + semiconductor region, 3 is an N-silicon carbide epitaxial layer, 3a is a heavily doped N-silicon carbide epitaxial layer, 3b is a lightly doped N-silicon carbide epitaxial layer, 4 is an N + silicon carbide substrate, 5 is a metal cathode, 6 is polysilicon, 7 is a P + silicon carbide region, 7a is a P + + silicon carbide region, 8 is a dielectric layer, 9 is an N + silicon carbide source region, 10 is a P + silicon carbide contact region, and 11 is a P-type silicon carbide body region; a is a super barrier structure; b is a heterojunction; and C is a PN junction.
Detailed Description
The structure and fabrication method of the device are described in detail below with reference to the drawings, so that those skilled in the art can clearly understand the technical scheme and principle of the present invention. The specific examples are provided for illustration only and are not intended to limit the scope of the invention.
Example 1:
a diode device has a cellular structure as shown in figure 2, and comprises a metal cathode 5, an N + silicon carbide substrate 4, an N-silicon carbide epitaxial layer 3 and a metal anode 1 which are sequentially stacked from bottom to top; two sides of the top layer of the N-silicon carbide epitaxial layer 3 are provided with a trench structure, the trench structure comprises a P + silicon carbide region 7 arranged at the bottom of the trench and polysilicon 6 arranged at the top of the trench, and the P + silicon carbide region 7 is in direct contact with the polysilicon 6; still have P type carborundum somatic region 11 between the trench structure of 3 top layers both sides of N-carborundum epitaxial layer, the top layer of P type carborundum somatic region 11 has P + carborundum contact zone 10 and locates the N + carborundum source zone 9 of P + carborundum contact zone 10 both sides, its characterized in that: the N + silicon carbide source region 9, the P-type silicon carbide body region 11 and part of the N-silicon carbide epitaxial layer 3 are in contact with the polycrystalline silicon 6 through the dielectric layer 8 on the side wall of the groove; the upper surfaces of the polycrystalline silicon 6, the dielectric layer 8, the N + silicon carbide source region 9 and the P + silicon carbide contact region 10 are in contact with the metal anode 1; wherein: the polycrystalline silicon 6, the dielectric layer 8, the N + silicon carbide source region 9, the P-type silicon carbide body region 11 and the N-silicon carbide epitaxial layer 3 form a super barrier structure, and the polycrystalline silicon 6 and the N-silicon carbide epitaxial layer 3 form a heterojunction at a contact interface; the P-type silicon carbide body region 11 and the N-silicon carbide epitaxial layer 3 and the P + silicon carbide region 7 and the N-silicon carbide epitaxial layer 3 form PN junctions, respectively.
In this embodiment, the wide bandgap semiconductor is silicon carbide, the narrow bandgap semiconductor is polysilicon, and parameters of each structure are given below by taking a 1200V N channel diode device as an example: the thickness of the metal anode 1 and the metal cathode 5 is 0.5-2 μm, and the width is 0.6-2 μm; the doping concentration of the N + silicon carbide substrate 4 is 5e 18-9 e18/cm3The thickness is 0.5 to 1.2 μm, and the width is 0.5 to 2 μm; the doping concentration of the N-silicon carbide epitaxial layer 3 is 2e 15-8 e15/cm3The thickness is 5-7 μm, and the width is 0.5-2 μm; the P + silicon carbide region 7 has a thickness of about 0.8 to 1.1 μm and a doping concentration of about 1e19 to 7e19/cm3The width is about 0.3-0.5 μm; the width of the polysilicon 6 is about 0.3-0.5 μm, and the thickness is about 0.8-1.6 μm; the thickness of the dielectric layer 8 is about 10 nm-50 nm; the P-SiC body region 11 has a thickness of about 0.3 μm to about 0.4 μm, a width of about 0.2 μm to about 0.4 μm, and a doping concentration of about 1e16 to about 1e17/cm3(ii) a The N + silicon carbide source region 9 has a thickness of about 0.2 μm to about 0.3 μm, a width of about 0.2 μm to about 0.4 μm, and a doping concentration of about 1e18 to about 6e18/cm3。
According to the invention, the structure of the device is reasonably improved to form three functional regions of a super barrier structure, a heterojunction and a PN junction, so that the comprehensive performance of the device is obviously superior to that of the traditional PIN diode.
The principles and features of the present invention will be described in detail below with reference to specific embodiments:
in this embodiment, an N-channel diode device formed by using silicon carbide as a wide bandgap semiconductor material and polysilicon as a narrow bandgap semiconductor material is taken as an example to explain the principle and characteristics of the present invention in detail, and a person skilled in the art can derive the principle of a P-channel diode device and the principle of a diode device formed by combining the remaining wide and narrow bandgap semiconductor materials according to the following disclosure:
aiming at the problems of large forward starting voltage (about 3.1V of a silicon carbide PIN diode), poor reverse recovery capability and the like of the traditional PIN diode, the invention reasonably improves the structure of the device to optimize the performance. For convenience of explanation of the principle of the present invention, three functional regions to be mentioned later and position points a1, a2, b1 and b2 on both sides of the dielectric layer 8 are respectively labeled as shown in fig. 9.
In the diode device provided by the invention, the polycrystalline silicon 6, the dielectric layer 8 and the P-type silicon carbide body region 11 form a metal M-insulator I-semiconductor S structure which is referred to as an MIS structure below, and parameters such as the doping concentration of the polycrystalline silicon 6, the thickness and the charge number of the dielectric layer 8, the doping concentration of the P-type silicon carbide body region 11 and the like are adjusted through process control, so that the threshold voltage of the MIS structure is about 0.1V. When the voltage applied to the metal anode 1 is close to 0.1V, a small part of the carrier current flows through the N-silicon carbide epitaxial layer 3, the P-type silicon carbide body region 11 and the N + silicon carbide source region 9 due to the presence of the current in the sub-threshold region of the MIS structure. This carrier current causes a voltage drop across the P-type silicon carbide body region 11. Meanwhile, at the other end of the dielectric layer 8, since the Si/SiC heterojunction is greater than the forward turn-on voltage of 0.1V, it can be considered that no current flows through the region where the polysilicon 6 is located, i.e., the potential of the region where the polysilicon 6 is located is the same everywhere. Fig. 10 is a graph showing potential distribution on both sides of the dielectric layer 8, in which a1 and a2 have almost no potential difference, and the potential difference increases from top to bottom in the vertical direction from point a to point b. This difference allows the voltage on the metal anode 1 to pass through a significant current, i.e., the on-state, without adding to 0.1V, i.e., the gate voltage of the super barrier structure. For a traditional power device, the normal operation of the device generally needs to be above a higher voltage, and the device structure provided by the invention has a starting voltage lower than 0.1V, which can be considered as close to the starting voltage of 0V, so that the device structure provided by the invention has absolute advantages in low-voltage application, and meanwhile, the device provided by the invention has the characteristic of large current density under normal operation bias voltage through structural improvement.
In the case of neglecting the resistance, I-V characteristic curves of the single functional region are shown in fig. 11, and in this embodiment, for convenience of explanation, P-type polysilicon is taken as an example, and a person skilled in the art can derive the principle of N-type polysilicon on the basis of this, as shown in fig. 9, in which a is a super barrier structure, B is a Si/SiC heterojunction, and C is a silicon carbide PN junction. A. B, C the forward opening voltage drops of three functional regions, i.e. super barrier structure, Si/SiC heterojunction and silicon carbide PN junction are about 0V, 1.1V and 3.1V respectively. Along with the increase of the voltage applied to the metal anode 1, the voltage drop at the two ends of the Si/SiC heterojunction and the silicon carbide PIN diode is increased, and when the voltages at the two ends of the Si/SiC heterojunction and the silicon carbide PIN diode reach 1.1V and 3.1V respectively, the Si/SiC heterojunction and the silicon carbide PIN diode are respectively conducted. For the sake of explanation in principle, assuming that the Si/SiC heterojunction conducts before the silicon carbide PIN diode, the I-V characteristic curve of the diode device is shown in fig. 12. Curve a in fig. 12 represents the case where only the super barrier structure is on; the curve A + B represents the conduction condition of the super barrier structure and the Si/SiC heterojunction; and the curve A + B + C represents the condition that the super barrier structure, the Si/SiC heterojunction and the silicon carbide PN junction are both conducted. Although the diode device provided by the invention still belongs to a bipolar device under the condition that the super barrier structure, the heterojunction and the PN junction are conducted, namely the conductance modulation effect can occur under the condition of large injection, the diode device provided by the invention has a lower conductance modulation level under the same voltage drop. As is well known to those skilled in the art, P-silicon carbide body regions 11 and N-silicon carbideEpitaxial layer 3 and P + silicon carbide region 7 and N-silicon carbide epitaxial layer 3 form a bipolar path that exhibits a conductivity modulation effect at higher bias voltages, requiring a sufficiently high level of conductivity modulation to reduce the greater resistance in the epitaxial layer for a silicon carbide PIN diode. However, due to the groove type super barrier diode structure and the existence of Si/SiC heterojunction multi-sub-current, the on-state voltage drop of the device can be the same as that of the traditional silicon carbide PIN diode without excessively high conductance modulation level. In other words, the stored charge of the diode device in the forward conduction mode is far lower than that of the traditional PIN diode with the same specification. Therefore, the structure provided by the invention optimizes the reverse recovery characteristic of the device, reduces the turn-off loss of the device and further reduces the voltage drop V in the forward conductionFA good compromise is obtained with the reverse recovery charge Qrr.
In addition, under the blocking state of the device, the PN junction formed by the P + silicon carbide region 7 and the N-silicon carbide epitaxial layer 3 is resistant to voltage, so that the voltage blocking capability of the device is basically the same as that of the traditional PIN diode with the same specification, and the device has lower reverse leakage capability compared with the traditional PIN diode with the same specification due to extremely low leakage of the super barrier structure in the device.
Example 2:
the schematic diagram of the cell structure of the diode device provided by this embodiment is shown in fig. 3, and the difference compared with embodiment 1 is that: the bottom end of the dielectric layer 8 extends transversely to separate the polycrystalline silicon 6 into two mutually independent parts, the polycrystalline silicon 6 below the dielectric layer 8 is in short circuit with the metal anode 1, the potential of the polycrystalline silicon 6 is always consistent with the potential of the metal anode 1 in this way, and the potential of the polycrystalline silicon 6 is prevented from changing after the heterojunction is conducted, so that the fluctuation influence is generated on the I-V characteristic of the super barrier structure. This embodiment improves the reliability of the device in practical use as compared with embodiment 1.
Example 3:
the schematic diagram of the cell structure of the diode device provided in this embodiment is shown in fig. 4, and the difference compared with embodiment 2 is that: the lateral width of the P + silicon carbide region 7 is made larger. Compared with embodiment 2, the larger the lateral width of the P + silicon carbide region 7 is, the stronger the electric field shielding effect on the region above the P + silicon carbide region 7 is when the device is in the blocking state, which not only protects the heterojunction, the super-barrier structure and other structures, but also improves the voltage withstanding performance of the device. It is to be noted that the wider the width of the P + silicon carbide region 7, the greater the on-resistance when the device is operating in the forward direction. The width of the P + silicon carbide region 7 needs to be balanced between forward and reverse operation.
In this embodiment, taking an N-channel diode device as an example, the width of the P + silicon carbide contact region is 0.4 μm to 0.7 μm.
Example 4:
the schematic diagram of the cell structure of the diode device provided in this embodiment is shown in fig. 5, and the difference compared with embodiment 2 is that: and a metal anode region 1a which is short-circuited with the metal anode 1 is arranged between the P + silicon carbide region 7 and the polysilicon 6 below the dielectric layer 8, and the metal anode region 1a forms ohmic contact with the P + silicon carbide region 7 and the polysilicon 6 below the dielectric layer 8. Fig. 6 shows a schematic perspective view of a metal anode region 1a, in general practical applications, the back surface of the cell shown in fig. 5 is connected with the device surface metal by performing trench etching and depositing metal, and the metal anode region 1a is in contact with the anode metal 1 on the back surface of the cell to realize equipotential.
In the embodiment, the arrangement of the metal anode region 1a is beneficial to improving the performance of the device, and in the forward working mode, the metal anode region 1a can reduce the on-resistance of the device, so that the on-loss of the device is reduced; under the reverse working mode, the metal anode region 1a can improve the shielding capability of the P + silicon carbide region 7 on an electric field, so that the voltage resistance of the device is improved.
Example 5:
the difference between the cell structure of the diode device provided by this embodiment and that of embodiment 1 is: the P + silicon carbide region 7 forms a super junction structure with the N-silicon carbide epitaxial layer 3. By controlling and adjusting the process parameters, the N columns, i.e., the N-silicon carbide epitaxial layer 3, and the P columns, i.e., the P + silicon carbide regions 7 satisfy Qn — Qp.
The super junction structure introduced in the embodiment can improve the voltage blocking capability of the device by optimizing the electric field distribution in the blocking mode. Meanwhile, the super junction structure can improve epitaxial concentration, so that the device can bear larger di/dt impact, and the device has higher surge current resistance.
Example 6:
the schematic diagram of the cell structure of the diode device provided by this embodiment is shown in fig. 7, and the difference compared with embodiment 5 is that: a heavily doped N-silicon carbide epitaxial layer 3a is formed on top of the N-silicon carbide epitaxial layer 3 and below the top thereof.
Example 7:
the schematic diagram of the cell structure of the diode device provided in this embodiment is shown in fig. 8, and the difference compared with embodiment 6 is that: the top of the P + silicon carbide region 7 forms a more highly doped P + + silicon carbide region 7a than below the top thereof.
Compared with embodiment 6, the present embodiment can protect the super barrier structure and the heterojunction above the N-pillar and the P-pillar better under the condition that the N-pillar and the P-pillar are fully depleted.
Example 8:
in this embodiment, a 1200V N trench diode device provided in embodiment 1 is taken as an example, the manufacturing method thereof is described in detail, and embodiments 2 to 6 are described based on this example, and according to the common general knowledge in the art, a person skilled in the art can prepare devices with different performance parameters according to actual requirements.
A manufacturing method of a diode device is characterized by comprising the following steps:
step 1: as shown in fig. 13, a silicon carbide wafer with appropriate resistivity and thickness is selected as the N-silicon carbide region epitaxial layer 3 and the N + silicon carbide substrate 4, wherein the doping concentration of the N + silicon carbide substrate 4 is 5e 18-9 e18/cm3The thickness is 0.5 to 1.2 μm, and the width is 0.5 to 2 μm; the doping concentration of the N-silicon carbide epitaxial layer 3 is 2e 15-8 e15/cm3The thickness is 5-7 μm, and the width is 0.5-2 μm;
step 2: performing aluminum ion implantation on the N-silicon carbide epitaxial layer 3 by a high-energy ion implantation process, wherein the implantation energy is about 1500-2000 keV, and the thickness is about 0.3-0.4 μm, and the width is about 0.3-0.4 μmThe degree is about 0.2 μm to 0.4 μm, and the doping concentration is about 1e16 to 1e17/cm3P-silicon carbide body region 11 as shown in fig. 14;
and step 3: through the working procedures of photoetching, ion implantation and the like, phosphorus ion implantation is carried out on the top layer of the P-silicon carbide body region 11 by using an NSD mask, the implantation energy is about 1300-1700 keV, the thickness is about 0.2-0.3 mu m, the width is about 0.2-0.4 mu m, the doping concentration is about 1e 18-6 e18/cm3As shown in fig. 15, the N + silicon carbide source region 9 of (a);
and 4, step 4: performing aluminum ion implantation at 450-550 deg.C in the center of the N + silicon carbide source region 9 by using PSD mask, wherein the implantation energy is about 1300-1700 keV, the thickness is about 0.3-0.4 μm, the width is about 0.2-0.4 μm, and the doping concentration is about 1e 16-1 e17/cm3Then activating the impurities at 1600-1700 c, as shown in fig. 16, in the P + silicon carbide contact region 10;
and 5: through a groove etching process, a groove with the width of 0.3-0.5 μm and the depth of 1.1-2 μm is etched by using a Trench mask, as shown in FIG. 17;
step 6: depositing a P-type silicon carbide material at the bottom of the trench by deposition and etching processes, and removing unnecessary P-type silicon carbide semiconductor by etching to form a P-type silicon carbide semiconductor with a thickness of about 0.8-1.1 μm and a doping concentration of about 1e 19-7 e19/cm3A P + silicon carbide region 7 having a width of about 0.3 μm to about 0.5 μm, as shown in FIG. 18;
and 7: through deposition and etching processes, depositing polycrystalline silicon 6 on the bottom of the trench, namely the surface of the P + silicon carbide region 7, removing redundant polycrystalline silicon 6 through etching, and reserving a part of polycrystalline silicon 6 at the bottom of the trench, as shown in FIG. 19;
and 8: forming a dielectric layer 8 with a thickness of about 10nm to 50nm by a dry oxygen oxidation process at a temperature of 1100 ℃ to 1300 ℃, as shown in fig. 20;
and step 9: selectively etching the dielectric layer 8 on the surface of the polysilicon 6 by an etching process, and leaving the dielectric layer 8 with the thickness of about 10 nm-50 nm on the side wall of the groove, as shown in FIG. 21;
step 10: depositing polycrystalline silicon 6 in the trench by deposition and etching processes, and removing redundant polycrystalline silicon 6 by etching to obtain polycrystalline silicon 6 with the width of about 0.3-0.5 μm and the thickness of about 0.8-1.6 μm, as shown in FIG. 22;
step 11: and forming a metal anode 1 and a metal cathode 5 with the thickness of 0.5-2.0 microns and the width of 0.6-2.0 microns by deposition, photoetching and etching processes, and finishing the manufacture of the device as shown in figure 23.
Further, in this embodiment, the narrow bandgap semiconductor deposited in step 7 and step 9 is a polysilicon material, and the polysilicon material may be P-type polysilicon or N-type polysilicon. The method can also be realized by adopting monocrystalline silicon, and the monocrystalline silicon can be P-type monocrystalline silicon or N-type monocrystalline silicon.
Further, the operation of forming the dielectric layer 8 and the polysilicon 6 in steps 8 and 9 in this embodiment may be replaced by the following operation: silicon nitride is deposited through the bottom of the trench and then thermal oxidation is performed. Then, the silicon nitride is etched by hot phosphoric acid, and finally, the polycrystalline silicon 6 in the groove is formed through deposition and etching processes.
Further, in step 6 of this embodiment, after depositing the P + silicon carbide region 7, the step further includes making the width of the P + silicon carbide region 7 greater than the width of the trench through a thermal diffusion process, so as to obtain the device structure shown in fig. 4.
Further, after the step 7 of forming the polysilicon 6 located at the bottom of the trench, a metal anode region 1a is formed between the polysilicon 6 and the P + silicon carbide region 7 by adding trench etching, depositing metal, and removing excess metal by etching, so as to obtain the device structure shown in fig. 5.
Further, the operation of forming the trench and the P + silicon carbide region 7 in the steps 5 and 6 may be replaced by the following operation: the depth of the trench etching is deepened through multiple times of epitaxy, thermal diffusion and etching, so that the P + silicon carbide region 7 and the N-silicon carbide epitaxial layer 3 are in phase-to-phase distribution, a super junction structure is formed by controlling the width and the doping concentration of the P + silicon carbide region 7 and the N-silicon carbide epitaxial layer 3, and further, when the super junction structure is formed, after the N-silicon carbide epitaxial layer 3 is formed in the step 5, a heavily doped N-silicon carbide epitaxial layer 3a is formed on the top of the N-silicon carbide epitaxial layer 3 through an ion implantation process, so that the device structure shown in fig. 7 can be obtained.
Further, when the super junction structure is formed, after the P + silicon carbide region 7 is formed in step 5, forming a P + + silicon carbide region 7a on top of the P + silicon carbide region 7 by an ion implantation process is further included, so that the device structure shown in fig. 8 can be obtained.
It should also be claimed that: as can be seen from the basic knowledge in the art, the wide bandgap semiconductor and the narrow bandgap semiconductor materials used in the diode device structure and the fabrication method of the diode device structure disclosed in the present invention are not limited to the silicon carbide and the silicon material disclosed in the present embodiment, and other combinations composed of the wide bandgap semiconductor material and the narrow bandgap semiconductor material are also suitable for the device structure provided in the present invention, and the present invention is not limited thereto; the dielectric layer may be formed of silicon dioxide (SiO2) or silicon nitride (Si)3N4) Hafnium oxide (HfO)2) Aluminum oxide (Al)2O3) And the like, any suitable high-K dielectric material; meanwhile, the specific implementation mode of the manufacturing process can be adjusted according to actual needs.
Claims (10)
1. A diode device comprises a cellular structure, a metal cathode (5), an N + wide bandgap semiconductor substrate (4), an N-wide bandgap semiconductor epitaxial layer (3) and a metal anode (1) which are sequentially stacked from bottom to top; two sides of the top layer of the N-wide bandgap semiconductor epitaxial layer (3) are provided with groove structures, each groove structure comprises a P + wide bandgap semiconductor region (7) arranged at the bottom of each groove and a narrow bandgap semiconductor (6) arranged at the top of each groove, and the P + wide bandgap semiconductor region (7) is in direct contact with the narrow bandgap semiconductor (6); the P-type wide bandgap semiconductor body region (11) is further arranged between the groove structures on the two sides of the top layer of the N-type wide bandgap semiconductor epitaxial layer (3), the top layer of the P-type wide bandgap semiconductor body region (11) is provided with a P + wide bandgap semiconductor contact region (10) and an N + wide bandgap semiconductor source region (9) arranged on the two sides of the P + wide bandgap semiconductor contact region (10), and the P-type wide bandgap semiconductor epitaxial layer is characterized in that: the N + wide bandgap semiconductor source region (9), the P-type wide bandgap semiconductor body region (11) and part of the N-wide bandgap semiconductor epitaxial layer (3) are in contact with the narrow bandgap semiconductor (6) through a dielectric layer (8) on the side wall of the groove; the upper surfaces of the narrow bandgap semiconductor (6), the dielectric layer (8), the N + wide bandgap semiconductor source region (9) and the P + wide bandgap semiconductor contact region (10) are in contact with the metal anode (1); wherein: the narrow bandgap semiconductor (6), the dielectric layer (8), the N + wide bandgap semiconductor source region (9), the P-type wide bandgap semiconductor body region (11) and the N-wide bandgap semiconductor epitaxial layer (3) form a super barrier structure, and the narrow bandgap semiconductor (6) and the N-wide bandgap semiconductor epitaxial layer (3) form a heterojunction at a contact interface; PN junctions are respectively formed by the P type wide bandgap semiconductor body region (11) and the N-wide bandgap semiconductor epitaxial layer (3) as well as the P + wide bandgap semiconductor region (7) and the N-wide bandgap semiconductor epitaxial layer (3).
2. A diode device according to claim 1, wherein: the width of the P + wide bandgap semiconductor region (7) is greater than the width of the trench.
3. A diode device according to claim 1, wherein: the narrow-band gap semiconductor (6) is further provided with a dielectric layer (8) which separates the narrow-band gap semiconductor (6) into a first narrow-band gap semiconductor and a second narrow-band gap semiconductor which are mutually independent, and the first narrow-band gap semiconductor is in short circuit with the metal anode (1) through ohmic contact.
4. A diode device according to claim 3, wherein: and a metal anode region (1a) which forms ohmic contact with the P + wide bandgap semiconductor region (7) and the second narrow bandgap semiconductor is also arranged between the P + wide bandgap semiconductor region (7) and the second narrow bandgap semiconductor, and the metal anode region (1a) is equipotential with the metal anode (1).
5. A diode device according to claim 1, wherein: the P + wide bandgap semiconductor region (7) and the N-wide bandgap semiconductor epitaxial layer (3) form a super junction structure.
6. A diode device according to claim 5, wherein: the doping concentration of the top layer of the N-wide bandgap semiconductor epitaxial layer (3) is greater than that below the top layer.
7. A diode device according to claim 5 or 6, wherein: the doping concentration of the top layer of the P + wide bandgap semiconductor region (7) is greater than the doping concentration below the top layer.
8. A diode device according to claim 1, wherein: the P + wide bandgap semiconductor region (7) is in short circuit with the metal anode (1) or the P + wide bandgap semiconductor region (7) is arranged in a floating mode.
9. A manufacturing method of a diode device is characterized by comprising the following steps:
step 1: selecting a wide bandgap semiconductor material as an N + wide bandgap semiconductor substrate (4) and an N-wide bandgap semiconductor epitaxial layer (3);
step 2: forming a P-type wide bandgap semiconductor body region (11) positioned above the N-wide bandgap semiconductor epitaxial layer (3) through an ion implantation process or an epitaxial process;
and step 3: forming N + wide bandgap semiconductor source regions (9) positioned on two sides of the top layer of the P-type wide bandgap semiconductor body region (11) through photoetching and ion implantation processes;
and 4, step 4: forming a P + wide bandgap semiconductor contact region (10) which is positioned on the top layer of the P type wide bandgap semiconductor body region (11) and two sides of which are contacted with the N + wide bandgap semiconductor source region (9) through photoetching and ion implantation processes;
and 5: forming grooves on two sides of the N-wide bandgap semiconductor epitaxial layer (3) through a groove etching process;
step 6: depositing and etching process or ion implantation process on the bottom of the groove or implanting P-type wide bandgap semiconductor material below the groove to form a P + wide bandgap semiconductor region (7);
and 7: depositing a narrow-bandgap semiconductor material on the upper surface of the P + wide-bandgap semiconductor region (7) through deposition and etching processes, removing redundant narrow-bandgap semiconductor material through etching, and reserving a part of narrow-bandgap semiconductor material at the bottom of the groove to be used as a second narrow-bandgap semiconductor;
and 8: forming a dielectric layer (8) on the surface and the side wall of the narrow bandgap semiconductor through a dry oxygen oxidation or deposition process;
and step 9: continuously depositing a narrow-bandgap semiconductor material on the dielectric layer (8) through deposition and etching processes, and removing redundant narrow-bandgap semiconductor material through etching to form a first narrow-bandgap semiconductor positioned on the dielectric layer (8), wherein the first narrow-bandgap semiconductor and the second narrow-bandgap semiconductor form a narrow-bandgap semiconductor (6) separated by the dielectric layer (8);
step 10: through deposition, photoetching and etching processes, a metal anode (1) is formed on the upper surfaces of a narrow bandgap semiconductor (6), a dielectric layer (8), an N + wide bandgap semiconductor source region (9) and a P + wide bandgap semiconductor contact region (10), and a metal cathode (5) is formed on the back surface of the turnover device, so that the manufacture of the device is completed.
10. The method of claim 9, wherein: the step 9 further comprises the following operations: and selectively removing the dielectric layer (8) on the surface of the narrow-bandgap semiconductor through an etching process.
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